Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
Paul Burton | 7a9d109 | 2013-11-09 10:22:08 +0000 | [diff] [blame] | 6 | #ifndef _MALTA_CONFIG_H |
| 7 | #define _MALTA_CONFIG_H |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 8 | |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 9 | /* |
| 10 | * System configuration |
| 11 | */ |
Paul Burton | 7a9d109 | 2013-11-09 10:22:08 +0000 | [diff] [blame] | 12 | #define CONFIG_MALTA |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 13 | |
Gabor Juhos | ab41305 | 2013-10-24 14:32:00 +0200 | [diff] [blame] | 14 | #define CONFIG_MEMSIZE_IN_BYTES |
| 15 | |
Gabor Juhos | feaa606 | 2013-05-22 03:57:42 +0000 | [diff] [blame] | 16 | #define CONFIG_PCI_GT64120 |
Paul Burton | baf37f0 | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 17 | #define CONFIG_PCI_MSC01 |
Gabor Juhos | f195749 | 2013-05-22 03:57:44 +0000 | [diff] [blame] | 18 | #define CONFIG_PCNET |
Paul Burton | e0878af | 2013-11-08 11:18:52 +0000 | [diff] [blame] | 19 | #define CONFIG_PCNET_79C973 |
| 20 | #define PCNET_HAS_PROM |
Gabor Juhos | feaa606 | 2013-05-22 03:57:42 +0000 | [diff] [blame] | 21 | |
Paul Burton | 3ced12a | 2013-11-08 11:18:55 +0000 | [diff] [blame] | 22 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 |
| 23 | |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 24 | /* |
| 25 | * CPU Configuration |
| 26 | */ |
| 27 | #define CONFIG_SYS_MHZ 250 /* arbitrary value */ |
| 28 | #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 29 | |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 30 | /* |
| 31 | * Memory map |
| 32 | */ |
Gabor Juhos | 10473d0 | 2013-11-12 16:47:32 +0100 | [diff] [blame] | 33 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 34 | |
Paul Burton | 0f832b9 | 2016-05-26 14:49:36 +0100 | [diff] [blame] | 35 | #ifdef CONFIG_64BIT |
| 36 | # define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 |
| 37 | #else |
| 38 | # define CONFIG_SYS_SDRAM_BASE 0x80000000 |
| 39 | #endif |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 40 | #define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024) |
| 41 | |
| 42 | #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 |
| 43 | |
Paul Burton | 0f832b9 | 2016-05-26 14:49:36 +0100 | [diff] [blame] | 44 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000) |
| 45 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) |
| 46 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x00800000) |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 47 | |
| 48 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) |
| 49 | #define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) |
Paul Burton | 67d4752 | 2013-11-26 17:45:28 +0000 | [diff] [blame] | 50 | #define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 51 | |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 52 | /* |
| 53 | * Serial driver |
| 54 | */ |
Paul Burton | 2e7eb12 | 2016-05-17 07:43:27 +0100 | [diff] [blame] | 55 | #define CONFIG_SYS_NS16550_PORT_MAPPED |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 56 | |
| 57 | /* |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 58 | * Flash configuration |
| 59 | */ |
Paul Burton | 0f832b9 | 2016-05-26 14:49:36 +0100 | [diff] [blame] | 60 | #ifdef CONFIG_64BIT |
| 61 | # define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000 |
| 62 | #else |
| 63 | # define CONFIG_SYS_FLASH_BASE 0xbe000000 |
| 64 | #endif |
Gabor Juhos | 52caee0 | 2013-05-22 03:57:39 +0000 | [diff] [blame] | 65 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 66 | #define CONFIG_SYS_MAX_FLASH_SECT 128 |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 67 | |
| 68 | /* |
Paul Burton | fba6f45 | 2013-11-08 11:18:56 +0000 | [diff] [blame] | 69 | * Environment |
| 70 | */ |
Paul Burton | fba6f45 | 2013-11-08 11:18:56 +0000 | [diff] [blame] | 71 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
| 72 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
| 73 | #define CONFIG_ENV_ADDR \ |
| 74 | (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE) |
| 75 | |
| 76 | /* |
Paul Burton | ba21a45 | 2015-01-29 10:38:20 +0000 | [diff] [blame] | 77 | * IDE/ATA |
| 78 | */ |
| 79 | #define CONFIG_SYS_IDE_MAXBUS 1 |
| 80 | #define CONFIG_SYS_IDE_MAXDEVICE 2 |
| 81 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS |
| 82 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0 |
| 83 | #define CONFIG_SYS_ATA_DATA_OFFSET 0 |
| 84 | #define CONFIG_SYS_ATA_REG_OFFSET 0 |
| 85 | |
| 86 | /* |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 87 | * Commands |
| 88 | */ |
Gabor Juhos | feaa606 | 2013-05-22 03:57:42 +0000 | [diff] [blame] | 89 | |
Paul Burton | 7a9d109 | 2013-11-09 10:22:08 +0000 | [diff] [blame] | 90 | #endif /* _MALTA_CONFIG_H */ |