blob: 07384234c95deb2428bd6498927bf1a76b5c1a32 [file] [log] [blame]
Marian Balakowicze6f2e902005-10-11 19:09:42 +02001/*
2 * (C) Copyright 2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * TQM8349 board configuration file
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
Marian Balakowicze6f2e902005-10-11 19:09:42 +020031/*
32 * High Level Configuration Options
33 */
34#define CONFIG_E300 1 /* E300 Family */
Peter Tyser0f898602009-05-22 17:23:24 -050035#define CONFIG_MPC83xx 1 /* MPC83xx family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050036#define CONFIG_MPC834x 1 /* MPC834x specific */
Timur Tabi9ca880a2006-10-31 21:23:16 -060037#define CONFIG_MPC8349 1 /* MPC8349 specific */
Marian Balakowicze6f2e902005-10-11 19:09:42 +020038#define CONFIG_TQM834X 1 /* TQM834X board specific */
39
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0x80000000
41
Mike Williams16263082011-07-22 04:01:30 +000042/* IMMR Base Address Register, use Freescale default: 0xff400000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_IMMR 0xff400000
Marian Balakowicze6f2e902005-10-11 19:09:42 +020044
45/* System clock. Primary input clock when in PCI host mode */
46#define CONFIG_83XX_CLKIN 66666000 /* 66,666 MHz */
47
48/*
49 * Local Bus LCRR
50 * LCRR: DLL bypass, Clock divider is 8
51 *
52 * for CSB = 266 MHz it gives LCB clock frequency = 33 MHz
53 *
54 * External Local Bus rate is
55 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
56 */
Kim Phillipsc7190f02009-09-25 18:19:44 -050057#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
58#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
Marian Balakowicze6f2e902005-10-11 19:09:42 +020059
60/* board pre init: do not call, nothing to do */
61#undef CONFIG_BOARD_EARLY_INIT_F
62
63/* detect the number of flash banks */
64#define CONFIG_BOARD_EARLY_INIT_R
65
66/*
67 * DDR Setup
68 */
Joe Hershbergerdf939e12011-10-11 23:57:22 -050069 /* DDR is system memory*/
70#define CONFIG_SYS_DDR_BASE 0x00000000
71#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Joe Hershbergerdf939e12011-10-11 23:57:22 -050073#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
74#undef CONFIG_DDR_ECC /* only for ECC DDR module */
75#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
Marian Balakowicze6f2e902005-10-11 19:09:42 +020076
Joe Hershbergerdf939e12011-10-11 23:57:22 -050077#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
79#define CONFIG_SYS_MEMTEST_END 0x00100000
Marian Balakowicze6f2e902005-10-11 19:09:42 +020080
81/*
82 * FLASH on the Local Bus
83 */
Joe Hershbergerdf939e12011-10-11 23:57:22 -050084#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
85#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#undef CONFIG_SYS_FLASH_CHECKSUM
87#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
88#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
Joe Hershbergerdf939e12011-10-11 23:57:22 -050089#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
Wolfgang Denka3455c02009-05-15 09:19:52 +020090#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Marian Balakowicze6f2e902005-10-11 19:09:42 +020091
92/*
93 * FLASH bank number detection
94 */
95
96/*
Joe Hershbergerdf939e12011-10-11 23:57:22 -050097 * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
98 * Flash banks has to be determined at runtime and stored in a gloabl variable
99 * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
100 * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
101 * flash_info, and should be made sufficiently large to accomodate the number
102 * of banks that might actually be detected. Since most (all?) Flash related
103 * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
104 * the board, it is defined as tqm834x_num_flash_banks.
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200105 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200107
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500108#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200109
110/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500111#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
112 | BR_MS_GPCM \
113 | BR_PS_32 \
114 | BR_V)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200115
116/* FLASH timing (0x0000_0c54) */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500117#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
118 | OR_GPCM_ACS_DIV4 \
119 | OR_GPCM_SCY_5 \
120 | OR_GPCM_TRLX)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200121
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500122#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200123
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500124#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
125 | CONFIG_SYS_OR_TIMING_FLASH)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200126
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500127#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB)
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200128
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500129 /* Window base at flash base */
130#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200131
132/* disable remaining mappings */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_BR1_PRELIM 0x00000000
134#define CONFIG_SYS_OR1_PRELIM 0x00000000
135#define CONFIG_SYS_LBLAWBAR1_PRELIM 0x00000000
136#define CONFIG_SYS_LBLAWAR1_PRELIM 0x00000000
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_BR2_PRELIM 0x00000000
139#define CONFIG_SYS_OR2_PRELIM 0x00000000
140#define CONFIG_SYS_LBLAWBAR2_PRELIM 0x00000000
141#define CONFIG_SYS_LBLAWAR2_PRELIM 0x00000000
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_BR3_PRELIM 0x00000000
144#define CONFIG_SYS_OR3_PRELIM 0x00000000
145#define CONFIG_SYS_LBLAWBAR3_PRELIM 0x00000000
146#define CONFIG_SYS_LBLAWAR3_PRELIM 0x00000000
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200147
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200148/*
149 * Monitor config
150 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200151#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
Wolfgang Denk4681e672009-05-14 23:18:34 +0200154# define CONFIG_SYS_RAMBOOT
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200155#else
Wolfgang Denk4681e672009-05-14 23:18:34 +0200156# undef CONFIG_SYS_RAMBOOT
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200157#endif
158
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500160#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
161#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200162
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500163#define CONFIG_SYS_GBL_DATA_OFFSET \
164 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200166
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500167 /* Reserve 384 kB = 3 sect. for Mon */
168#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
169 /* Reserve 512 kB for malloc */
170#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200171
172/*
173 * Serial Port
174 */
175#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_NS16550
177#define CONFIG_SYS_NS16550_SERIAL
178#define CONFIG_SYS_NS16550_REG_SIZE 1
179#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500182 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
185#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200186
187/*
188 * I2C
189 */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500190#define CONFIG_HARD_I2C /* I2C with hardware support */
191#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Timur Tabibe5e6182006-11-03 19:15:00 -0600192#define CONFIG_FSL_I2C
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500193#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */
194#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
195#define CONFIG_SYS_I2C_OFFSET 0x3000
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200196
197/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500198#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
199#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
200#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
201#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
202#define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200203
204/* I2C RTC */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500205#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
206#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200207
208/* I2C SYSMON (LM75) */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500209#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
210#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_DTT_MAX_TEMP 70
212#define CONFIG_SYS_DTT_LOW_TEMP -30
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500213#define CONFIG_SYS_DTT_HYSTERESIS 3
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200214
215/*
216 * TSEC
217 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200218#define CONFIG_TSEC_ENET /* tsec ethernet support */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200219#define CONFIG_MII
220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500222#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500224#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200225
226#if defined(CONFIG_TSEC_ENET)
227
Kim Phillips255a35772007-05-16 16:52:19 -0500228#define CONFIG_TSEC1 1
229#define CONFIG_TSEC1_NAME "TSEC0"
230#define CONFIG_TSEC2 1
231#define CONFIG_TSEC2_NAME "TSEC1"
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500232#define TSEC1_PHY_ADDR 2
233#define TSEC2_PHY_ADDR 1
234#define TSEC1_PHYIDX 0
235#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500236#define TSEC1_FLAGS TSEC_GIGABIT
237#define TSEC2_FLAGS TSEC_GIGABIT
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200238
239/* Options are: TSEC[0-1] */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500240#define CONFIG_ETHPRIME "TSEC0"
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200241
242#endif /* CONFIG_TSEC_ENET */
243
244/*
245 * General PCI
246 * Addresses are mapped 1-1.
247 */
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200248#define CONFIG_PCI
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200249
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200250#if defined(CONFIG_PCI)
251
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500252#define CONFIG_PCI_PNP /* do pci plug-and-play */
253#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200254
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200255/* PCI1 host bridge */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500256#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
257#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
258#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
259#define CONFIG_SYS_PCI1_MMIO_BASE \
260 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
261#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
262#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
263#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
264#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
265#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200266
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200267#undef CONFIG_EEPRO100
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200268#define CONFIG_EEPRO100
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200269#undef CONFIG_TULIP
270
271#if !defined(CONFIG_PCI_PNP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE
273 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200274 #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200275#endif
276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200278
279#endif /* CONFIG_PCI */
280
281/*
282 * Environment
283 */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500284#define CONFIG_ENV_IS_IN_FLASH 1
285#define CONFIG_ENV_ADDR \
286 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
287#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
288#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
Wolfgang Denk929b79a2009-05-14 23:18:33 +0200289#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
290#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
291
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500292#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
293#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200294
Jon Loeliger26946902007-07-04 22:30:50 -0500295/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500296 * BOOTP options
297 */
298#define CONFIG_BOOTP_BOOTFILESIZE
299#define CONFIG_BOOTP_BOOTPATH
300#define CONFIG_BOOTP_GATEWAY
301#define CONFIG_BOOTP_HOSTNAME
302
303
304/*
Jon Loeliger26946902007-07-04 22:30:50 -0500305 * Command line configuration.
306 */
307#include <config_cmd_default.h>
308
Wolfgang Denk4681e672009-05-14 23:18:34 +0200309#define CONFIG_CMD_ASKENV
Jon Loeliger26946902007-07-04 22:30:50 -0500310#define CONFIG_CMD_DATE
Wolfgang Denk4681e672009-05-14 23:18:34 +0200311#define CONFIG_CMD_DHCP
Jon Loeliger26946902007-07-04 22:30:50 -0500312#define CONFIG_CMD_DTT
313#define CONFIG_CMD_EEPROM
314#define CONFIG_CMD_I2C
Wolfgang Denk4681e672009-05-14 23:18:34 +0200315#define CONFIG_CMD_NFS
Jon Loeliger26946902007-07-04 22:30:50 -0500316#define CONFIG_CMD_JFFS2
317#define CONFIG_CMD_MII
318#define CONFIG_CMD_PING
Wolfgang Denk4681e672009-05-14 23:18:34 +0200319#define CONFIG_CMD_REGINFO
320#define CONFIG_CMD_SNTP
Jon Loeliger26946902007-07-04 22:30:50 -0500321
322#if defined(CONFIG_PCI)
323 #define CONFIG_CMD_PCI
324#endif
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500327 #undef CONFIG_CMD_SAVEENV
Jon Loeliger26946902007-07-04 22:30:50 -0500328 #undef CONFIG_CMD_LOADS
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200329#endif
330
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200331/*
332 * Miscellaneous configurable options
333 */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500334#define CONFIG_SYS_LONGHELP /* undef to save memory */
335#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
336#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200337
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500338#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
339#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Kim Phillipsa059e902010-04-15 17:36:05 -0500340
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500341#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Wolfgang Denk2751a952006-10-28 02:29:14 +0200342
Jon Loeliger26946902007-07-04 22:30:50 -0500343#if defined(CONFIG_CMD_KGDB)
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500344 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200345#else
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500346 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200347#endif
348
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500349 /* Print Buffer Size */
350#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
351#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
352 /* Boot Argument Buffer Size */
353#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
354#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200355
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500356#undef CONFIG_WATCHDOG /* watchdog disabled */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200357
Wolfgang Denk4681e672009-05-14 23:18:34 +0200358/* pass open firmware flat tree */
359#define CONFIG_OF_LIBFDT 1
360#define CONFIG_OF_BOARD_SETUP 1
361#define CONFIG_OF_STDOUT_VIA_ALIAS 1
362
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200363/*
364 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700365 * have to be in the first 256 MB of memory, since this is
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200366 * the maximum mapped by the Linux kernel during initialization.
367 */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500368 /* Initial Memory map for Linux */
369#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200370
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_HRCW_LOW (\
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200372 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
373 HRCWL_DDR_TO_SCB_CLK_1X1 |\
374 HRCWL_CSB_TO_CLKIN_4X1 |\
375 HRCWL_VCO_1X2 |\
376 HRCWL_CORE_TO_CSB_2X1)
377
378#if defined(PCI_64BIT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_HRCW_HIGH (\
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200380 HRCWH_PCI_HOST |\
381 HRCWH_64_BIT_PCI |\
382 HRCWH_PCI1_ARBITER_ENABLE |\
383 HRCWH_PCI2_ARBITER_DISABLE |\
384 HRCWH_CORE_ENABLE |\
385 HRCWH_FROM_0X00000100 |\
386 HRCWH_BOOTSEQ_DISABLE |\
387 HRCWH_SW_WATCHDOG_DISABLE |\
388 HRCWH_ROM_LOC_LOCAL_16BIT |\
389 HRCWH_TSEC1M_IN_GMII |\
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500390 HRCWH_TSEC2M_IN_GMII)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200391#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_HRCW_HIGH (\
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200393 HRCWH_PCI_HOST |\
394 HRCWH_32_BIT_PCI |\
395 HRCWH_PCI1_ARBITER_ENABLE |\
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200396 HRCWH_PCI2_ARBITER_DISABLE |\
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200397 HRCWH_CORE_ENABLE |\
398 HRCWH_FROM_0X00000100 |\
399 HRCWH_BOOTSEQ_DISABLE |\
400 HRCWH_SW_WATCHDOG_DISABLE |\
401 HRCWH_ROM_LOC_LOCAL_16BIT |\
402 HRCWH_TSEC1M_IN_GMII |\
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500403 HRCWH_TSEC2M_IN_GMII)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200404#endif
405
Kumar Gala9260a562006-01-11 11:12:57 -0600406/* System IO Config */
Kim Phillips3c9b1ee2009-06-05 14:11:33 -0500407#define CONFIG_SYS_SICRH 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_SICRL SICRL_LDP_A
Kumar Gala9260a562006-01-11 11:12:57 -0600409
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200410/* i-cache and d-cache disabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_HID0_INIT 0x000000000
Kim Phillips1a2e2032010-04-20 19:37:54 -0500412#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
413 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_HID2 HID2_HBE
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200415
Becky Bruce31d82672008-05-08 19:02:12 -0500416#define CONFIG_HIGH_BATS 1 /* High BATs supported */
417
Kumar Gala2688e2f2006-02-10 15:40:06 -0600418/* DDR 0 - 512M */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500419#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500420 | BATL_PP_RW \
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500421 | BATL_MEMCOHERENCE)
422#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
423 | BATU_BL_256M \
424 | BATU_VS \
425 | BATU_VP)
426#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500427 | BATL_PP_RW \
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500428 | BATL_MEMCOHERENCE)
429#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
430 | BATU_BL_256M \
431 | BATU_VS \
432 | BATU_VP)
Kumar Gala2688e2f2006-02-10 15:40:06 -0600433
434/* stack in DCACHE @ 512M (no backing mem) */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500435#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500436 | BATL_PP_RW \
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500437 | BATL_MEMCOHERENCE)
438#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
439 | BATU_BL_128K \
440 | BATU_VS \
441 | BATU_VP)
Kumar Gala2688e2f2006-02-10 15:40:06 -0600442
443/* PCI */
Rafal Jaworowski6fe16a82006-08-18 10:39:11 +0200444#ifdef CONFIG_PCI
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500445#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500446 | BATL_PP_RW \
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500447 | BATL_MEMCOHERENCE)
448#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
449 | BATU_BL_256M \
450 | BATU_VS \
451 | BATU_VP)
452#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500453 | BATL_PP_RW \
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500454 | BATL_MEMCOHERENCE \
455 | BATL_GUARDEDSTORAGE)
456#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
457 | BATU_BL_256M \
458 | BATU_VS \
459 | BATU_VP)
460#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500461 | BATL_PP_RW \
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500462 | BATL_CACHEINHIBIT \
463 | BATL_GUARDEDSTORAGE)
464#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
465 | BATU_BL_16M \
466 | BATU_VS \
467 | BATU_VP)
Rafal Jaworowski6fe16a82006-08-18 10:39:11 +0200468#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#define CONFIG_SYS_IBAT3L (0)
470#define CONFIG_SYS_IBAT3U (0)
471#define CONFIG_SYS_IBAT4L (0)
472#define CONFIG_SYS_IBAT4U (0)
473#define CONFIG_SYS_IBAT5L (0)
474#define CONFIG_SYS_IBAT5U (0)
Rafal Jaworowski6fe16a82006-08-18 10:39:11 +0200475#endif
Kumar Gala2688e2f2006-02-10 15:40:06 -0600476
477/* IMMRBAR */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500478#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500479 | BATL_PP_RW \
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500480 | BATL_CACHEINHIBIT \
481 | BATL_GUARDEDSTORAGE)
482#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
483 | BATU_BL_1M \
484 | BATU_VS \
485 | BATU_VP)
Kumar Gala2688e2f2006-02-10 15:40:06 -0600486
487/* FLASH */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500488#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500489 | BATL_PP_RW \
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500490 | BATL_CACHEINHIBIT \
491 | BATL_GUARDEDSTORAGE)
492#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
493 | BATU_BL_256M \
494 | BATU_VS \
495 | BATU_VP)
Kumar Gala2688e2f2006-02-10 15:40:06 -0600496
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200497#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
498#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
499#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
500#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
501#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
502#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
503#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
504#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
505#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
506#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
507#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
508#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
509#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
510#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
511#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
512#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kumar Gala2688e2f2006-02-10 15:40:06 -0600513
Jon Loeliger26946902007-07-04 22:30:50 -0500514#if defined(CONFIG_CMD_KGDB)
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200515#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
516#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
517#endif
518
519/*
520 * Environment Configuration
521 */
522
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500523 /* default location for tftp and bootm */
524#define CONFIG_LOADADDR 400000
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200525
526#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500527#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200528
529#define CONFIG_BAUDRATE 115200
530
531#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100532 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200533 "echo"
534
535#undef CONFIG_BOOTARGS
536
537#define CONFIG_EXTRA_ENV_SETTINGS \
538 "netdev=eth0\0" \
Wolfgang Denkb931b3a2008-02-14 23:18:01 +0100539 "hostname=tqm834x\0" \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200540 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100541 "nfsroot=${serverip}:${rootpath}\0" \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200542 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100543 "addip=setenv bootargs ${bootargs} " \
544 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
545 ":${hostname}:${netdev}:off panic=1\0" \
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500546 "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
Wolfgang Denk4681e672009-05-14 23:18:34 +0200547 "flash_nfs_old=run nfsargs addip addcons;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100548 "bootm ${kernel_addr}\0" \
Wolfgang Denk4681e672009-05-14 23:18:34 +0200549 "flash_nfs=run nfsargs addip addcons;" \
550 "bootm ${kernel_addr} - ${fdt_addr}\0" \
551 "flash_self_old=run ramargs addip addcons;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100552 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
Wolfgang Denk4681e672009-05-14 23:18:34 +0200553 "flash_self=run ramargs addip addcons;" \
554 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
555 "net_nfs_old=tftp 400000 ${bootfile};" \
556 "run nfsargs addip addcons;bootm\0" \
557 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
558 "tftp ${fdt_addr_r} ${fdt_file}; " \
559 "run nfsargs addip addcons; " \
560 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200561 "rootpath=/opt/eldk/ppc_6xx\0" \
Wolfgang Denk4681e672009-05-14 23:18:34 +0200562 "bootfile=tqm834x/uImage\0" \
563 "fdtfile=tqm834x/tqm834x.dtb\0" \
564 "kernel_addr_r=400000\0" \
565 "fdt_addr_r=600000\0" \
566 "ramdisk_addr_r=800000\0" \
567 "kernel_addr=800C0000\0" \
568 "fdt_addr=800A0000\0" \
569 "ramdisk_addr=80300000\0" \
570 "u-boot=tqm834x/u-boot.bin\0" \
571 "load=tftp 200000 ${u-boot}\0" \
572 "update=protect off 80000000 +${filesize};" \
573 "era 80000000 +${filesize};" \
574 "cp.b 200000 80000000 ${filesize}\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100575 "upd=run load update\0" \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200576 ""
577
578#define CONFIG_BOOTCOMMAND "run flash_self"
579
580/*
581 * JFFS2 partitions
582 */
583/* mtdparts command line support */
Stefan Roese68d7d652009-03-19 13:30:36 +0100584#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200585#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
586#define CONFIG_FLASH_CFI_MTD
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200587#define MTDIDS_DEFAULT "nor0=TQM834x-0"
588
589/* default mtd partition table */
Joe Hershbergerdf939e12011-10-11 23:57:22 -0500590#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
591 "1m(kernel),2m(initrd)," \
592 "-(user);" \
Marian Balakowicze6f2e902005-10-11 19:09:42 +0200593
594#endif /* __CONFIG_H */