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Heiko Schocheradf22b62008-08-19 10:08:49 +02001/*
2 * (C) Copyright 2008
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_8260 1
33#define CONFIG_MPC8260 1
34#define CONFIG_MUAS3001 1
35
Wolfgang Denk2ae18242010-10-06 09:05:45 +020036#define CONFIG_SYS_TEXT_BASE 0xFF000000
37
Heiko Schocheradf22b62008-08-19 10:08:49 +020038#define CONFIG_CPM2 1 /* Has a CPM2 */
39
40/* Do boardspecific init */
41#define CONFIG_BOARD_EARLY_INIT_R 1
42
Heiko Schocher4a02a2d2008-09-08 10:20:19 +020043/* enable Watchdog */
44#define CONFIG_WATCHDOG 1
45
Heiko Schocheradf22b62008-08-19 10:08:49 +020046/*
47 * Select serial console configuration
48 *
49 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
50 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
51 * for SCC).
52 */
53#define CONFIG_CONS_ON_SMC /* Console is on SMC */
54#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
55#undef CONFIG_CONS_NONE /* It's not on external UART */
56#if defined(CONFIG_MUAS_DEV_BOARD)
57#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
58#else
59#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
60#endif
61
62/*
63 * Select ethernet configuration
64 *
65 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
66 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
67 * SCC, 1-3 for FCC)
68 *
69 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
70 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
71 * must be unset.
72 */
73#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
74#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
75#undef CONFIG_ETHER_NONE /* No external Ethernet */
76
77#define CONFIG_ETHER_INDEX 1
78#define CONFIG_ETHER_ON_FCC1
Marcel Ziswiler3ca55bc2009-09-11 07:50:33 -040079#define CONFIG_HAS_ETH0
Heiko Schocheradf22b62008-08-19 10:08:49 +020080#define FCC_ENET
81
82/*
83 * - Rx-CLK is CLK11
84 * - Tx-CLK is CLK12
85 */
Mike Frysingerd4590da2011-10-17 05:38:58 +000086# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
87# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
Heiko Schocheradf22b62008-08-19 10:08:49 +020088/*
89 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
90 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091# define CONFIG_SYS_CPMFCR_RAMTYPE (0)
Heiko Schocheradf22b62008-08-19 10:08:49 +020092/* know on local Bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093/* define CONFIG_SYS_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) */
Heiko Schocheradf22b62008-08-19 10:08:49 +020094/*
95 * - Enable Full Duplex in FSMR
96 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
Heiko Schocheradf22b62008-08-19 10:08:49 +020098
99#define CONFIG_MII /* MII PHY management */
100#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101# define CONFIG_SYS_PHY_ADDR 1
Heiko Schocheradf22b62008-08-19 10:08:49 +0200102/*
103 * GPIO pins used for bit-banged MII communications
104 */
105#define MDIO_PORT 0 /* Port A */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200106#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
107 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
108#define MDC_DECLARE MDIO_DECLARE
109
Heiko Schocheradf22b62008-08-19 10:08:49 +0200110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */
112#define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
115#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
116#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
Heiko Schocheradf22b62008-08-19 10:08:49 +0200117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
119 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
Heiko Schocheradf22b62008-08-19 10:08:49 +0200120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
122 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
Heiko Schocheradf22b62008-08-19 10:08:49 +0200123
124#define MIIDELAY udelay(1)
125
126#ifndef CONFIG_8260_CLKIN
127#define CONFIG_8260_CLKIN 66000000 /* in Hz */
128#endif
129
130#define CONFIG_BAUDRATE 115200
131
132/*
133 * Command line configuration.
134 */
135#include <config_cmd_default.h>
136
Heiko Schocher245f6ef2008-09-08 10:21:11 +0200137#define CONFIG_CMD_DTT
Heiko Schocheradf22b62008-08-19 10:08:49 +0200138#define CONFIG_CMD_ECHO
139#define CONFIG_CMD_IMMAP
140#define CONFIG_CMD_MII
141#define CONFIG_CMD_PING
142#define CONFIG_CMD_I2C
143
144/*
145 * Default environment settings
146 */
147#define CONFIG_EXTRA_ENV_SETTINGS \
148 "netdev=eth0\0" \
149 "u-boot_addr_r=100000\0" \
150 "kernel_addr_r=200000\0" \
151 "fdt_addr_r=400000\0" \
152 "rootpath=/opt/eldk/ppc_6xx\0" \
153 "u-boot=muas3001/u-boot.bin\0" \
154 "bootfile=muas3001/uImage\0" \
155 "fdt_file=muas3001/muas3001.dtb\0" \
156 "ramdisk_file=uRamdisk\0" \
157 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
158 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
159 "cp.b ${u-boot_addr_r} ff000000 ${filesize};" \
160 "prot on ff000000 ff03ffff\0" \
161 "ramargs=setenv bootargs root=/dev/ram rw\0" \
162 "nfsargs=setenv bootargs root=/dev/nfs rw " \
163 "nfsroot=${serverip}:${rootpath}\0" \
164 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
165 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
166 "addip=setenv bootargs ${bootargs} " \
167 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
168 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
169 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
170 "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \
171 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
172 "net_self=tftp ${kernel_addr_r} ${bootfile}; " \
173 "tftp ${fdt_addr_r} ${fdt_file}; " \
174 "tftp ${ramdisk_addr} ${ramdisk_file}; " \
175 "run ramargs addip; " \
176 "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \
177 "ramdisk_addr=ff210000\0" \
178 "kernel_addr=ff050000\0" \
179 "fdt_addr=ff200000\0" \
180 "flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \
181 " ${ramdisk_addr} ${fdt_addr}\0" \
182 "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \
183 " ${ramdisk_file};" \
184 "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \
185 "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \
186 " ${bootfile};" \
187 "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \
188 "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \
189 "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \
190 ""
191
192#define CONFIG_BOOTCOMMAND "run net_nfs"
193#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
194
Heiko Schocheradf22b62008-08-19 10:08:49 +0200195/*
196 * Miscellaneous configurable options
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_HUSH_PARSER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_LONGHELP /* undef to save memory */
200#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200201#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200203#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200205#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
207#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
208#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
211#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200216
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Heiko Schocheradf22b62008-08-19 10:08:49 +0200218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_SDRAM_BASE 0x00000000
220#define CONFIG_SYS_FLASH_BASE 0xFF000000
221#define CONFIG_SYS_FLASH_SIZE 32
222#define CONFIG_SYS_FLASH_CFI
Heiko Schocheradf22b62008-08-19 10:08:49 +0200223#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
225#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Heiko Schocheradf22b62008-08-19 10:08:49 +0200228
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200229#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
231#define CONFIG_SYS_RAMBOOT
Heiko Schocheradf22b62008-08-19 10:08:49 +0200232#endif
233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200235
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200236#define CONFIG_ENV_IS_IN_FLASH
Heiko Schocheradf22b62008-08-19 10:08:49 +0200237
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200238#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200239#define CONFIG_ENV_SECT_SIZE 0x10000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200241#endif /* CONFIG_ENV_IS_IN_FLASH */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200242
243/*
244 * I2C Bus
245 */
246#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
248#define CONFIG_SYS_I2C_SLAVE 0x7F
Heiko Schocheradf22b62008-08-19 10:08:49 +0200249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
Heiko Schocher245f6ef2008-09-08 10:21:11 +0200251/* I2C SYSMON (LM75, AD7414 is almost compatible) */
252#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
253#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_DTT_MAX_TEMP 70
255#define CONFIG_SYS_DTT_LOW_TEMP -30
256#define CONFIG_SYS_DTT_HYSTERESIS 3
Heiko Schocher245f6ef2008-09-08 10:21:11 +0200257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_IMMR 0xF0000000
259#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
Heiko Schocheradf22b62008-08-19 10:08:49 +0200260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200262#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200263#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocheradf22b62008-08-19 10:08:49 +0200265
266/* Hard reset configuration word */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200268
269/* No slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_HRCW_SLAVE1 0
271#define CONFIG_SYS_HRCW_SLAVE2 0
272#define CONFIG_SYS_HRCW_SLAVE3 0
273#define CONFIG_SYS_HRCW_SLAVE4 0
274#define CONFIG_SYS_HRCW_SLAVE5 0
275#define CONFIG_SYS_HRCW_SLAVE6 0
276#define CONFIG_SYS_HRCW_SLAVE7 0
Heiko Schocheradf22b62008-08-19 10:08:49 +0200277
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
279#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200282#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200284#endif
285
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_HID0_INIT 0
287#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
Heiko Schocheradf22b62008-08-19 10:08:49 +0200288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_HID2 0
Heiko Schocheradf22b62008-08-19 10:08:49 +0200290
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_SIUMCR 0x00200000
292#define CONFIG_SYS_BCR 0x004c0000
293#define CONFIG_SYS_SCCR 0x0
Heiko Schocheradf22b62008-08-19 10:08:49 +0200294
295/*-----------------------------------------------------------------------
Heiko Schocher4a02a2d2008-09-08 10:20:19 +0200296 * SYPCR - System Protection Control 4-35
297 * SYPCR can only be written once after reset!
298 *-----------------------------------------------------------------------
299 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
300 */
301#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
Heiko Schocher4a02a2d2008-09-08 10:20:19 +0200303 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
304#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
Heiko Schocher4a02a2d2008-09-08 10:20:19 +0200306 SYPCR_SWRI|SYPCR_SWP)
307#endif /* CONFIG_WATCHDOG */
308
309/*-----------------------------------------------------------------------
Heiko Schocheradf22b62008-08-19 10:08:49 +0200310 * RMR - Reset Mode Register 5-5
311 *-----------------------------------------------------------------------
312 * turn on Checkstop Reset Enable
313 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_RMR 0
Heiko Schocheradf22b62008-08-19 10:08:49 +0200315
316/*-----------------------------------------------------------------------
317 * TMCNTSC - Time Counter Status and Control 4-40
318 *-----------------------------------------------------------------------
319 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
320 * and enable Time Counter
321 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
Heiko Schocheradf22b62008-08-19 10:08:49 +0200323
324/*-----------------------------------------------------------------------
325 * PISCR - Periodic Interrupt Status and Control 4-42
326 *-----------------------------------------------------------------------
327 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
328 * Periodic timer
329 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
Heiko Schocheradf22b62008-08-19 10:08:49 +0200331
332/*-----------------------------------------------------------------------
333 * RCCR - RISC Controller Configuration 13-7
334 *-----------------------------------------------------------------------
335 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_RCCR 0
Heiko Schocheradf22b62008-08-19 10:08:49 +0200337
338/*
339 * Init Memory Controller:
340 *
341 * Bank Bus Machine PortSz Device
342 * ---- --- ------- ------ ------
343 * 0 60x GPCM 32 bit FLASH
344 * 1 60x SDRAM 64 bit SDRAM
345 * 4 60x GPCM 16 bit I/O Ctrl
346 *
347 */
348/* Bank 0 - FLASH
349 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
Heiko Schocheradf22b62008-08-19 10:08:49 +0200351 BRx_PS_32 |\
352 BRx_MS_GPCM_P |\
353 BRx_V)
354
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_OR0_PRELIM (0xff000020)
Heiko Schocheradf22b62008-08-19 10:08:49 +0200356
357/* Bank 1 - 60x bus SDRAM
358 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200360
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_MPTPR 0x2800
Heiko Schocheradf22b62008-08-19 10:08:49 +0200362
363/*-----------------------------------------------------------------------------
364 * Address for Mode Register Set (MRS) command
365 *-----------------------------------------------------------------------------
366 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_MRS_OFFS 0x00000110
368#define CONFIG_SYS_PSRT 0x13
Heiko Schocheradf22b62008-08-19 10:08:49 +0200369
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
Heiko Schocheradf22b62008-08-19 10:08:49 +0200371 BRx_PS_64 |\
372 BRx_MS_SDRAM_P |\
373 BRx_V)
374
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_LITTLE
Heiko Schocheradf22b62008-08-19 10:08:49 +0200376
377/* SDRAM initialization values
378*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_OR1_LITTLE ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schocheradf22b62008-08-19 10:08:49 +0200380 ORxS_BPD_4 |\
381 ORxS_ROWST_PBI1_A7 |\
382 ORxS_NUMR_12)
383
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384#define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3
Heiko Schochera55d0742008-09-08 10:19:36 +0200385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_OR1_BIG ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schochera55d0742008-09-08 10:19:36 +0200387 ORxS_BPD_4 |\
388 ORxS_ROWST_PBI1_A4 |\
389 ORxS_NUMR_12)
390
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_PSDMR_BIG 0x014f36a3
Heiko Schocheradf22b62008-08-19 10:08:49 +0200392
393/* IO on CS4 initialization values
394*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_IO_BASE 0xc0000000
396#define CONFIG_SYS_IO_SIZE 1
Heiko Schocheradf22b62008-08-19 10:08:49 +0200397
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\
Heiko Schocher0b7c5632008-09-10 11:15:28 +0200399 BRx_PS_16 | BRx_MS_GPCM_L | BRx_V)
Heiko Schocheradf22b62008-08-19 10:08:49 +0200400
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_OR4_PRELIM (0xfff80020)
Heiko Schocheradf22b62008-08-19 10:08:49 +0200402
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200404
405/* pass open firmware flat tree */
406#define CONFIG_OF_LIBFDT 1
407#define CONFIG_OF_BOARD_SETUP 1
408
Heiko Schocheradf22b62008-08-19 10:08:49 +0200409#define OF_TBCLK (bd->bi_busfreq / 4)
410#if defined(CONFIG_MUAS_DEV_BOARD)
411#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
412#else
413#define OF_STDOUT_PATH "/soc/cpm/serial@11a80"
414#endif
415
416#endif /* __CONFIG_H */