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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 0c5587549b89b8394e341e15833acc4be98ad916 / . / include / configs / xpedite550x.h
blob: 2acf6c80a5eee260f9e75691b04e0284d8513c16 [file] [log] [blame]
John Schmollerbfe18812010-10-22 00:20:34 -0500[diff] [blame]1/*
2 * Copyright 2010 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * xpedite550x board configuration file
25 */
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 */
32#define CONFIG_BOOKE 1 /* BOOKE */
33#define CONFIG_E500 1 /* BOOKE e500 family */
34#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
35#define CONFIG_P2020 1
36#define CONFIG_XPEDITE550X 1
37#define CONFIG_SYS_BOARD_NAME "XPedite5500"
38#define CONFIG_SYS_FORM_PMC_XMC 1
39#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
40#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
41
42#ifndef CONFIG_SYS_TEXT_BASE
43#define CONFIG_SYS_TEXT_BASE 0xfff80000
44#endif
45
46#define CONFIG_PCI 1 /* Enable PCI/PCIE */
47#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
48#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
49#define CONFIG_PCIE1 1 /* PCIE controler 1 (PEX8112 or XMC) */
50#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
51#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
52#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
53#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
54#define CONFIG_FSL_ELBC 1
55
56/*
57 * Multicore config
58 */
59#define CONFIG_MP
60#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
61#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
62
63/*
64 * DDR config
65 */
66#define CONFIG_FSL_DDR3
67#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
68#define CONFIG_DDR_SPD
69#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
Kumar Galac39f44d2011-01-31 22:18:47 -0600[diff] [blame]70#define SPD_EEPROM_ADDRESS 0x54
John Schmollerbfe18812010-10-22 00:20:34 -0500[diff] [blame]71#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
72#define CONFIG_NUM_DDR_CONTROLLERS 1
73#define CONFIG_DIMM_SLOTS_PER_CTLR 1
74#define CONFIG_CHIP_SELECTS_PER_CTRL 2
75#define CONFIG_DDR_ECC
76#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
77#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
78#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
79#define CONFIG_VERY_BIG_RAM
80
81#ifndef __ASSEMBLY__
82extern unsigned long get_board_sys_clk(unsigned long dummy);
83extern unsigned long get_board_ddr_clk(unsigned long dummy);
84#endif
85
86#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
87#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
88
89/*
90 * These can be toggled for performance analysis, otherwise use default.
91 */
92#define CONFIG_L2_CACHE /* toggle L2 cache */
93#define CONFIG_BTB /* toggle branch predition */
94#define CONFIG_ENABLE_36BIT_PHYS 1
95
Timur Tabie46fedf2011-08-04 18:03:41 -0500[diff] [blame]96#define CONFIG_SYS_CCSRBAR 0xef000000
97#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
John Schmollerbfe18812010-10-22 00:20:34 -0500[diff] [blame]98
99/*
100 * Diagnostics
101 */
102#define CONFIG_SYS_ALT_MEMTEST
103#define CONFIG_SYS_MEMTEST_START 0x10000000
104#define CONFIG_SYS_MEMTEST_END 0x20000000
105#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
106 CONFIG_SYS_POST_I2C)
107#define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
108 CONFIG_SYS_I2C_LM75_ADDR, \
109 CONFIG_SYS_I2C_LM90_ADDR, \
110 CONFIG_SYS_I2C_PCA953X_ADDR0, \
111 CONFIG_SYS_I2C_PCA953X_ADDR2, \
112 CONFIG_SYS_I2C_PCA953X_ADDR3, \
113 CONFIG_SYS_I2C_RTC_ADDR}
114
115/*
116 * Memory map
117 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
118 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
119 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
120 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
121 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
122 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
123 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
124 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
125 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
126 */
127
128#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
129
130/*
131 * NAND flash configuration
132 */
133#define CONFIG_SYS_NAND_BASE 0xef800000
134#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
135#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
136 CONFIG_SYS_NAND_BASE2}
137#define CONFIG_SYS_MAX_NAND_DEVICE 2
138#define CONFIG_MTD_NAND_VERIFY_WRITE
139#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
140#define CONFIG_NAND_FSL_ELBC
141
142/*
143 * NOR flash configuration
144 */
145#define CONFIG_SYS_FLASH_BASE 0xf8000000
146#define CONFIG_SYS_FLASH_BASE2 0xf0000000
147#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
148#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
149#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
150#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
151#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
152#define CONFIG_FLASH_CFI_DRIVER
153#define CONFIG_SYS_FLASH_CFI
154#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
155#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
156 {0xf7f40000, 0xc0000} }
157#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
158
159/*
160 * Chip select configuration
161 */
162/* NOR Flash 0 on CS0 */
163#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
164 BR_PS_16 | \
165 BR_V)
166#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
167 OR_GPCM_CSNT | \
168 OR_GPCM_XACS | \
169 OR_GPCM_ACS_DIV2 | \
170 OR_GPCM_SCY_8 | \
171 OR_GPCM_TRLX | \
172 OR_GPCM_EHTR | \
173 OR_GPCM_EAD)
174
175/* NOR Flash 1 on CS1 */
176#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
177 BR_PS_16 | \
178 BR_V)
179#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
180
181/* NAND flash on CS2 */
182#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
183 (2<<BR_DECC_SHIFT) | \
184 BR_PS_8 | \
185 BR_MS_FCM | \
186 BR_V)
187
188/* NAND flash on CS2 */
189#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
190 OR_FCM_PGS | \
191 OR_FCM_CSCT | \
192 OR_FCM_CST | \
193 OR_FCM_CHT | \
194 OR_FCM_SCY_1 | \
195 OR_FCM_TRLX | \
196 OR_FCM_EHTR)
197
198/* NAND flash on CS3 */
199#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
200 (2<<BR_DECC_SHIFT) | \
201 BR_PS_8 | \
202 BR_MS_FCM | \
203 BR_V)
204#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
205
206/*
207 * Use L1 as initial stack
208 */
209#define CONFIG_SYS_INIT_RAM_LOCK 1
210#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200[diff] [blame]211#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
John Schmollerbfe18812010-10-22 00:20:34 -0500[diff] [blame]212
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200[diff] [blame]213#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
John Schmollerbfe18812010-10-22 00:20:34 -0500[diff] [blame]214#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
215
216#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
217#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
218
219/*
220 * Serial Port
221 */
222#define CONFIG_CONS_INDEX 1
223#define CONFIG_SYS_NS16550
224#define CONFIG_SYS_NS16550_SERIAL
225#define CONFIG_SYS_NS16550_REG_SIZE 1
226#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
227#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
228#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
229#define CONFIG_SYS_BAUDRATE_TABLE \
230 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
231#define CONFIG_BAUDRATE 115200
232#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
233#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
234
235/*
236 * Use the HUSH parser
237 */
238#define CONFIG_SYS_HUSH_PARSER
John Schmollerbfe18812010-10-22 00:20:34 -0500[diff] [blame]239
240/*
241 * Pass open firmware flat tree
242 */
243#define CONFIG_OF_LIBFDT 1
244#define CONFIG_OF_BOARD_SETUP 1
245#define CONFIG_OF_STDOUT_VIA_ALIAS 1
246#define CONFIG_FDT_FIXUP_PCI_IRQ 1
247
248/*
249 * I2C
250 */
251#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
252#define CONFIG_HARD_I2C /* I2C with hardware support */
253#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
254#define CONFIG_SYS_I2C_SLAVE 0x7F
255#define CONFIG_SYS_I2C_OFFSET 0x3000
256#define CONFIG_SYS_I2C2_OFFSET 0x3100
257#define CONFIG_I2C_MULTI_BUS
258
259/* I2C DS7505 temperature sensor */
260#define CONFIG_DTT_LM75
261#define CONFIG_DTT_SENSORS { 0 }
262#define CONFIG_SYS_I2C_LM75_ADDR 0x48
263
264/* I2C ADT7461 temperature sensor */
265#define CONFIG_SYS_I2C_LM90_ADDR 0x4C
266
267/* I2C EEPROM - AT24C128B */
268#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
269#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
270#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
271#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
272
273/* I2C RTC */
274#define CONFIG_RTC_M41T11 1
275#define CONFIG_SYS_I2C_RTC_ADDR 0x68
276#define CONFIG_SYS_M41T11_BASE_YEAR 2000
277
278/* GPIO */
279#define CONFIG_PCA953X
280#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
281#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
282#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
283#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
284#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
285
286/*
287 * GPIO pin definitions, PU = pulled high, PD = pulled low
288 */
289/* PCA9557 @ 0x18*/
290#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
291#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
292#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
293#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
294#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
295#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
296
297/* PCA9557 @ 0x1e*/
298#define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
299#define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
300#define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
301#define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
302#define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
303#define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
304#define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
305
306/* PCA9557 @ 0x1f */
307#define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
308#define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
309#define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
310#define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
311#define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
312#define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
313#define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
314#define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
315
316/*
317 * General PCI
318 * Memory space is mapped 1-1, but I/O space must start from 0.
319 */
320
321/* controller 1 - PEX8112 or XMC, depending on build option */
322#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
323#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
324#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
325#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
326#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
327#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
328
329
330/*
331 * Networking options
332 */
333#define CONFIG_TSEC_ENET /* tsec ethernet support */
334#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
John Schmollerbfe18812010-10-22 00:20:34 -0500[diff] [blame]335#define CONFIG_TSEC_TBI
336#define CONFIG_MII 1 /* MII PHY management */
337#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
338#define CONFIG_ETHPRIME "eTSEC2"
339
Kumar Gala72c96a62010-12-01 22:55:54 -0600[diff] [blame]340/*
341 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
342 * 1000mbps SGMII link
343 */
344#define CONFIG_TSEC_TBICR_SETTINGS ( \
345 TBICR_PHY_RESET \
346 | TBICR_FULL_DUPLEX \
347 | TBICR_SPEED1_SET \
348 )
349
John Schmollerbfe18812010-10-22 00:20:34 -0500[diff] [blame]350#define CONFIG_TSEC1 1
351#define CONFIG_TSEC1_NAME "eTSEC1"
352#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
353#define TSEC1_PHY_ADDR 1
354#define TSEC1_PHYIDX 0
355#define CONFIG_HAS_ETH0
356
357#define CONFIG_TSEC2 1
358#define CONFIG_TSEC2_NAME "eTSEC2"
359#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
360#define TSEC2_PHY_ADDR 2
361#define TSEC2_PHYIDX 0
362#define CONFIG_HAS_ETH1
363
364#define CONFIG_TSEC3 1
365#define CONFIG_TSEC3_NAME "eTSEC3"
366#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
367#define TSEC3_PHY_ADDR 3
368#define TSEC3_PHYIDX 0
369#define CONFIG_HAS_ETH2
370
371/*
372 * USB
373 */
374#define CONFIG_USB_STORAGE
375#define CONFIG_USB_EHCI
376#define CONFIG_USB_EHCI_FSL
377#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
378#define CONFIG_DOS_PARTITION
379
380/*
381 * Command configuration.
382 */
383#include <config_cmd_default.h>
384
385#define CONFIG_CMD_ASKENV
386#define CONFIG_CMD_DATE
387#define CONFIG_CMD_DHCP
388#define CONFIG_CMD_DTT
389#define CONFIG_CMD_EEPROM
390#define CONFIG_CMD_ELF
391#define CONFIG_CMD_FLASH
392#define CONFIG_CMD_I2C
393#define CONFIG_CMD_JFFS2
394#define CONFIG_CMD_MII
395#define CONFIG_CMD_NAND
396#define CONFIG_CMD_NET
397#define CONFIG_CMD_PCA953X
398#define CONFIG_CMD_PCA953X_INFO
399#define CONFIG_CMD_PCI
400#define CONFIG_CMD_PCI_ENUM
401#define CONFIG_CMD_PING
402#define CONFIG_CMD_REGINFO
403#define CONFIG_CMD_SAVEENV
404#define CONFIG_CMD_SNTP
405#define CONFIG_CMD_USB
406
407/*
408 * Miscellaneous configurable options
409 */
410#define CONFIG_SYS_LONGHELP /* undef to save memory */
411#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
412#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
413#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
414#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
415#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
416#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
417#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
418#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
419#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
420#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
421#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
422#define CONFIG_PANIC_HANG /* do not reset board on panic */
423#define CONFIG_PREBOOT /* enable preboot variable */
424#define CONFIG_FIT 1
425#define CONFIG_FIT_VERBOSE 1
426#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
427
428/*
429 * For booting Linux, the board info and command line data
430 * have to be in the first 16 MB of memory, since this is
431 * the maximum mapped by the Linux kernel during initialization.
432 */
433#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
434#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
435
436/*
John Schmollerbfe18812010-10-22 00:20:34 -0500[diff] [blame]437 * Environment Configuration
438 */
439#define CONFIG_ENV_IS_IN_FLASH 1
440#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
441#define CONFIG_ENV_SIZE 0x8000
442#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
443
444/*
445 * Flash memory map:
446 * fff80000 - ffffffff Pri U-Boot (512 KB)
447 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
448 * fff00000 - fff3ffff Pri FDT (256KB)
449 * fef00000 - ffefffff Pri OS image (16MB)
450 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
451 *
452 * f7f80000 - f7ffffff Sec U-Boot (512 KB)
453 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
454 * f7f00000 - f7f3ffff Sec FDT (256KB)
455 * f6f00000 - f7efffff Sec OS image (16MB)
456 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
457 */
Marek Vasut5368c552012-09-23 17:41:24 +0200[diff] [blame]458#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
459#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
460#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
461#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
462#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
463#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
John Schmollerbfe18812010-10-22 00:20:34 -0500[diff] [blame]464
465#define CONFIG_PROG_UBOOT1 \
466 "$download_cmd $loadaddr $ubootfile; " \
467 "if test $? -eq 0; then " \
468 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
469 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
470 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
471 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
472 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
473 "if test $? -ne 0; then " \
474 "echo PROGRAM FAILED; " \
475 "else; " \
476 "echo PROGRAM SUCCEEDED; " \
477 "fi; " \
478 "else; " \
479 "echo DOWNLOAD FAILED; " \
480 "fi;"
481
482#define CONFIG_PROG_UBOOT2 \
483 "$download_cmd $loadaddr $ubootfile; " \
484 "if test $? -eq 0; then " \
485 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
486 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
487 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
488 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
489 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
490 "if test $? -ne 0; then " \
491 "echo PROGRAM FAILED; " \
492 "else; " \
493 "echo PROGRAM SUCCEEDED; " \
494 "fi; " \
495 "else; " \
496 "echo DOWNLOAD FAILED; " \
497 "fi;"
498
499#define CONFIG_BOOT_OS_NET \
500 "$download_cmd $osaddr $osfile; " \
501 "if test $? -eq 0; then " \
502 "if test -n $fdtaddr; then " \
503 "$download_cmd $fdtaddr $fdtfile; " \
504 "if test $? -eq 0; then " \
505 "bootm $osaddr - $fdtaddr; " \
506 "else; " \
507 "echo FDT DOWNLOAD FAILED; " \
508 "fi; " \
509 "else; " \
510 "bootm $osaddr; " \
511 "fi; " \
512 "else; " \
513 "echo OS DOWNLOAD FAILED; " \
514 "fi;"
515
516#define CONFIG_PROG_OS1 \
517 "$download_cmd $osaddr $osfile; " \
518 "if test $? -eq 0; then " \
519 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
520 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
521 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
522 "if test $? -ne 0; then " \
523 "echo OS PROGRAM FAILED; " \
524 "else; " \
525 "echo OS PROGRAM SUCCEEDED; " \
526 "fi; " \
527 "else; " \
528 "echo OS DOWNLOAD FAILED; " \
529 "fi;"
530
531#define CONFIG_PROG_OS2 \
532 "$download_cmd $osaddr $osfile; " \
533 "if test $? -eq 0; then " \
534 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
535 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
536 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
537 "if test $? -ne 0; then " \
538 "echo OS PROGRAM FAILED; " \
539 "else; " \
540 "echo OS PROGRAM SUCCEEDED; " \
541 "fi; " \
542 "else; " \
543 "echo OS DOWNLOAD FAILED; " \
544 "fi;"
545
546#define CONFIG_PROG_FDT1 \
547 "$download_cmd $fdtaddr $fdtfile; " \
548 "if test $? -eq 0; then " \
549 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
550 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
551 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
552 "if test $? -ne 0; then " \
553 "echo FDT PROGRAM FAILED; " \
554 "else; " \
555 "echo FDT PROGRAM SUCCEEDED; " \
556 "fi; " \
557 "else; " \
558 "echo FDT DOWNLOAD FAILED; " \
559 "fi;"
560
561#define CONFIG_PROG_FDT2 \
562 "$download_cmd $fdtaddr $fdtfile; " \
563 "if test $? -eq 0; then " \
564 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
565 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
566 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
567 "if test $? -ne 0; then " \
568 "echo FDT PROGRAM FAILED; " \
569 "else; " \
570 "echo FDT PROGRAM SUCCEEDED; " \
571 "fi; " \
572 "else; " \
573 "echo FDT DOWNLOAD FAILED; " \
574 "fi;"
575
576#define CONFIG_EXTRA_ENV_SETTINGS \
577 "autoload=yes\0" \
578 "download_cmd=tftp\0" \
579 "console_args=console=ttyS0,115200\0" \
580 "root_args=root=/dev/nfs rw\0" \
581 "misc_args=ip=on\0" \
582 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
583 "bootfile=/home/user/file\0" \
584 "osfile=/home/user/board.uImage\0" \
585 "fdtfile=/home/user/board.dtb\0" \
586 "ubootfile=/home/user/u-boot.bin\0" \
587 "fdtaddr=c00000\0" \
588 "osaddr=0x1000000\0" \
589 "loadaddr=0x1000000\0" \
590 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
591 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
592 "prog_os1="CONFIG_PROG_OS1"\0" \
593 "prog_os2="CONFIG_PROG_OS2"\0" \
594 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
595 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
596 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
597 "bootcmd_flash1=run set_bootargs; " \
598 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
599 "bootcmd_flash2=run set_bootargs; " \
600 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
601 "bootcmd=run bootcmd_flash1\0"
602#endif /* __CONFIG_H */