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Wenyou Yang2c62c562015-11-04 14:25:13 +08001/*
2 * Atmel PIO4 device driver
3 *
4 * Copyright (C) 2015 Atmel Corporation
5 * Wenyou.Yang <wenyou.yang@atmel.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9#include <common.h>
Wenyou Yangee3311d2016-07-20 17:16:26 +080010#include <clk.h>
Wenyou Yang2c62c562015-11-04 14:25:13 +080011#include <dm.h>
Wenyou Yangee3311d2016-07-20 17:16:26 +080012#include <fdtdec.h>
Wenyou Yang2c62c562015-11-04 14:25:13 +080013#include <asm/arch/hardware.h>
Wenyou Yangee3311d2016-07-20 17:16:26 +080014#include <asm/gpio.h>
Wenyou Yang2c62c562015-11-04 14:25:13 +080015#include <mach/gpio.h>
16#include <mach/atmel_pio4.h>
17
Wenyou Yangee3311d2016-07-20 17:16:26 +080018DECLARE_GLOBAL_DATA_PTR;
19
Wenyou Yang2c62c562015-11-04 14:25:13 +080020static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
21{
22 struct atmel_pio4_port *base = NULL;
23
24 switch (port) {
25 case AT91_PIO_PORTA:
26 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
27 break;
28 case AT91_PIO_PORTB:
29 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
30 break;
31 case AT91_PIO_PORTC:
32 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
33 break;
34 case AT91_PIO_PORTD:
35 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
36 break;
37 default:
38 printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
39 port);
40 break;
41 }
42
43 return base;
44}
45
46static int atmel_pio4_config_io_func(u32 port, u32 pin,
47 u32 func, u32 use_pullup)
48{
49 struct atmel_pio4_port *port_base;
50 u32 reg, mask;
51
Wenyou Yang46ed9382016-07-20 17:16:25 +080052 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
Wenyou Yang2c62c562015-11-04 14:25:13 +080053 return -ENODEV;
54
55 port_base = atmel_pio4_port_base(port);
56 if (!port_base)
57 return -ENODEV;
58
59 mask = 1 << pin;
60 reg = func;
Wenyou Yang46ed9382016-07-20 17:16:25 +080061 reg |= use_pullup ? ATMEL_PIO_PUEN_MASK : 0;
Wenyou Yang2c62c562015-11-04 14:25:13 +080062
63 writel(mask, &port_base->mskr);
64 writel(reg, &port_base->cfgr);
65
66 return 0;
67}
68
69int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup)
70{
71 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080072 ATMEL_PIO_CFGR_FUNC_GPIO,
Wenyou Yang2c62c562015-11-04 14:25:13 +080073 use_pullup);
74}
75
76int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup)
77{
78 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080079 ATMEL_PIO_CFGR_FUNC_PERIPH_A,
Wenyou Yang2c62c562015-11-04 14:25:13 +080080 use_pullup);
81}
82
83int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup)
84{
85 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080086 ATMEL_PIO_CFGR_FUNC_PERIPH_B,
Wenyou Yang2c62c562015-11-04 14:25:13 +080087 use_pullup);
88}
89
90int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup)
91{
92 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +080093 ATMEL_PIO_CFGR_FUNC_PERIPH_C,
Wenyou Yang2c62c562015-11-04 14:25:13 +080094 use_pullup);
95}
96
97int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup)
98{
99 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800100 ATMEL_PIO_CFGR_FUNC_PERIPH_D,
Wenyou Yang2c62c562015-11-04 14:25:13 +0800101 use_pullup);
102}
103
104int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup)
105{
106 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800107 ATMEL_PIO_CFGR_FUNC_PERIPH_E,
Wenyou Yang2c62c562015-11-04 14:25:13 +0800108 use_pullup);
109}
110
111int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup)
112{
113 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800114 ATMEL_PIO_CFGR_FUNC_PERIPH_F,
Wenyou Yang2c62c562015-11-04 14:25:13 +0800115 use_pullup);
116}
117
118int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup)
119{
120 return atmel_pio4_config_io_func(port, pin,
Wenyou Yang46ed9382016-07-20 17:16:25 +0800121 ATMEL_PIO_CFGR_FUNC_PERIPH_G,
Wenyou Yang2c62c562015-11-04 14:25:13 +0800122 use_pullup);
123}
124
125int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
126{
127 struct atmel_pio4_port *port_base;
128 u32 reg, mask;
129
Wenyou Yang46ed9382016-07-20 17:16:25 +0800130 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
Wenyou Yang2c62c562015-11-04 14:25:13 +0800131 return -ENODEV;
132
133 port_base = atmel_pio4_port_base(port);
134 if (!port_base)
135 return -ENODEV;
136
137 mask = 0x01 << pin;
Wenyou Yang46ed9382016-07-20 17:16:25 +0800138 reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800139
140 writel(mask, &port_base->mskr);
141 writel(reg, &port_base->cfgr);
142
143 if (value)
144 writel(mask, &port_base->sodr);
145 else
146 writel(mask, &port_base->codr);
147
148 return 0;
149}
150
151int atmel_pio4_get_pio_input(u32 port, u32 pin)
152{
153 struct atmel_pio4_port *port_base;
154 u32 reg, mask;
155
Wenyou Yang46ed9382016-07-20 17:16:25 +0800156 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
Wenyou Yang2c62c562015-11-04 14:25:13 +0800157 return -ENODEV;
158
159 port_base = atmel_pio4_port_base(port);
160 if (!port_base)
161 return -ENODEV;
162
163 mask = 0x01 << pin;
Wenyou Yang46ed9382016-07-20 17:16:25 +0800164 reg = ATMEL_PIO_CFGR_FUNC_GPIO;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800165
166 writel(mask, &port_base->mskr);
167 writel(reg, &port_base->cfgr);
168
169 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
170}
171
172#ifdef CONFIG_DM_GPIO
Wenyou Yangee3311d2016-07-20 17:16:26 +0800173
174struct atmel_pioctrl_data {
175 u32 nbanks;
176};
177
178struct atmel_pio4_platdata {
179 struct atmel_pio4_port *reg_base;
180};
181
182static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev,
183 u32 bank)
184{
185 struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
186 struct atmel_pio4_port *port_base =
187 (struct atmel_pio4_port *)((u32)plat->reg_base +
188 ATMEL_PIO_BANK_OFFSET * bank);
189
190 return port_base;
191}
192
Wenyou Yang2c62c562015-11-04 14:25:13 +0800193static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
194{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800195 u32 bank = ATMEL_PIO_BANK(offset);
196 u32 line = ATMEL_PIO_LINE(offset);
197 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
198 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800199
200 writel(mask, &port_base->mskr);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800201
202 clrbits_le32(&port_base->cfgr,
203 ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800204
205 return 0;
206}
207
208static int atmel_pio4_direction_output(struct udevice *dev,
209 unsigned offset, int value)
210{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800211 u32 bank = ATMEL_PIO_BANK(offset);
212 u32 line = ATMEL_PIO_LINE(offset);
213 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
214 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800215
216 writel(mask, &port_base->mskr);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800217
218 clrsetbits_le32(&port_base->cfgr,
219 ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800220
221 if (value)
222 writel(mask, &port_base->sodr);
223 else
224 writel(mask, &port_base->codr);
225
226 return 0;
227}
228
229static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
230{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800231 u32 bank = ATMEL_PIO_BANK(offset);
232 u32 line = ATMEL_PIO_LINE(offset);
233 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
234 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800235
236 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
237}
238
239static int atmel_pio4_set_value(struct udevice *dev,
240 unsigned offset, int value)
241{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800242 u32 bank = ATMEL_PIO_BANK(offset);
243 u32 line = ATMEL_PIO_LINE(offset);
244 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
245 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800246
247 if (value)
248 writel(mask, &port_base->sodr);
249 else
250 writel(mask, &port_base->codr);
251
252 return 0;
253}
254
255static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
256{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800257 u32 bank = ATMEL_PIO_BANK(offset);
258 u32 line = ATMEL_PIO_LINE(offset);
259 struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank);
260 u32 mask = BIT(line);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800261
262 writel(mask, &port_base->mskr);
263
264 return (readl(&port_base->cfgr) &
Wenyou Yang46ed9382016-07-20 17:16:25 +0800265 ATMEL_PIO_DIR_MASK) ? GPIOF_OUTPUT : GPIOF_INPUT;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800266}
267
268static const struct dm_gpio_ops atmel_pio4_ops = {
269 .direction_input = atmel_pio4_direction_input,
270 .direction_output = atmel_pio4_direction_output,
271 .get_value = atmel_pio4_get_value,
272 .set_value = atmel_pio4_set_value,
273 .get_function = atmel_pio4_get_function,
274};
275
Wenyou Yangee3311d2016-07-20 17:16:26 +0800276static int atmel_pio4_bind(struct udevice *dev)
277{
Simon Glass79fc0c72017-05-17 17:18:06 -0600278 return dm_scan_fdt_dev(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800279}
280
Wenyou Yang2c62c562015-11-04 14:25:13 +0800281static int atmel_pio4_probe(struct udevice *dev)
282{
Wenyou Yangee3311d2016-07-20 17:16:26 +0800283 struct atmel_pio4_platdata *plat = dev_get_platdata(dev);
Wenyou Yang2c62c562015-11-04 14:25:13 +0800284 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800285 struct atmel_pioctrl_data *pioctrl_data;
Wenyou Yangee3311d2016-07-20 17:16:26 +0800286 struct clk clk;
287 fdt_addr_t addr_base;
288 u32 nbanks;
Wenyou Yangee3311d2016-07-20 17:16:26 +0800289 int ret;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800290
Wenyou Yangee3311d2016-07-20 17:16:26 +0800291 ret = clk_get_by_index(dev, 0, &clk);
292 if (ret)
293 return ret;
294
Wenyou Yangee3311d2016-07-20 17:16:26 +0800295 ret = clk_enable(&clk);
296 if (ret)
297 return ret;
298
299 clk_free(&clk);
300
Simon Glassa821c4a2017-05-17 17:18:05 -0600301 addr_base = devfdt_get_addr(dev);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800302 if (addr_base == FDT_ADDR_T_NONE)
303 return -EINVAL;
304
305 plat->reg_base = (struct atmel_pio4_port *)addr_base;
306
307 pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev);
308 nbanks = pioctrl_data->nbanks;
309
Simon Glasse160f7d2017-01-17 16:52:55 -0700310 uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev_of_offset(dev),
311 NULL);
Wenyou Yangee3311d2016-07-20 17:16:26 +0800312 uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
Wenyou Yang2c62c562015-11-04 14:25:13 +0800313
314 return 0;
315}
316
Wenyou Yangee3311d2016-07-20 17:16:26 +0800317/*
318 * The number of banks can be different from a SoC to another one.
319 * We can have up to 16 banks.
320 */
321static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
322 .nbanks = 4,
323};
324
325static const struct udevice_id atmel_pio4_ids[] = {
326 {
327 .compatible = "atmel,sama5d2-gpio",
328 .data = (ulong)&atmel_sama5d2_pioctrl_data,
329 },
330 {}
331};
332
Wenyou Yang2c62c562015-11-04 14:25:13 +0800333U_BOOT_DRIVER(gpio_atmel_pio4) = {
334 .name = "gpio_atmel_pio4",
335 .id = UCLASS_GPIO,
336 .ops = &atmel_pio4_ops,
337 .probe = atmel_pio4_probe,
Wenyou Yangee3311d2016-07-20 17:16:26 +0800338 .bind = atmel_pio4_bind,
339 .of_match = atmel_pio4_ids,
340 .platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata),
Wenyou Yang2c62c562015-11-04 14:25:13 +0800341};
Wenyou Yangee3311d2016-07-20 17:16:26 +0800342
Wenyou Yang2c62c562015-11-04 14:25:13 +0800343#endif