blob: 4a6a3f85155d91242c01ab042892be7fd2ea0258 [file] [log] [blame]
Stefan Roese7644f162005-09-22 09:16:57 +02001/*
2 * (C) Copyright 2005
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38
39#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
40
41#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
42
43#define CONFIG_BAUDRATE 9600
44#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
45
46#undef CONFIG_BOOTARGS
47#undef CONFIG_BOOTCOMMAND
48
49#define CONFIG_PREBOOT /* enable preboot variable */
50
51#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
52#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
53
54#define CONFIG_MII 1 /* MII PHY management */
55#define CONFIG_PHY_ADDR 0 /* PHY address */
56
57#define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \
58 CFG_CMD_PCI | \
59 CFG_CMD_IRQ | \
60 CFG_CMD_ELF | \
61 CFG_CMD_I2C | \
62 CFG_CMD_BSP | \
63 CFG_CMD_EEPROM )
64
65/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
66#include <cmd_confdefs.h>
67
68#undef CONFIG_WATCHDOG /* watchdog disabled */
69
70#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
71
72/*
73 * Miscellaneous configurable options
74 */
75#define CFG_LONGHELP /* undef to save memory */
76#define CFG_PROMPT "=> " /* Monitor Command Prompt */
77
78#undef CFG_HUSH_PARSER /* use "hush" command parser */
79#ifdef CFG_HUSH_PARSER
80#define CFG_PROMPT_HUSH_PS2 "> "
81#endif
82
83#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
84#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
85#else
86#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
87#endif
88#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
89#define CFG_MAXARGS 16 /* max number of command args */
90#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
91
92#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
93
94#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
95
96#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
97
98#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
99#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
100
101#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
102#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
103#define CFG_BASE_BAUD 691200
104#define CONFIG_UART1_CONSOLE /* define for uart1 as console */
105
106/* The following table includes the supported baudrates */
107#define CFG_BAUDRATE_TABLE \
108 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
109 57600, 115200, 230400, 460800, 921600 }
110
111#define CFG_LOAD_ADDR 0x100000 /* default load address */
112#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
113
114#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
115
116#define CONFIG_LOOPW 1 /* enable loopw command */
117
118#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
119
120#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
121
122#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
123
124/*-----------------------------------------------------------------------
125 * PCI stuff
126 *-----------------------------------------------------------------------
127 */
128#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
129#define PCI_HOST_FORCE 1 /* configure as pci host */
130#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
131
132#define CONFIG_PCI /* include pci support */
133#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
134#define CONFIG_PCI_PNP /* do pci plug-and-play */
135 /* resource configuration */
136
137#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
138
139#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
140
141#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
142
143#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
144#define CFG_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */
145#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
146#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
147#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
148#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
149#define CFG_PCI_PTM2LA 0xef600000 /* point to internal regs + PB0/1 */
150#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */
151#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
152
153/*-----------------------------------------------------------------------
154 * Start addresses for the final memory configuration
155 * (Set up by the startup code)
156 * Please note that CFG_SDRAM_BASE _must_ start at 0
157 */
158#define CFG_SDRAM_BASE 0x00000000
159#define CFG_FLASH_BASE 0xFFFC0000
160#define CFG_MONITOR_BASE CFG_FLASH_BASE
161#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
162#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
163
164/*
165 * For booting Linux, the board info and command line data
166 * have to be in the first 8 MB of memory, since this is
167 * the maximum mapped by the Linux kernel during initialization.
168 */
169#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
170/*-----------------------------------------------------------------------
171 * FLASH organization
172 */
173#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
174#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
175
176#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
177#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
178
179#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
180#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
181#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
182
183#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
184#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
185#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
186
187#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
188
189#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
190#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
191#define CFG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
192
193/*-----------------------------------------------------------------------
194 * I2C EEPROM (CAT24WC16) for environment
195 */
196#define CONFIG_HARD_I2C /* I2c with hardware support */
197#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
198#define CFG_I2C_SLAVE 0x7F
199
200#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
201#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
202/* mask of address bits that overflow into the "EEPROM chip address" */
203#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
204#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
205 /* 16 byte page write mode using*/
206 /* last 4 bits of the address */
207#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
208#define CFG_EEPROM_PAGE_WRITE_ENABLE
209
210#define CFG_EEPROM_WREN 1
211
212/*-----------------------------------------------------------------------
213 * Cache Configuration
214 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200215#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
Stefan Roese7644f162005-09-22 09:16:57 +0200216 /* have only 8kB, 16kB is save here */
217#define CFG_CACHELINE_SIZE 32 /* ... */
218#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
219#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
220#endif
221
222/*
223 * Init Memory Controller:
224 *
225 * BR0/1 and OR0/1 (FLASH)
226 */
227#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
228#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
229
230/*-----------------------------------------------------------------------
231 * External Bus Controller (EBC) Setup
232 */
233
234/* Memory Bank 0 (Flash Bank 0) initialization */
235#define CFG_EBC_PB0AP 0x92015480
236#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
237
238/* Memory Bank 2 (PB0) initialization */
239#define CFG_EBC_PB2AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
240#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
241
242/* Memory Bank 3 (PB1) initialization */
243#define CFG_EBC_PB3AP 0x03004580 /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
244#define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
245
246/*-----------------------------------------------------------------------
247 * Definitions for initial stack pointer and data area (in data cache)
248 */
249#define CFG_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
250
251#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
252#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
253#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
254#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
255#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
256
257/*-----------------------------------------------------------------------
258 * GPIO definitions
259 */
260#define CFG_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */
261#define CFG_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */
262
263/*
264 * Internal Definitions
265 *
266 * Boot Flags
267 */
268#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
269#define BOOTFLAG_WARM 0x02 /* Software reboot */
270
271#endif /* __CONFIG_H */