blob: 8dc623ea069c6899e5ea59e8096a8274c2968480 [file] [log] [blame]
wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2001
3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
37#define CONFIG_4xx 1 /* ...member of PPC405 family */
38#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
39#define CONFIG_W7OLMC 1 /* ...specifically an LMC */
40
wdenkc837dcb2004-01-20 23:12:12 +000041#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
42#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
wdenke2211742002-11-02 23:30:20 +000043
44#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
45
46#define CONFIG_BAUDRATE 9600
47#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48
49#if 1
50#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
51#else
52#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
53#endif
54
55#undef CONFIG_BOOTARGS
56
57#define CONFIG_LOADADDR F0080000
58
59#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
60#define CONFIG_OVERWRITE_ETHADDR_ONCE
61#define CONFIG_IPADDR 192.168.1.1
62#define CONFIG_NETMASK 255.255.255.0
63#define CONFIG_SERVERIP 192.168.1.2
64
65#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
66#undef CFG_LOADS_BAUD_CHANGE /* disallow baudrate change */
67
68#define CONFIG_MII 1 /* MII PHY management */
69#define CONFIG_PHY_ADDR 0 /* PHY address */
70
71#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
72
73#define CONFIG_COMMANDS \
74 (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
75 CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
76 CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO)
77
78/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
79#include <cmd_confdefs.h>
80
81#undef CONFIG_WATCHDOG /* watchdog disabled */
82#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
83
84#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
wdenkdb2f721f2003-03-06 00:58:30 +000085#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */
wdenke2211742002-11-02 23:30:20 +000086/*
87 * Miscellaneous configurable options
88 */
89#define CFG_LONGHELP /* undef to save memory */
90#define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
91#undef CFG_HUSH_PARSER /* No hush parse for U-Boot */
92#ifdef CFG_HUSH_PARSER
93#define CFG_PROMPT_HUSH_PS2 "> "
94#endif
95#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
96#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
97#else
98#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
99#endif
100#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
101#define CFG_MAXARGS 16 /* max number of command args */
102#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
103
104#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
105#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
106
107#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
108#define CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
109#define CFG_BASE_BAUD 384000
110
111
112/* The following table includes the supported baudrates */
113#define CFG_BAUDRATE_TABLE {9600}
114
115#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
116
117#define CFG_LOAD_ADDR 0x100000 /* default load address */
118#define CFG_EXTBDINFO 1 /* use extended board_info (bd_t) */
119
120#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
121
122/*-----------------------------------------------------------------------
123 * PCI stuff
124 *-----------------------------------------------------------------------
125 */
126#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
127#define PCI_HOST_FORCE 1 /* configure as pci host */
128#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
129
130
131#define CONFIG_PCI /* include pci support */
132#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
133#define CONFIG_PCI_PNP /* pci plug-and-play */
134/* resource configuration */
135#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
136#define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
137#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
138#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
139#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
140#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
141#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
142#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
143
144/*-----------------------------------------------------------------------
145 * Set up values for external bus controller
146 * used by cpu_init.c
147 *-----------------------------------------------------------------------
148 */
149 /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
150#undef CONFIG_USE_PERWE
151
152/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
153#define CFG_TEMP_STACK_OCM 1
154
155/* bank 0 is boot flash */
156/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
157#define CFG_W7O_EBC_PB0AP 0x03050440
158/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
159#define CFG_W7O_EBC_PB0CR 0xFFE38000
160
161/* bank 1 is main flash */
162/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
163#define CFG_EBC_PB1AP 0x05850240
164/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
165#define CFG_EBC_PB1CR 0xF00FC000
166
167/* bank 2 is RTC/NVRAM */
168/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
169#define CFG_EBC_PB2AP 0x03000440
170/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
171#define CFG_EBC_PB2CR 0xFC018000
172
173/* bank 3 is FPGA 0 */
174/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
175#define CFG_EBC_PB3AP 0x02000400
176/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
177#define CFG_EBC_PB3CR 0xFD01A000
178
179/* bank 4 is FPGA 1 */
180/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
181#define CFG_EBC_PB4AP 0x02000400
182/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
183#define CFG_EBC_PB4CR 0xFD11A000
184
185/* bank 5 is FPGA 2 */
186/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
187#define CFG_EBC_PB5AP 0x02000400
188/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
189#define CFG_EBC_PB5CR 0xFD21A000
190
191/* bank 6 is unused */
192/* pb6ap = 0 */
193#define CFG_EBC_PB6AP 0x00000000
194/* pb6cr = 0 */
195#define CFG_EBC_PB6CR 0x00000000
196
197/* bank 7 is LED register */
198/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
199#define CFG_W7O_EBC_PB7AP 0x03050440
200/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
201#define CFG_W7O_EBC_PB7CR 0xFE01C000
202
203/*-----------------------------------------------------------------------
204 * Start addresses for the final memory configuration
205 * (Set up by the startup code)
206 * Please note that CFG_SDRAM_BASE _must_ start at 0
207 */
208#define CFG_SDRAM_BASE 0x00000000
209#define CFG_FLASH_BASE 0xFFFC0000
210#define CFG_MONITOR_BASE CFG_FLASH_BASE
211#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
212#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
213
214/*
215 * For booting Linux, the board info and command line data
216 * have to be in the first 8 MB of memory, since this is
217 * the maximum mapped by the Linux kernel during initialization.
218 */
219#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
220/*-----------------------------------------------------------------------
221 * FLASH organization
222 */
223#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
224#define CFG_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
225
226#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
227#define CFG_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
228#define CFG_FLASH_PROTECTION 1 /* Use real Flash protection */
229
230#if 1 /* Use NVRAM for environment variables */
231/*-----------------------------------------------------------------------
232 * NVRAM organization
233 */
234#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
235#define CFG_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
236#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
237#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
238/*define CFG_ENV_ADDR \
239 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env */
240#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR
241
242#else /* Use Boot Flash for environment variables */
243/*-----------------------------------------------------------------------
244 * Flash EEPROM for environment
245 */
246#define CFG_ENV_IS_IN_FLASH 1
247#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
248#define CFG_ENV_SIZE 0x10000 /* Total Size of env. sector */
249
250#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
251#endif
252
253/*-----------------------------------------------------------------------
254 * I2C EEPROM (CAT24WC08) for environment
255 */
256#define CONFIG_HARD_I2C /* I2c with hardware support */
257#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
258#define CFG_I2C_SLAVE 0x7F
259
260#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
261#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
262/* mask of address bits that overflow into the "EEPROM chip address" */
263#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
264#define CFG_EEPROM_PAGE_WRITE_ENABLE
265#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
266 /* 16 byte page write mode using*/
267 /* last 4 bits of the address */
268#define CFG_I2C_MULTI_EEPROMS
269/*-----------------------------------------------------------------------
270 * Definitions for Serial Presence Detect EEPROM address
271 * (to get SDRAM settings)
272 */
273#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
274
275/*-----------------------------------------------------------------------
276 * Cache Configuration
277 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200278#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
wdenke2211742002-11-02 23:30:20 +0000279#define CFG_CACHELINE_SIZE 32 /* ... */
280#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
281#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
282#endif
283
284/*
285 * Init Memory Controller:
286 */
287#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
288#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
289
290/* On Chip Memory location */
291#define CFG_OCM_DATA_ADDR 0xF8000000
292#define CFG_OCM_DATA_SIZE 0x1000
293
294/*-----------------------------------------------------------------------
295 * Definitions for initial stack pointer and data area (in RAM)
296 */
297#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
298#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
299#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
300#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
301#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
302
303
304/*
305 * Internal Definitions
306 *
307 * Boot Flags
308 */
309#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
310#define BOOTFLAG_WARM 0x02 /* Software reboot */
311
312#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
313#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
314#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
315#endif
316
317/*
318 * FPGA(s) configuration
319 */
320#define CFG_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
321#define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */
322#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
323#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
324#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
325
326#endif /* __CONFIG_H */