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TsiChungLiew8ae158c2007-08-16 15:05:11 -05001/*
2 * MCF5445x Internal Memory Map
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __MCF5445X__
27#define __MCF5445X__
28
29/*********************************************************************
TsiChungLiew8ae158c2007-08-16 15:05:11 -050030* Interrupt Controller (INTC)
31*********************************************************************/
32#define INT0_LO_RSVD0 (0)
33#define INT0_LO_EPORT1 (1)
34#define INT0_LO_EPORT2 (2)
35#define INT0_LO_EPORT3 (3)
36#define INT0_LO_EPORT4 (4)
37#define INT0_LO_EPORT5 (5)
38#define INT0_LO_EPORT6 (6)
39#define INT0_LO_EPORT7 (7)
40#define INT0_LO_EDMA_00 (8)
41#define INT0_LO_EDMA_01 (9)
42#define INT0_LO_EDMA_02 (10)
43#define INT0_LO_EDMA_03 (11)
44#define INT0_LO_EDMA_04 (12)
45#define INT0_LO_EDMA_05 (13)
46#define INT0_LO_EDMA_06 (14)
47#define INT0_LO_EDMA_07 (15)
48#define INT0_LO_EDMA_08 (16)
49#define INT0_LO_EDMA_09 (17)
50#define INT0_LO_EDMA_10 (18)
51#define INT0_LO_EDMA_11 (19)
52#define INT0_LO_EDMA_12 (20)
53#define INT0_LO_EDMA_13 (21)
54#define INT0_LO_EDMA_14 (22)
55#define INT0_LO_EDMA_15 (23)
56#define INT0_LO_EDMA_ERR (24)
57#define INT0_LO_SCM (25)
58#define INT0_LO_UART0 (26)
59#define INT0_LO_UART1 (27)
60#define INT0_LO_UART2 (28)
61#define INT0_LO_RSVD1 (29)
62#define INT0_LO_I2C (30)
63#define INT0_LO_QSPI (31)
64#define INT0_HI_DTMR0 (32)
65#define INT0_HI_DTMR1 (33)
66#define INT0_HI_DTMR2 (34)
67#define INT0_HI_DTMR3 (35)
68#define INT0_HI_FEC0_TXF (36)
69#define INT0_HI_FEC0_TXB (37)
70#define INT0_HI_FEC0_UN (38)
71#define INT0_HI_FEC0_RL (39)
72#define INT0_HI_FEC0_RXF (40)
73#define INT0_HI_FEC0_RXB (41)
74#define INT0_HI_FEC0_MII (42)
75#define INT0_HI_FEC0_LC (43)
76#define INT0_HI_FEC0_HBERR (44)
77#define INT0_HI_FEC0_GRA (45)
78#define INT0_HI_FEC0_EBERR (46)
79#define INT0_HI_FEC0_BABT (47)
80#define INT0_HI_FEC0_BABR (48)
81#define INT0_HI_FEC1_TXF (49)
82#define INT0_HI_FEC1_TXB (50)
83#define INT0_HI_FEC1_UN (51)
84#define INT0_HI_FEC1_RL (52)
85#define INT0_HI_FEC1_RXF (53)
86#define INT0_HI_FEC1_RXB (54)
87#define INT0_HI_FEC1_MII (55)
88#define INT0_HI_FEC1_LC (56)
89#define INT0_HI_FEC1_HBERR (57)
90#define INT0_HI_FEC1_GRA (58)
91#define INT0_HI_FEC1_EBERR (59)
92#define INT0_HI_FEC1_BABT (60)
93#define INT0_HI_FEC1_BABR (61)
94#define INT0_HI_SCMIR (62)
95#define INT0_HI_RTC_ISR (63)
96
97#define INT1_HI_DSPI_EOQF (33)
98#define INT1_HI_DSPI_TFFF (34)
99#define INT1_HI_DSPI_TCF (35)
100#define INT1_HI_DSPI_TFUF (36)
101#define INT1_HI_DSPI_RFDF (37)
102#define INT1_HI_DSPI_RFOF (38)
103#define INT1_HI_DSPI_RFOF_TFUF (39)
104#define INT1_HI_RNG_EI (40)
105#define INT1_HI_PIT0_PIF (43)
106#define INT1_HI_PIT1_PIF (44)
107#define INT1_HI_PIT2_PIF (45)
108#define INT1_HI_PIT3_PIF (46)
109#define INT1_HI_USBOTG_USBSTS (47)
110#define INT1_HI_SSI_ISR (49)
111#define INT1_HI_CCM_UOCSR (53)
112#define INT1_HI_ATA_ISR (54)
113#define INT1_HI_PCI_SCR (55)
114#define INT1_HI_PCI_ASR (56)
115#define INT1_HI_PLL_LOCKS (57)
116
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500117/*********************************************************************
118* Watchdog Timer Modules (WTM)
119*********************************************************************/
120
121/* Bit definitions and macros for WCR */
122#define WTM_WCR_EN (0x0001)
123#define WTM_WCR_HALTED (0x0002)
124#define WTM_WCR_DOZE (0x0004)
125#define WTM_WCR_WAIT (0x0008)
126
127/*********************************************************************
128* Serial Boot Facility (SBF)
129*********************************************************************/
130
131/* Bit definitions and macros for SBFCR */
132#define SBF_SBFCR_BLDIV(x) (((x)&0x000F)) /* Boot loader clock divider */
133#define SBF_SBFCR_FR (0x0010) /* Fast read */
134
135/*********************************************************************
136* Reset Controller Module (RCM)
137*********************************************************************/
138
139/* Bit definitions and macros for RCR */
140#define RCM_RCR_FRCRSTOUT (0x40)
141#define RCM_RCR_SOFTRST (0x80)
142
143/* Bit definitions and macros for RSR */
144#define RCM_RSR_LOL (0x01)
145#define RCM_RSR_WDR_CORE (0x02)
146#define RCM_RSR_EXT (0x04)
147#define RCM_RSR_POR (0x08)
148#define RCM_RSR_SOFT (0x20)
149
150/*********************************************************************
151* Chip Configuration Module (CCM)
152*********************************************************************/
153
154/* Bit definitions and macros for CCR_360 */
155#define CCM_CCR_360_PLLMULT2(x) (((x)&0x0003)) /* 2-Bit PLL clock mode */
156#define CCM_CCR_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
157#define CCM_CCR_360_PCIMODE (0x0008) /* PCI host/agent mode */
158#define CCM_CCR_360_PLLMODE (0x0010) /* PLL Mode */
159#define CCM_CCR_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
160#define CCM_CCR_360_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL Clock Mode */
161#define CCM_CCR_360_OSCMODE (0x0008) /* Oscillator Clock Mode */
162#define CCM_CCR_360_FBCONFIG_MASK (0x00E0)
163#define CCM_CCR_360_PLLMULT2_MASK (0x0003)
164#define CCM_CCR_360_PLLMULT3_MASK (0x0007)
165#define CCM_CCR_360_FBCONFIG_NM_NP_32 (0x0000)
166#define CCM_CCR_360_FBCONFIG_NM_NP_8 (0x0020)
167#define CCM_CCR_360_FBCONFIG_NM_NP_16 (0x0040)
168#define CCM_CCR_360_FBCONFIG_M_P_16 (0x0060)
169#define CCM_CCR_360_FBCONFIG_M_NP_32 (0x0080)
170#define CCM_CCR_360_FBCONFIG_M_NP_8 (0x00A0)
171#define CCM_CCR_360_FBCONFIG_M_NP_16 (0x00C0)
172#define CCM_CCR_360_FBCONFIG_M_P_8 (0x00E0)
173#define CCM_CCR_360_PLLMULT2_12X (0x0000)
174#define CCM_CCR_360_PLLMULT2_6X (0x0001)
175#define CCM_CCR_360_PLLMULT2_16X (0x0002)
176#define CCM_CCR_360_PLLMULT2_8X (0x0003)
177#define CCM_CCR_360_PLLMULT3_20X (0x0000)
178#define CCM_CCR_360_PLLMULT3_10X (0x0001)
179#define CCM_CCR_360_PLLMULT3_24X (0x0002)
180#define CCM_CCR_360_PLLMULT3_18X (0x0003)
181#define CCM_CCR_360_PLLMULT3_12X (0x0004)
182#define CCM_CCR_360_PLLMULT3_6X (0x0005)
183#define CCM_CCR_360_PLLMULT3_16X (0x0006)
184#define CCM_CCR_360_PLLMULT3_8X (0x0007)
185
186/* Bit definitions and macros for CCR_256 */
187#define CCM_CCR_256_PLLMULT3(x) (((x)&0x0007)) /* 3-Bit PLL clock mode */
188#define CCM_CCR_256_OSCMODE (0x0008) /* Oscillator clock mode */
189#define CCM_CCR_256_PLLMODE (0x0010) /* PLL Mode */
190#define CCM_CCR_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
191#define CCM_CCR_256_FBCONFIG_MASK (0x00E0)
192#define CCM_CCR_256_FBCONFIG_NM_32 (0x0000)
193#define CCM_CCR_256_FBCONFIG_NM_8 (0x0020)
194#define CCM_CCR_256_FBCONFIG_NM_16 (0x0040)
195#define CCM_CCR_256_FBCONFIG_M_32 (0x0080)
196#define CCM_CCR_256_FBCONFIG_M_8 (0x00A0)
197#define CCM_CCR_256_FBCONFIG_M_16 (0x00C0)
198#define CCM_CCR_256_PLLMULT3_MASK (0x0007)
199#define CCM_CCR_256_PLLMULT3_20X (0x0000)
200#define CCM_CCR_256_PLLMULT3_10X (0x0001)
201#define CCM_CCR_256_PLLMULT3_24X (0x0002)
202#define CCM_CCR_256_PLLMULT3_18X (0x0003)
203#define CCM_CCR_256_PLLMULT3_12X (0x0004)
204#define CCM_CCR_256_PLLMULT3_6X (0x0005)
205#define CCM_CCR_256_PLLMULT3_16X (0x0006)
206#define CCM_CCR_256_PLLMULT3_8X (0x0007)
207
208/* Bit definitions and macros for RCON_360 */
209#define CCM_RCON_360_PLLMULT(x) (((x)&0x0003)) /* PLL clock mode */
210#define CCM_RCON_360_PCISLEW (0x0004) /* PCI pad slew rate mode */
211#define CCM_RCON_360_PCIMODE (0x0008) /* PCI host/agent mode */
212#define CCM_RCON_360_PLLMODE (0x0010) /* PLL Mode */
213#define CCM_RCON_360_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
214
215/* Bit definitions and macros for RCON_256 */
216#define CCM_RCON_256_PLLMULT(x) (((x)&0x0007)) /* PLL clock mode */
217#define CCM_RCON_256_OSCMODE (0x0008) /* Oscillator clock mode */
218#define CCM_RCON_256_PLLMODE (0x0010) /* PLL Mode */
219#define CCM_RCON_256_FBCONFIG(x) (((x)&0x0007)<<5) /* Flexbus/PCI port size configuration */
220
221/* Bit definitions and macros for CIR */
222#define CCM_CIR_PRN(x) (((x)&0x003F)) /* Part revision number */
223#define CCM_CIR_PIN(x) (((x)&0x03FF)<<6) /* Part identification number */
224#define CCM_CIR_PIN_MASK (0xFFC0)
225#define CCM_CIR_PRN_MASK (0x003F)
226#define CCM_CIR_PIN_MCF54450 (0x4F<<6)
227#define CCM_CIR_PIN_MCF54451 (0x4D<<6)
228#define CCM_CIR_PIN_MCF54452 (0x4B<<6)
229#define CCM_CIR_PIN_MCF54453 (0x49<<6)
230#define CCM_CIR_PIN_MCF54454 (0x4A<<6)
231#define CCM_CIR_PIN_MCF54455 (0x48<<6)
232
233/* Bit definitions and macros for MISCCR */
234#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
235#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense polarity */
236#define CCM_MISCCR_USBPUE (0x0004) /* USB transceiver pull-up enable */
237#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
238#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
239#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
240#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
241#define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8) /* Bus monitor timing field */
242#define CCM_MISCCR_BME (0x0800) /* Bus monitor external enable bit */
243#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
244#define CCM_MISCCR_BMT_65536 (0)
245#define CCM_MISCCR_BMT_32768 (1)
246#define CCM_MISCCR_BMT_16384 (2)
247#define CCM_MISCCR_BMT_8192 (3)
248#define CCM_MISCCR_BMT_4096 (4)
249#define CCM_MISCCR_BMT_2048 (5)
250#define CCM_MISCCR_BMT_1024 (6)
251#define CCM_MISCCR_BMT_512 (7)
252#define CCM_MISCCR_SSIPUS_UP (1)
253#define CCM_MISCCR_SSIPUS_DOWN (0)
254#define CCM_MISCCR_TIMDMA_TIM (1)
255#define CCM_MISCCR_TIMDMA_SSI (0)
256#define CCM_MISCCR_SSISRC_CLKIN (0)
257#define CCM_MISCCR_SSISRC_PLL (1)
258#define CCM_MISCCR_USBOC_ACTHI (0)
259#define CCM_MISCCR_USBOV_ACTLO (1)
260#define CCM_MISCCR_USBSRC_CLKIN (0)
261#define CCM_MISCCR_USBSRC_PLL (1)
262
263/* Bit definitions and macros for CDR */
264#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clock divider */
265#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clock divider */
266
267/* Bit definitions and macros for UOCSR */
268#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down enable */
269#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt enable */
270#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
271#define CCM_UOCSR_PWRFLT (0x0008) /* VBUS power fault */
272#define CCM_UOCSR_SEND (0x0010) /* Session end */
273#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
274#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
275#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
276#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (read-only) */
277#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor enabled (read-only) */
278#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (read-only) */
279#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (read-only) */
280#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (read-only) */
281
282/*********************************************************************
283* General Purpose I/O Module (GPIO)
284*********************************************************************/
285
286/* Bit definitions and macros for PAR_FEC */
287#define GPIO_PAR_FEC_FEC0(x) (((x)&0x07))
288#define GPIO_PAR_FEC_FEC1(x) (((x)&0x07)<<4)
289#define GPIO_PAR_FEC_FEC1_MASK (0x8F)
290#define GPIO_PAR_FEC_FEC1_MII (0x70)
291#define GPIO_PAR_FEC_FEC1_RMII_GPIO (0x30)
292#define GPIO_PAR_FEC_FEC1_RMII_ATA (0x20)
293#define GPIO_PAR_FEC_FEC1_ATA (0x10)
294#define GPIO_PAR_FEC_FEC1_GPIO (0x00)
295#define GPIO_PAR_FEC_FEC0_MASK (0xF8)
296#define GPIO_PAR_FEC_FEC0_MII (0x07)
297#define GPIO_PAR_FEC_FEC0_RMII_GPIO (0x03)
TsiChungLiew225a24b2007-11-07 18:00:54 -0600298#define GPIO_PAR_FEC_FEC0_RMII_ULPI (0x02)
299#define GPIO_PAR_FEC_FEC0_ULPI (0x01)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500300#define GPIO_PAR_FEC_FEC0_GPIO (0x00)
301
302/* Bit definitions and macros for PAR_DMA */
303#define GPIO_PAR_DMA_DREQ0 (0x01)
304#define GPIO_PAR_DMA_DACK0(x) (((x)&0x03)<<2)
305#define GPIO_PAR_DMA_DREQ1(x) (((x)&0x03)<<4)
306#define GPIO_PAR_DMA_DACK1(x) (((x)&0x03)<<6)
307#define GPIO_PAR_DMA_DACK1_MASK (0x3F)
308#define GPIO_PAR_DMA_DACK1_DACK1 (0xC0)
309#define GPIO_PAR_DMA_DACK1_ULPI_DIR (0x40)
310#define GPIO_PAR_DMA_DACK1_GPIO (0x00)
311#define GPIO_PAR_DMA_DREQ1_MASK (0xCF)
312#define GPIO_PAR_DMA_DREQ1_DREQ1 (0x30)
313#define GPIO_PAR_DMA_DREQ1_USB_CLKIN (0x10)
314#define GPIO_PAR_DMA_DREQ1_GPIO (0x00)
315#define GPIO_PAR_DMA_DACK0_MASK (0xF3)
316#define GPIO_PAR_DMA_DACK0_DACK1 (0x0C)
317#define GPIO_PAR_DMA_DACK0_ULPI_DIR (0x04)
318#define GPIO_PAR_DMA_DACK0_GPIO (0x00)
319#define GPIO_PAR_DMA_DREQ0_DREQ0 (0x01)
320#define GPIO_PAR_DMA_DREQ0_GPIO (0x00)
321
322/* Bit definitions and macros for PAR_FBCTL */
323#define GPIO_PAR_FBCTL_TS(x) (((x)&0x03)<<3)
324#define GPIO_PAR_FBCTL_RW (0x20)
325#define GPIO_PAR_FBCTL_TA (0x40)
326#define GPIO_PAR_FBCTL_OE (0x80)
327#define GPIO_PAR_FBCTL_OE_OE (0x80)
328#define GPIO_PAR_FBCTL_OE_GPIO (0x00)
329#define GPIO_PAR_FBCTL_TA_TA (0x40)
330#define GPIO_PAR_FBCTL_TA_GPIO (0x00)
331#define GPIO_PAR_FBCTL_RW_RW (0x20)
332#define GPIO_PAR_FBCTL_RW_GPIO (0x00)
333#define GPIO_PAR_FBCTL_TS_MASK (0xE7)
334#define GPIO_PAR_FBCTL_TS_TS (0x18)
335#define GPIO_PAR_FBCTL_TS_ALE (0x10)
336#define GPIO_PAR_FBCTL_TS_TBST (0x08)
337#define GPIO_PAR_FBCTL_TS_GPIO (0x80)
338
339/* Bit definitions and macros for PAR_DSPI */
340#define GPIO_PAR_DSPI_SCK (0x01)
341#define GPIO_PAR_DSPI_SOUT (0x02)
342#define GPIO_PAR_DSPI_SIN (0x04)
343#define GPIO_PAR_DSPI_PCS0 (0x08)
344#define GPIO_PAR_DSPI_PCS1 (0x10)
345#define GPIO_PAR_DSPI_PCS2 (0x20)
346#define GPIO_PAR_DSPI_PCS5 (0x40)
347#define GPIO_PAR_DSPI_PCS5_PCS5 (0x40)
348#define GPIO_PAR_DSPI_PCS5_GPIO (0x00)
349#define GPIO_PAR_DSPI_PCS2_PCS2 (0x20)
350#define GPIO_PAR_DSPI_PCS2_GPIO (0x00)
351#define GPIO_PAR_DSPI_PCS1_PCS1 (0x10)
352#define GPIO_PAR_DSPI_PCS1_GPIO (0x00)
353#define GPIO_PAR_DSPI_PCS0_PCS0 (0x08)
354#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
355#define GPIO_PAR_DSPI_SIN_SIN (0x04)
356#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
357#define GPIO_PAR_DSPI_SOUT_SOUT (0x02)
358#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
359#define GPIO_PAR_DSPI_SCK_SCK (0x01)
360#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
361
362/* Bit definitions and macros for PAR_BE */
363#define GPIO_PAR_BE_BS0 (0x01)
364#define GPIO_PAR_BE_BS1 (0x04)
365#define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
366#define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
367#define GPIO_PAR_BE_BE3_MASK (0x3F)
368#define GPIO_PAR_BE_BE3_BE3 (0xC0)
369#define GPIO_PAR_BE_BE3_TSIZ1 (0x80)
370#define GPIO_PAR_BE_BE3_GPIO (0x00)
371#define GPIO_PAR_BE_BE2_MASK (0xCF)
372#define GPIO_PAR_BE_BE2_BE2 (0x30)
373#define GPIO_PAR_BE_BE2_TSIZ0 (0x20)
374#define GPIO_PAR_BE_BE2_GPIO (0x00)
375#define GPIO_PAR_BE_BE1_BE1 (0x04)
376#define GPIO_PAR_BE_BE1_GPIO (0x00)
377#define GPIO_PAR_BE_BE0_BE0 (0x01)
378#define GPIO_PAR_BE_BE0_GPIO (0x00)
379
380/* Bit definitions and macros for PAR_CS */
381#define GPIO_PAR_CS_CS1 (0x02)
382#define GPIO_PAR_CS_CS2 (0x04)
383#define GPIO_PAR_CS_CS3 (0x08)
384#define GPIO_PAR_CS_CS3_CS3 (0x08)
385#define GPIO_PAR_CS_CS3_GPIO (0x00)
386#define GPIO_PAR_CS_CS2_CS2 (0x04)
387#define GPIO_PAR_CS_CS2_GPIO (0x00)
388#define GPIO_PAR_CS_CS1_CS1 (0x02)
389#define GPIO_PAR_CS_CS1_GPIO (0x00)
390
391/* Bit definitions and macros for PAR_TIMER */
392#define GPIO_PAR_TIMER_T0IN(x) (((x)&0x03))
393#define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
394#define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
395#define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
396#define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
397#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
398#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
399#define GPIO_PAR_TIMER_T3IN_U2RXD (0x40)
400#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
401#define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
402#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
403#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
404#define GPIO_PAR_TIMER_T2IN_U2TXD (0x10)
405#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
406#define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
407#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
408#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
409#define GPIO_PAR_TIMER_T1IN_U2CTS (0x04)
410#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
411#define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
412#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
413#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
414#define GPIO_PAR_TIMER_T0IN_U2RTS (0x01)
415#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
416
417/* Bit definitions and macros for PAR_USB */
418#define GPIO_PAR_USB_VBUSOC(x) (((x)&0x03))
419#define GPIO_PAR_USB_VBUSEN(x) (((x)&0x03)<<2)
420#define GPIO_PAR_USB_VBUSEN_MASK (0xF3)
421#define GPIO_PAR_USB_VBUSEN_VBUSEN (0x0C)
422#define GPIO_PAR_USB_VBUSEN_USBPULLUP (0x08)
423#define GPIO_PAR_USB_VBUSEN_ULPI_NXT (0x04)
424#define GPIO_PAR_USB_VBUSEN_GPIO (0x00)
425#define GPIO_PAR_USB_VBUSOC_MASK (0xFC)
426#define GPIO_PAR_USB_VBUSOC_VBUSOC (0x03)
427#define GPIO_PAR_USB_VBUSOC_ULPI_STP (0x01)
428#define GPIO_PAR_USB_VBUSOC_GPIO (0x00)
429
430/* Bit definitions and macros for PAR_UART */
431#define GPIO_PAR_UART_U0TXD (0x01)
432#define GPIO_PAR_UART_U0RXD (0x02)
433#define GPIO_PAR_UART_U0RTS (0x04)
434#define GPIO_PAR_UART_U0CTS (0x08)
435#define GPIO_PAR_UART_U1TXD (0x10)
436#define GPIO_PAR_UART_U1RXD (0x20)
437#define GPIO_PAR_UART_U1RTS (0x40)
438#define GPIO_PAR_UART_U1CTS (0x80)
439#define GPIO_PAR_UART_U1CTS_U1CTS (0x80)
440#define GPIO_PAR_UART_U1CTS_GPIO (0x00)
441#define GPIO_PAR_UART_U1RTS_U1RTS (0x40)
442#define GPIO_PAR_UART_U1RTS_GPIO (0x00)
443#define GPIO_PAR_UART_U1RXD_U1RXD (0x20)
444#define GPIO_PAR_UART_U1RXD_GPIO (0x00)
445#define GPIO_PAR_UART_U1TXD_U1TXD (0x10)
446#define GPIO_PAR_UART_U1TXD_GPIO (0x00)
447#define GPIO_PAR_UART_U0CTS_U0CTS (0x08)
448#define GPIO_PAR_UART_U0CTS_GPIO (0x00)
449#define GPIO_PAR_UART_U0RTS_U0RTS (0x04)
450#define GPIO_PAR_UART_U0RTS_GPIO (0x00)
451#define GPIO_PAR_UART_U0RXD_U0RXD (0x02)
452#define GPIO_PAR_UART_U0RXD_GPIO (0x00)
453#define GPIO_PAR_UART_U0TXD_U0TXD (0x01)
454#define GPIO_PAR_UART_U0TXD_GPIO (0x00)
455
456/* Bit definitions and macros for PAR_FECI2C */
457#define GPIO_PAR_FECI2C_SDA(x) (((x)&0x0003))
458#define GPIO_PAR_FECI2C_SCL(x) (((x)&0x0003)<<2)
459#define GPIO_PAR_FECI2C_MDIO0 (0x0010)
460#define GPIO_PAR_FECI2C_MDC0 (0x0040)
461#define GPIO_PAR_FECI2C_MDIO1(x) (((x)&0x0003)<<8)
462#define GPIO_PAR_FECI2C_MDC1(x) (((x)&0x0003)<<10)
463#define GPIO_PAR_FECI2C_MDC1_MASK (0xF3FF)
464#define GPIO_PAR_FECI2C_MDC1_MDC1 (0x0C00)
465#define GPIO_PAR_FECI2C_MDC1_ATA_DIOR (0x0800)
466#define GPIO_PAR_FECI2C_MDC1_GPIO (0x0000)
467#define GPIO_PAR_FECI2C_MDIO1_MASK (0xFCFF)
468#define GPIO_PAR_FECI2C_MDIO1_MDIO1 (0x0300)
469#define GPIO_PAR_FECI2C_MDIO1_ATA_DIOW (0x0200)
470#define GPIO_PAR_FECI2C_MDIO1_GPIO (0x0000)
471#define GPIO_PAR_FECI2C_MDC0_MDC0 (0x0040)
472#define GPIO_PAR_FECI2C_MDC0_GPIO (0x0000)
473#define GPIO_PAR_FECI2C_MDIO0_MDIO0 (0x0010)
474#define GPIO_PAR_FECI2C_MDIO0_GPIO (0x0000)
475#define GPIO_PAR_FECI2C_SCL_MASK (0xFFF3)
476#define GPIO_PAR_FECI2C_SCL_SCL (0x000C)
477#define GPIO_PAR_FECI2C_SCL_U2TXD (0x0004)
478#define GPIO_PAR_FECI2C_SCL_GPIO (0x0000)
479#define GPIO_PAR_FECI2C_SDA_MASK (0xFFFC)
480#define GPIO_PAR_FECI2C_SDA_SDA (0x0003)
481#define GPIO_PAR_FECI2C_SDA_U2RXD (0x0001)
482#define GPIO_PAR_FECI2C_SDA_GPIO (0x0000)
483
484/* Bit definitions and macros for PAR_SSI */
485#define GPIO_PAR_SSI_MCLK (0x0001)
486#define GPIO_PAR_SSI_STXD(x) (((x)&0x0003)<<2)
487#define GPIO_PAR_SSI_SRXD(x) (((x)&0x0003)<<4)
488#define GPIO_PAR_SSI_FS(x) (((x)&0x0003)<<6)
489#define GPIO_PAR_SSI_BCLK(x) (((x)&0x0003)<<8)
490#define GPIO_PAR_SSI_BCLK_MASK (0xFCFF)
491#define GPIO_PAR_SSI_BCLK_BCLK (0x0300)
492#define GPIO_PAR_SSI_BCLK_U1CTS (0x0200)
493#define GPIO_PAR_SSI_BCLK_GPIO (0x0000)
494#define GPIO_PAR_SSI_FS_MASK (0xFF3F)
495#define GPIO_PAR_SSI_FS_FS (0x00C0)
496#define GPIO_PAR_SSI_FS_U1RTS (0x0080)
497#define GPIO_PAR_SSI_FS_GPIO (0x0000)
498#define GPIO_PAR_SSI_SRXD_MASK (0xFFCF)
499#define GPIO_PAR_SSI_SRXD_SRXD (0x0030)
500#define GPIO_PAR_SSI_SRXD_U1RXD (0x0020)
501#define GPIO_PAR_SSI_SRXD_GPIO (0x0000)
502#define GPIO_PAR_SSI_STXD_MASK (0xFFF3)
503#define GPIO_PAR_SSI_STXD_STXD (0x000C)
504#define GPIO_PAR_SSI_STXD_U1TXD (0x0008)
505#define GPIO_PAR_SSI_STXD_GPIO (0x0000)
506#define GPIO_PAR_SSI_MCLK_MCLK (0x0001)
507#define GPIO_PAR_SSI_MCLK_GPIO (0x0000)
508
509/* Bit definitions and macros for PAR_ATA */
510#define GPIO_PAR_ATA_IORDY (0x0001)
511#define GPIO_PAR_ATA_DMARQ (0x0002)
512#define GPIO_PAR_ATA_RESET (0x0004)
513#define GPIO_PAR_ATA_DA0 (0x0020)
514#define GPIO_PAR_ATA_DA1 (0x0040)
515#define GPIO_PAR_ATA_DA2 (0x0080)
516#define GPIO_PAR_ATA_CS0 (0x0100)
517#define GPIO_PAR_ATA_CS1 (0x0200)
518#define GPIO_PAR_ATA_BUFEN (0x0400)
519#define GPIO_PAR_ATA_BUFEN_BUFEN (0x0400)
520#define GPIO_PAR_ATA_BUFEN_GPIO (0x0000)
521#define GPIO_PAR_ATA_CS1_CS1 (0x0200)
522#define GPIO_PAR_ATA_CS1_GPIO (0x0000)
523#define GPIO_PAR_ATA_CS0_CS0 (0x0100)
524#define GPIO_PAR_ATA_CS0_GPIO (0x0000)
525#define GPIO_PAR_ATA_DA2_DA2 (0x0080)
526#define GPIO_PAR_ATA_DA2_GPIO (0x0000)
527#define GPIO_PAR_ATA_DA1_DA1 (0x0040)
528#define GPIO_PAR_ATA_DA1_GPIO (0x0000)
529#define GPIO_PAR_ATA_DA0_DA0 (0x0020)
530#define GPIO_PAR_ATA_DA0_GPIO (0x0000)
531#define GPIO_PAR_ATA_RESET_RESET (0x0004)
532#define GPIO_PAR_ATA_RESET_GPIO (0x0000)
533#define GPIO_PAR_ATA_DMARQ_DMARQ (0x0002)
534#define GPIO_PAR_ATA_DMARQ_GPIO (0x0000)
535#define GPIO_PAR_ATA_IORDY_IORDY (0x0001)
536#define GPIO_PAR_ATA_IORDY_GPIO (0x0000)
537
538/* Bit definitions and macros for PAR_IRQ */
539#define GPIO_PAR_IRQ_IRQ1 (0x02)
540#define GPIO_PAR_IRQ_IRQ4 (0x10)
541#define GPIO_PAR_IRQ_IRQ4_IRQ4 (0x10)
542#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
543#define GPIO_PAR_IRQ_IRQ1_IRQ1 (0x02)
544#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
545
546/* Bit definitions and macros for PAR_PCI */
547#define GPIO_PAR_PCI_REQ0 (0x0001)
548#define GPIO_PAR_PCI_REQ1 (0x0004)
549#define GPIO_PAR_PCI_REQ2 (0x0010)
550#define GPIO_PAR_PCI_REQ3(x) (((x)&0x0003)<<6)
551#define GPIO_PAR_PCI_GNT0 (0x0100)
552#define GPIO_PAR_PCI_GNT1 (0x0400)
553#define GPIO_PAR_PCI_GNT2 (0x1000)
554#define GPIO_PAR_PCI_GNT3(x) (((x)&0x0003)<<14)
555#define GPIO_PAR_PCI_GNT3_MASK (0x3FFF)
556#define GPIO_PAR_PCI_GNT3_GNT3 (0xC000)
557#define GPIO_PAR_PCI_GNT3_ATA_DMACK (0x8000)
558#define GPIO_PAR_PCI_GNT3_GPIO (0x0000)
559#define GPIO_PAR_PCI_GNT2_GNT2 (0x1000)
560#define GPIO_PAR_PCI_GNT2_GPIO (0x0000)
561#define GPIO_PAR_PCI_GNT1_GNT1 (0x0400)
562#define GPIO_PAR_PCI_GNT1_GPIO (0x0000)
563#define GPIO_PAR_PCI_GNT0_GNT0 (0x0100)
564#define GPIO_PAR_PCI_GNT0_GPIO (0x0000)
565#define GPIO_PAR_PCI_REQ3_MASK (0xFF3F)
566#define GPIO_PAR_PCI_REQ3_REQ3 (0x00C0)
567#define GPIO_PAR_PCI_REQ3_ATA_INTRQ (0x0080)
568#define GPIO_PAR_PCI_REQ3_GPIO (0x0000)
569#define GPIO_PAR_PCI_REQ2_REQ2 (0x0010)
570#define GPIO_PAR_PCI_REQ2_GPIO (0x0000)
571#define GPIO_PAR_PCI_REQ1_REQ1 (0x0040)
572#define GPIO_PAR_PCI_REQ1_GPIO (0x0000)
573#define GPIO_PAR_PCI_REQ0_REQ0 (0x0001)
574#define GPIO_PAR_PCI_REQ0_GPIO (0x0000)
575
576/* Bit definitions and macros for MSCR_SDRAM */
577#define GPIO_MSCR_SDRAM_SDCTL(x) (((x)&0x03))
578#define GPIO_MSCR_SDRAM_SDCLK(x) (((x)&0x03)<<2)
579#define GPIO_MSCR_SDRAM_SDDQS(x) (((x)&0x03)<<4)
580#define GPIO_MSCR_SDRAM_SDDATA(x) (((x)&0x03)<<6)
581#define GPIO_MSCR_SDRAM_SDDATA_MASK (0x3F)
582#define GPIO_MSCR_SDRAM_SDDATA_DDR1 (0xC0)
583#define GPIO_MSCR_SDRAM_SDDATA_DDR2 (0x80)
584#define GPIO_MSCR_SDRAM_SDDATA_FS_LPDDR (0x40)
585#define GPIO_MSCR_SDRAM_SDDATA_HS_LPDDR (0x00)
586#define GPIO_MSCR_SDRAM_SDDQS_MASK (0xCF)
587#define GPIO_MSCR_SDRAM_SDDQS_DDR1 (0x30)
588#define GPIO_MSCR_SDRAM_SDDQS_DDR2 (0x20)
589#define GPIO_MSCR_SDRAM_SDDQS_FS_LPDDR (0x10)
590#define GPIO_MSCR_SDRAM_SDDQS_HS_LPDDR (0x00)
591#define GPIO_MSCR_SDRAM_SDCLK_MASK (0xF3)
592#define GPIO_MSCR_SDRAM_SDCLK_DDR1 (0x0C)
593#define GPIO_MSCR_SDRAM_SDCLK_DDR2 (0x08)
594#define GPIO_MSCR_SDRAM_SDCLK_FS_LPDDR (0x04)
595#define GPIO_MSCR_SDRAM_SDCLK_HS_LPDDR (0x00)
596#define GPIO_MSCR_SDRAM_SDCTL_MASK (0xFC)
597#define GPIO_MSCR_SDRAM_SDCTL_DDR1 (0x03)
598#define GPIO_MSCR_SDRAM_SDCTL_DDR2 (0x02)
599#define GPIO_MSCR_SDRAM_SDCTL_FS_LPDDR (0x01)
600#define GPIO_MSCR_SDRAM_SDCTL_HS_LPDDR (0x00)
601
602/* Bit definitions and macros for MSCR_PCI */
603#define GPIO_MSCR_PCI_PCI (0x01)
604#define GPIO_MSCR_PCI_PCI_HI_66MHZ (0x01)
605#define GPIO_MSCR_PCI_PCI_LO_33MHZ (0x00)
606
607/* Bit definitions and macros for DSCR_I2C */
608#define GPIO_DSCR_I2C_I2C(x) (((x)&0x03))
609#define GPIO_DSCR_I2C_I2C_LOAD_50PF (0x03)
610#define GPIO_DSCR_I2C_I2C_LOAD_30PF (0x02)
611#define GPIO_DSCR_I2C_I2C_LOAD_20PF (0x01)
612#define GPIO_DSCR_I2C_I2C_LOAD_10PF (0x00)
613
614/* Bit definitions and macros for DSCR_FLEXBUS */
615#define GPIO_DSCR_FLEXBUS_FBADL(x) (((x)&0x03))
616#define GPIO_DSCR_FLEXBUS_FBADH(x) (((x)&0x03)<<2)
617#define GPIO_DSCR_FLEXBUS_FBCTL(x) (((x)&0x03)<<4)
618#define GPIO_DSCR_FLEXBUS_FBCLK(x) (((x)&0x03)<<6)
619#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_50PF (0xC0)
620#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_30PF (0x80)
621#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_20PF (0x40)
622#define GPIO_DSCR_FLEXBUS_FBCLK_LOAD_10PF (0x00)
623#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_50PF (0x30)
624#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_30PF (0x20)
625#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_20PF (0x10)
626#define GPIO_DSCR_FLEXBUS_FBCTL_LOAD_10PF (0x00)
627#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_50PF (0x0C)
628#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_30PF (0x08)
629#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_20PF (0x04)
630#define GPIO_DSCR_FLEXBUS_FBADH_LOAD_10PF (0x00)
631#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_50PF (0x03)
632#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_30PF (0x02)
633#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_20PF (0x01)
634#define GPIO_DSCR_FLEXBUS_FBADL_LOAD_10PF (0x00)
635
636/* Bit definitions and macros for DSCR_FEC */
637#define GPIO_DSCR_FEC_FEC0(x) (((x)&0x03))
638#define GPIO_DSCR_FEC_FEC1(x) (((x)&0x03)<<2)
639#define GPIO_DSCR_FEC_FEC1_LOAD_50PF (0x0C)
640#define GPIO_DSCR_FEC_FEC1_LOAD_30PF (0x08)
641#define GPIO_DSCR_FEC_FEC1_LOAD_20PF (0x04)
642#define GPIO_DSCR_FEC_FEC1_LOAD_10PF (0x00)
643#define GPIO_DSCR_FEC_FEC0_LOAD_50PF (0x03)
644#define GPIO_DSCR_FEC_FEC0_LOAD_30PF (0x02)
645#define GPIO_DSCR_FEC_FEC0_LOAD_20PF (0x01)
646#define GPIO_DSCR_FEC_FEC0_LOAD_10PF (0x00)
647
648/* Bit definitions and macros for DSCR_UART */
649#define GPIO_DSCR_UART_UART0(x) (((x)&0x03))
650#define GPIO_DSCR_UART_UART1(x) (((x)&0x03)<<2)
651#define GPIO_DSCR_UART_UART1_LOAD_50PF (0x0C)
652#define GPIO_DSCR_UART_UART1_LOAD_30PF (0x08)
653#define GPIO_DSCR_UART_UART1_LOAD_20PF (0x04)
654#define GPIO_DSCR_UART_UART1_LOAD_10PF (0x00)
655#define GPIO_DSCR_UART_UART0_LOAD_50PF (0x03)
656#define GPIO_DSCR_UART_UART0_LOAD_30PF (0x02)
657#define GPIO_DSCR_UART_UART0_LOAD_20PF (0x01)
658#define GPIO_DSCR_UART_UART0_LOAD_10PF (0x00)
659
660/* Bit definitions and macros for DSCR_DSPI */
661#define GPIO_DSCR_DSPI_DSPI(x) (((x)&0x03))
662#define GPIO_DSCR_DSPI_DSPI_LOAD_50PF (0x03)
663#define GPIO_DSCR_DSPI_DSPI_LOAD_30PF (0x02)
664#define GPIO_DSCR_DSPI_DSPI_LOAD_20PF (0x01)
665#define GPIO_DSCR_DSPI_DSPI_LOAD_10PF (0x00)
666
667/* Bit definitions and macros for DSCR_TIMER */
668#define GPIO_DSCR_TIMER_TIMER(x) (((x)&0x03))
669#define GPIO_DSCR_TIMER_TIMER_LOAD_50PF (0x03)
670#define GPIO_DSCR_TIMER_TIMER_LOAD_30PF (0x02)
671#define GPIO_DSCR_TIMER_TIMER_LOAD_20PF (0x01)
672#define GPIO_DSCR_TIMER_TIMER_LOAD_10PF (0x00)
673
674/* Bit definitions and macros for DSCR_SSI */
675#define GPIO_DSCR_SSI_SSI(x) (((x)&0x03))
676#define GPIO_DSCR_SSI_SSI_LOAD_50PF (0x03)
677#define GPIO_DSCR_SSI_SSI_LOAD_30PF (0x02)
678#define GPIO_DSCR_SSI_SSI_LOAD_20PF (0x01)
679#define GPIO_DSCR_SSI_SSI_LOAD_10PF (0x00)
680
681/* Bit definitions and macros for DSCR_DMA */
682#define GPIO_DSCR_DMA_DMA(x) (((x)&0x03))
683#define GPIO_DSCR_DMA_DMA_LOAD_50PF (0x03)
684#define GPIO_DSCR_DMA_DMA_LOAD_30PF (0x02)
685#define GPIO_DSCR_DMA_DMA_LOAD_20PF (0x01)
686#define GPIO_DSCR_DMA_DMA_LOAD_10PF (0x00)
687
688/* Bit definitions and macros for DSCR_DEBUG */
689#define GPIO_DSCR_DEBUG_DEBUG(x) (((x)&0x03))
690#define GPIO_DSCR_DEBUG_DEBUG_LOAD_50PF (0x03)
691#define GPIO_DSCR_DEBUG_DEBUG_LOAD_30PF (0x02)
692#define GPIO_DSCR_DEBUG_DEBUG_LOAD_20PF (0x01)
693#define GPIO_DSCR_DEBUG_DEBUG_LOAD_10PF (0x00)
694
695/* Bit definitions and macros for DSCR_RESET */
696#define GPIO_DSCR_RESET_RESET(x) (((x)&0x03))
697#define GPIO_DSCR_RESET_RESET_LOAD_50PF (0x03)
698#define GPIO_DSCR_RESET_RESET_LOAD_30PF (0x02)
699#define GPIO_DSCR_RESET_RESET_LOAD_20PF (0x01)
700#define GPIO_DSCR_RESET_RESET_LOAD_10PF (0x00)
701
702/* Bit definitions and macros for DSCR_IRQ */
703#define GPIO_DSCR_IRQ_IRQ(x) (((x)&0x03))
704#define GPIO_DSCR_IRQ_IRQ_LOAD_50PF (0x03)
705#define GPIO_DSCR_IRQ_IRQ_LOAD_30PF (0x02)
706#define GPIO_DSCR_IRQ_IRQ_LOAD_20PF (0x01)
707#define GPIO_DSCR_IRQ_IRQ_LOAD_10PF (0x00)
708
709/* Bit definitions and macros for DSCR_USB */
710#define GPIO_DSCR_USB_USB(x) (((x)&0x03))
711#define GPIO_DSCR_USB_USB_LOAD_50PF (0x03)
712#define GPIO_DSCR_USB_USB_LOAD_30PF (0x02)
713#define GPIO_DSCR_USB_USB_LOAD_20PF (0x01)
714#define GPIO_DSCR_USB_USB_LOAD_10PF (0x00)
715
716/* Bit definitions and macros for DSCR_ATA */
717#define GPIO_DSCR_ATA_ATA(x) (((x)&0x03))
718#define GPIO_DSCR_ATA_ATA_LOAD_50PF (0x03)
719#define GPIO_DSCR_ATA_ATA_LOAD_30PF (0x02)
720#define GPIO_DSCR_ATA_ATA_LOAD_20PF (0x01)
721#define GPIO_DSCR_ATA_ATA_LOAD_10PF (0x00)
722
723/*********************************************************************
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500724* SDRAM Controller (SDRAMC)
725*********************************************************************/
726
727/* Bit definitions and macros for SDMR */
728#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
729#define SDRAMC_SDMR_CMD (0x00010000) /* Command */
730#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
731#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
732#define SDRAMC_SDMR_BK_LMR (0x00000000)
733#define SDRAMC_SDMR_BK_LEMR (0x40000000)
734
735/* Bit definitions and macros for SDCR */
736#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
737#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
738#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
739#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
740#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
741#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
742#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
743#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
744#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
745#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
746#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
747#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
748#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
749#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
750
751/* Bit definitions and macros for SDCFG1 */
752#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
753#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
754#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
755#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
756#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
757#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
758#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
759
760/* Bit definitions and macros for SDCFG2 */
761#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
762#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
763#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
764#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
765
766/* Bit definitions and macros for SDCS group */
767#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
768#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
769#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
770#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
771#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
772#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
773#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
774#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
775#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
776#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
777#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
778#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
779#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
780#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
781#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
782#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
783#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
784
785/*********************************************************************
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500786* Phase Locked Loop (PLL)
787*********************************************************************/
788
789/* Bit definitions and macros for PCR */
790#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
791#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for internal bus clock frequency */
792#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for Flexbus clock frequency */
793#define PLL_PCR_OUTDIV4(x) (((x)&0x0000000F)<<12) /* Output divider for PCI clock frequency */
794#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
795#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
796#define PLL_PCR_PFDR_MASK (0x000F0000)
797#define PLL_PCR_OUTDIV5_MASK (0x000F0000)
798#define PLL_PCR_OUTDIV4_MASK (0x0000F000)
799#define PLL_PCR_OUTDIV3_MASK (0x00000F00)
800#define PLL_PCR_OUTDIV2_MASK (0x000000F0)
801#define PLL_PCR_OUTDIV1_MASK (0x0000000F)
802
803/* Bit definitions and macros for PSR */
804#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
805#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
806#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
807#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
808
809/*********************************************************************
810* PCI
811*********************************************************************/
812
813/* Bit definitions and macros for SCR */
814#define PCI_SCR_PE (0x80000000) /* Parity Error detected */
815#define PCI_SCR_SE (0x40000000) /* System error signalled */
816#define PCI_SCR_MA (0x20000000) /* Master aboart received */
817#define PCI_SCR_TR (0x10000000) /* Target abort received */
818#define PCI_SCR_TS (0x08000000) /* Target abort signalled */
819#define PCI_SCR_DT (0x06000000) /* PCI_DEVSEL timing */
820#define PCI_SCR_DP (0x01000000) /* Master data parity err */
821#define PCI_SCR_FC (0x00800000) /* Fast back-to-back */
822#define PCI_SCR_R (0x00400000) /* Reserved */
823#define PCI_SCR_66M (0x00200000) /* 66Mhz */
824#define PCI_SCR_C (0x00100000) /* Capabilities list */
825#define PCI_SCR_F (0x00000200) /* Fast back-to-back enable */
826#define PCI_SCR_S (0x00000100) /* SERR enable */
827#define PCI_SCR_ST (0x00000080) /* Addr and Data stepping */
828#define PCI_SCR_PER (0x00000040) /* Parity error response */
829#define PCI_SCR_V (0x00000020) /* VGA palette snoop enable */
830#define PCI_SCR_MW (0x00000010) /* Memory write and invalidate enable */
831#define PCI_SCR_SP (0x00000008) /* Special cycle monitor or ignore */
832#define PCI_SCR_B (0x00000004) /* Bus master enable */
833#define PCI_SCR_M (0x00000002) /* Memory access control */
834#define PCI_SCR_IO (0x00000001) /* I/O access control */
835
836#define PCI_CR1_BIST(x) ((x & 0xFF) << 24) /* Built in self test */
837#define PCI_CR1_HDR(x) ((x & 0xFF) << 16) /* Header type */
838#define PCI_CR1_LTMR(x) ((x & 0xF8) << 8) /* Latency timer */
839#define PCI_CR1_CLS(x) (x & 0x0F) /* Cache line size */
840
841#define PCI_BAR_BAR0(x) (x & 0xFFFC0000)
842#define PCI_BAR_BAR1(x) (x & 0xFFF00000)
843#define PCI_BAR_BAR2(x) (x & 0xFFC00000)
844#define PCI_BAR_BAR3(x) (x & 0xFF000000)
845#define PCI_BAR_BAR4(x) (x & 0xF8000000)
846#define PCI_BAR_BAR5(x) (x & 0xE0000000)
847#define PCI_BAR_PREF (0x00000004) /* Prefetchable access */
848#define PCI_BAR_RANGE (0x00000002) /* Fixed to 00 */
849#define PCI_BAR_IO_M (0x00000001) /* IO / memory space */
850
851#define PCI_CR2_MAXLAT(x) ((x & 0xFF) << 24) /* Maximum latency */
852#define PCI_CR2_MINGNT(x) ((x & 0xFF) << 16) /* Minimum grant */
853#define PCI_CR2_INTPIN(x) ((x & 0xFF) << 8) /* Interrupt Pin */
854#define PCI_CR2_INTLIN(x) (x & 0xFF) /* Interrupt Line */
855
856#define PCI_GSCR_DRD (0x80000000) /* Delayed read discarded */
857#define PCI_GSCR_PE (0x20000000) /* PCI_PERR detected */
858#define PCI_GSCR_SE (0x10000000) /* SERR detected */
859#define PCI_GSCR_ER (0x08000000) /* Error response detected */
860#define PCI_GSCR_DRDE (0x00008000) /* Delayed read discarded enable */
861#define PCI_GSCR_PEE (0x00002000) /* PERR detected interrupt enable */
862#define PCI_GSCR_SEE (0x00001000) /* SERR detected interrupt enable */
863#define PCI_GSCR_PR (0x00000001) /* PCI reset */
864
865#define PCI_TCR1_LD (0x01000000) /* Latency rule disable */
866#define PCI_TCR1_PID (0x00020000) /* Prefetch invalidate and disable */
867#define PCI_TCR1_P (0x00010000) /* Prefetch reads */
868#define PCI_TCR1_WCD (0x00000100) /* Write combine disable */
869
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600870#define PCI_TCR2_B5E (0x00002000) /* */
871#define PCI_TCR2_B4E (0x00001000) /* */
872#define PCI_TCR2_B3E (0x00000800) /* */
873#define PCI_TCR2_B2E (0x00000400) /* */
874#define PCI_TCR2_B1E (0x00000200) /* */
875#define PCI_TCR2_B0E (0x00000100) /* */
876#define PCI_TCR2_CR (0x00000001) /* */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500877
878#define PCI_TBATR_BAT(x) ((x & 0xFFF) << 20)
879#define PCI_TBATR_EN (0x00000001) /* Enable */
880
881#define PCI_IWCR_W0C_IO (0x08000000) /* Windows Maps to PCI I/O */
882#define PCI_IWCR_W0C_PRC_RDMUL (0x04000000) /* PCI Memory Read multiple */
883#define PCI_IWCR_W0C_PRC_RDLN (0x02000000) /* PCI Memory Read line */
884#define PCI_IWCR_W0C_PRC_RD (0x00000000) /* PCI Memory Read */
885#define PCI_IWCR_W0C_EN (0x01000000) /* Enable - Register initialize */
886#define PCI_IWCR_W1C_IO (0x00080000) /* Windows Maps to PCI I/O */
887#define PCI_IWCR_W1C_PRC_RDMUL (0x00040000) /* PCI Memory Read multiple */
888#define PCI_IWCR_W1C_PRC_RDLN (0x00020000) /* PCI Memory Read line */
889#define PCI_IWCR_W1C_PRC_RD (0x00000000) /* PCI Memory Read */
890#define PCI_IWCR_W1C_EN (0x00010000) /* Enable - Register initialize */
891#define PCI_IWCR_W2C_IO (0x00000800) /* Windows Maps to PCI I/O */
892#define PCI_IWCR_W2C_PRC_RDMUL (0x00000400) /* PCI Memory Read multiple */
893#define PCI_IWCR_W2C_PRC_RDLN (0x00000200) /* PCI Memory Read line */
894#define PCI_IWCR_W2C_PRC_RD (0x00000000) /* PCI Memory Read */
895#define PCI_IWCR_W2C_EN (0x00000100) /* Enable - Register initialize */
896
897#define PCI_ICR_REE (0x04000000) /* Retry error enable */
898#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
899#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
TsiChungLiewd2b16492008-01-14 17:06:55 -0600900#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500901
902/********************************************************************/
903
904#endif /* __MCF5445X__ */