blob: 525361179b378a31f5269804019fc31a7ad250dc [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk0ac6f8b2004-07-09 23:27:13 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
wdenk0ac6f8b2004-07-09 23:27:13 +000025/*
26 * mpc8540ads board configuration file
27 *
28 * Please refer to doc/README.mpc85xx for more info.
29 *
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
wdenk42d1f032003-10-15 23:53:47 +000032 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* High Level Configuration Options */
wdenk0ac6f8b2004-07-09 23:27:13 +000038#define CONFIG_BOOKE 1 /* BOOKE */
39#define CONFIG_E500 1 /* BOOKE e500 family */
40#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41#define CONFIG_MPC8540 1 /* MPC8540 specific */
42#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
wdenk42d1f032003-10-15 23:53:47 +000043
Jon Loeliger288693a2005-07-25 12:14:54 -050044#ifndef CONFIG_HAS_FEC
45#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
46#endif
47
wdenk0ac6f8b2004-07-09 23:27:13 +000048#define CONFIG_PCI
Kumar Gala0151cba2008-10-21 11:33:58 -050049#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020050#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000051#define CONFIG_ENV_OVERWRITE
Kumar Gala7232a272008-01-16 01:32:06 -060052#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk42d1f032003-10-15 23:53:47 +000053
wdenk0ac6f8b2004-07-09 23:27:13 +000054/*
55 * sysclk for MPC85xx
56 *
57 * Two valid values are:
58 * 33000000
59 * 66000000
60 *
61 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000062 * is likely the desired value here, so that is now the default.
63 * The board, however, can run at 66MHz. In any event, this value
64 * must match the settings of some switches. Details can be found
65 * in the README.mpc85xxads.
Matthew McClintock34c3c0e2006-06-28 10:47:03 -050066 *
67 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
68 * 33MHz to accommodate, based on a PCI pin.
69 * Note that PCI-X won't work at 33MHz.
wdenk0ac6f8b2004-07-09 23:27:13 +000070 */
71
wdenk9aea9532004-08-01 23:02:45 +000072#ifndef CONFIG_SYS_CLK_FREQ
Matthew McClintock34c3c0e2006-06-28 10:47:03 -050073#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000074#endif
75
wdenk9aea9532004-08-01 23:02:45 +000076
wdenk0ac6f8b2004-07-09 23:27:13 +000077/*
78 * These can be toggled for performance analysis, otherwise use default.
79 */
80#define CONFIG_L2_CACHE /* toggle L2 cache */
81#define CONFIG_BTB /* toggle branch predition */
wdenk42d1f032003-10-15 23:53:47 +000082
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
84#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk42d1f032003-10-15 23:53:47 +000085
wdenk42d1f032003-10-15 23:53:47 +000086
87/*
88 * Base addresses -- Note these are effective addresses where the
89 * actual resources get mapped (not physical addresses)
90 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
92#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
93#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
94#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
wdenk42d1f032003-10-15 23:53:47 +000095
Kumar Gala9617c8d2008-06-06 13:12:18 -050096/* DDR Setup */
97#define CONFIG_FSL_DDR1
98#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
99#define CONFIG_DDR_SPD
100#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk9aea9532004-08-01 23:02:45 +0000101
Kumar Gala9617c8d2008-06-06 13:12:18 -0500102#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
105#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +0000106
Kumar Gala9617c8d2008-06-06 13:12:18 -0500107#define CONFIG_NUM_DDR_CONTROLLERS 1
108#define CONFIG_DIMM_SLOTS_PER_CTLR 1
109#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk9aea9532004-08-01 23:02:45 +0000110
Kumar Gala9617c8d2008-06-06 13:12:18 -0500111/* I2C addresses of SPD EEPROMs */
112#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk9aea9532004-08-01 23:02:45 +0000113
Kumar Gala9617c8d2008-06-06 13:12:18 -0500114/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
116#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
117#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
118#define CONFIG_SYS_DDR_TIMING_1 0x37344321
119#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
120#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
121#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
122#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk42d1f032003-10-15 23:53:47 +0000123
wdenk0ac6f8b2004-07-09 23:27:13 +0000124/*
125 * SDRAM on the Local Bus
126 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
128#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +0000129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
131#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +0000132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
134#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
135#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
136#undef CONFIG_SYS_FLASH_CHECKSUM
137#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
138#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
wdenk0ac6f8b2004-07-09 23:27:13 +0000141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
143#define CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000144#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#undef CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000146#endif
147
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200148#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_CFI
150#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk42d1f032003-10-15 23:53:47 +0000151
wdenk42d1f032003-10-15 23:53:47 +0000152#undef CONFIG_CLOCKS_IN_MHZ
153
wdenk0ac6f8b2004-07-09 23:27:13 +0000154
155/*
156 * Local Bus Definitions
157 */
158
159/*
160 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk0ac6f8b2004-07-09 23:27:13 +0000162 *
163 * For BR2, need:
164 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
165 * port-size = 32-bits = BR2[19:20] = 11
166 * no parity checking = BR2[21:22] = 00
167 * SDRAM for MSEL = BR2[24:26] = 011
168 * Valid = BR[31] = 1
169 *
170 * 0 4 8 12 16 20 24 28
171 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
172 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk0ac6f8b2004-07-09 23:27:13 +0000174 * FIXME: the top 17 bits of BR2.
175 */
176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk0ac6f8b2004-07-09 23:27:13 +0000178
179/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk0ac6f8b2004-07-09 23:27:13 +0000181 *
182 * For OR2, need:
183 * 64MB mask for AM, OR2[0:7] = 1111 1100
184 * XAM, OR2[17:18] = 11
185 * 9 columns OR2[19-21] = 010
186 * 13 rows OR2[23-25] = 100
187 * EAD set for extra time OR[31] = 1
188 *
189 * 0 4 8 12 16 20 24 28
190 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
191 */
192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
196#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
197#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
198#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000199
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500200#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
201 | LSDMR_RFCR5 \
202 | LSDMR_PRETOACT3 \
203 | LSDMR_ACTTORW3 \
204 | LSDMR_BL8 \
205 | LSDMR_WRC2 \
206 | LSDMR_CL3 \
207 | LSDMR_RFEN \
wdenk0ac6f8b2004-07-09 23:27:13 +0000208 )
209
210/*
211 * SDRAM Controller configuration sequence.
212 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500213#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
214#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
215#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
216#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
217#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000218
wdenk42d1f032003-10-15 23:53:47 +0000219
wdenk9aea9532004-08-01 23:02:45 +0000220/*
221 * 32KB, 8-bit wide for ADS config reg
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_BR4_PRELIM 0xf8000801
224#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
225#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk42d1f032003-10-15 23:53:47 +0000226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_INIT_RAM_LOCK 1
228#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
229#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
232#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
233#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
236#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000237
238/* Serial Port */
239#define CONFIG_CONS_INDEX 1
240#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_NS16550
242#define CONFIG_SYS_NS16550_SERIAL
243#define CONFIG_SYS_NS16550_REG_SIZE 1
244#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk42d1f032003-10-15 23:53:47 +0000245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk42d1f032003-10-15 23:53:47 +0000247 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
250#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk42d1f032003-10-15 23:53:47 +0000251
252/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_HUSH_PARSER
254#ifdef CONFIG_SYS_HUSH_PARSER
255#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk42d1f032003-10-15 23:53:47 +0000256#endif
257
Matthew McClintock0e163872006-06-28 10:43:36 -0500258/* pass open firmware flat tree */
Kumar Gala0fd5ec62007-11-28 22:54:27 -0600259#define CONFIG_OF_LIBFDT 1
260#define CONFIG_OF_BOARD_SETUP 1
261#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500262
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_64BIT_VSPRINTF 1
264#define CONFIG_SYS_64BIT_STRTOUL 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500265
Jon Loeliger20476722006-10-20 15:50:15 -0500266/*
267 * I2C
268 */
269#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
270#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000271#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
273#define CONFIG_SYS_I2C_SLAVE 0x7F
274#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
275#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk42d1f032003-10-15 23:53:47 +0000276
wdenk0ac6f8b2004-07-09 23:27:13 +0000277/* RapidIO MMU */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600278#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala10795f42008-12-02 16:08:36 -0600279#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600280#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000282
283/*
284 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300285 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk0ac6f8b2004-07-09 23:27:13 +0000286 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600287#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600288#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600289#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600291#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600292#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
294#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000295
wdenk42d1f032003-10-15 23:53:47 +0000296#if defined(CONFIG_PCI)
wdenk0ac6f8b2004-07-09 23:27:13 +0000297
wdenk42d1f032003-10-15 23:53:47 +0000298#define CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200299#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk0ac6f8b2004-07-09 23:27:13 +0000300
wdenk42d1f032003-10-15 23:53:47 +0000301#undef CONFIG_EEPRO100
wdenk0ac6f8b2004-07-09 23:27:13 +0000302#undef CONFIG_TULIP
303
304#if !defined(CONFIG_PCI_PNP)
305 #define PCI_ENET0_IOADDR 0xe0000000
306 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200307 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000308#endif
309
wdenk0ac6f8b2004-07-09 23:27:13 +0000310#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk0ac6f8b2004-07-09 23:27:13 +0000312
313#endif /* CONFIG_PCI */
314
315
316#if defined(CONFIG_TSEC_ENET)
317
318#ifndef CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200319#define CONFIG_NET_MULTI 1
wdenk0ac6f8b2004-07-09 23:27:13 +0000320#endif
321
322#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500323#define CONFIG_TSEC1 1
324#define CONFIG_TSEC1_NAME "TSEC0"
325#define CONFIG_TSEC2 1
326#define CONFIG_TSEC2_NAME "TSEC1"
wdenk0ac6f8b2004-07-09 23:27:13 +0000327#define TSEC1_PHY_ADDR 0
328#define TSEC2_PHY_ADDR 1
wdenk0ac6f8b2004-07-09 23:27:13 +0000329#define TSEC1_PHYIDX 0
330#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500331#define TSEC1_FLAGS TSEC_GIGABIT
332#define TSEC2_FLAGS TSEC_GIGABIT
wdenk9aea9532004-08-01 23:02:45 +0000333
Jon Loeliger288693a2005-07-25 12:14:54 -0500334
335#if CONFIG_HAS_FEC
wdenk9aea9532004-08-01 23:02:45 +0000336#define CONFIG_MPC85XX_FEC 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500337#define CONFIG_MPC85XX_FEC_NAME "FEC"
wdenk9aea9532004-08-01 23:02:45 +0000338#define FEC_PHY_ADDR 3
wdenk0ac6f8b2004-07-09 23:27:13 +0000339#define FEC_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500340#define FEC_FLAGS 0
Jon Loeliger288693a2005-07-25 12:14:54 -0500341#endif
wdenk9aea9532004-08-01 23:02:45 +0000342
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500343/* Options are: TSEC[0-1], FEC */
344#define CONFIG_ETHPRIME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000345
346#endif /* CONFIG_TSEC_ENET */
347
348
349/*
350 * Environment
351 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200353 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200355 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
356 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000357#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200359 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200361 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000362#endif
363
wdenk0ac6f8b2004-07-09 23:27:13 +0000364#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000366
Jon Loeliger2835e512007-06-13 13:22:08 -0500367
368/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500369 * BOOTP options
370 */
371#define CONFIG_BOOTP_BOOTFILESIZE
372#define CONFIG_BOOTP_BOOTPATH
373#define CONFIG_BOOTP_GATEWAY
374#define CONFIG_BOOTP_HOSTNAME
375
376
377/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500378 * Command line configuration.
379 */
380#include <config_cmd_default.h>
381
382#define CONFIG_CMD_PING
383#define CONFIG_CMD_I2C
Kumar Gala82ac8c92007-12-07 12:04:30 -0600384#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500385#define CONFIG_CMD_IRQ
386#define CONFIG_CMD_SETEXPR
Jon Loeliger2835e512007-06-13 13:22:08 -0500387
388#if defined(CONFIG_PCI)
389 #define CONFIG_CMD_PCI
wdenk42d1f032003-10-15 23:53:47 +0000390#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000391
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500393 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500394 #undef CONFIG_CMD_LOADS
395#endif
396
wdenk42d1f032003-10-15 23:53:47 +0000397
wdenk0ac6f8b2004-07-09 23:27:13 +0000398#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000399
400/*
401 * Miscellaneous configurable options
402 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kumar Gala22abb2d2007-11-29 10:34:28 -0600404#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
406#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk0ac6f8b2004-07-09 23:27:13 +0000407
Jon Loeliger2835e512007-06-13 13:22:08 -0500408#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000410#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000412#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000413
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
415#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
416#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
417#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk42d1f032003-10-15 23:53:47 +0000418
419/*
420 * For booting Linux, the board info and command line data
421 * have to be in the first 8 MB of memory, since this is
422 * the maximum mapped by the Linux kernel during initialization.
423 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
wdenk42d1f032003-10-15 23:53:47 +0000425
wdenk42d1f032003-10-15 23:53:47 +0000426/*
427 * Internal Definitions
428 *
429 * Boot Flags
430 */
431#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenk0ac6f8b2004-07-09 23:27:13 +0000432#define BOOTFLAG_WARM 0x02 /* Software reboot */
wdenk42d1f032003-10-15 23:53:47 +0000433
Jon Loeliger2835e512007-06-13 13:22:08 -0500434#if defined(CONFIG_CMD_KGDB)
wdenk42d1f032003-10-15 23:53:47 +0000435#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
436#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
437#endif
438
wdenk9aea9532004-08-01 23:02:45 +0000439
440/*
441 * Environment Configuration
442 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000443
444/* The mac addresses for all ethernet interface */
wdenk42d1f032003-10-15 23:53:47 +0000445#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500446#define CONFIG_HAS_ETH0
wdenk0ac6f8b2004-07-09 23:27:13 +0000447#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000448#define CONFIG_HAS_ETH1
wdenk0ac6f8b2004-07-09 23:27:13 +0000449#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000450#define CONFIG_HAS_ETH2
wdenk0ac6f8b2004-07-09 23:27:13 +0000451#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
wdenk42d1f032003-10-15 23:53:47 +0000452#endif
453
wdenk0ac6f8b2004-07-09 23:27:13 +0000454#define CONFIG_IPADDR 192.168.1.253
455
456#define CONFIG_HOSTNAME unknown
457#define CONFIG_ROOTPATH /nfsroot
458#define CONFIG_BOOTFILE your.uImage
459
460#define CONFIG_SERVERIP 192.168.1.1
461#define CONFIG_GATEWAYIP 192.168.1.1
462#define CONFIG_NETMASK 255.255.255.0
463
464#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
465
466#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
467#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
468
469#define CONFIG_BAUDRATE 115200
470
wdenk9aea9532004-08-01 23:02:45 +0000471#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk0ac6f8b2004-07-09 23:27:13 +0000472 "netdev=eth0\0" \
473 "consoledev=ttyS0\0" \
Andy Flemingd3ec0d92007-05-10 17:50:01 -0500474 "ramdiskaddr=1000000\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500475 "ramdiskfile=your.ramdisk.u-boot\0" \
476 "fdtaddr=400000\0" \
477 "fdtfile=your.fdt.dtb\0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000478
wdenk9aea9532004-08-01 23:02:45 +0000479#define CONFIG_NFSBOOTCOMMAND \
wdenk0ac6f8b2004-07-09 23:27:13 +0000480 "setenv bootargs root=/dev/nfs rw " \
481 "nfsroot=$serverip:$rootpath " \
482 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
483 "console=$consoledev,$baudrate $othbootargs;" \
484 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500485 "tftp $fdtaddr $fdtfile;" \
486 "bootm $loadaddr - $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000487
488#define CONFIG_RAMBOOTCOMMAND \
489 "setenv bootargs root=/dev/ram rw " \
490 "console=$consoledev,$baudrate $othbootargs;" \
491 "tftp $ramdiskaddr $ramdiskfile;" \
492 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500493 "tftp $fdtaddr $fdtfile;" \
Andy Flemingd3ec0d92007-05-10 17:50:01 -0500494 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000495
496#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000497
498#endif /* __CONFIG_H */