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wdenk03f5c552004-10-10 21:21:55 +00001/*
2 * Copyright 2004 Freescale Semiconductor.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * mpc8541cds board configuration file
25 *
26 * Please refer to doc/README.mpc85xxcds for more info.
27 *
28 */
wdenk03f5c552004-10-10 21:21:55 +000029#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/* High Level Configuration Options */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050036#define CONFIG_CPM2 1 /* has CPM2 */
wdenk03f5c552004-10-10 21:21:55 +000037#define CONFIG_MPC8541 1 /* MPC8541 specific */
38#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
39
40#define CONFIG_PCI
Kumar Gala0151cba2008-10-21 11:33:58 -050041#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020042#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk03f5c552004-10-10 21:21:55 +000043#define CONFIG_ENV_OVERWRITE
Jon Loeligerd9b94f22005-07-25 14:05:07 -050044
Kumar Gala2cfaa1a2008-01-16 01:45:10 -060045#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk03f5c552004-10-10 21:21:55 +000046
Jon Loeliger25eedb22008-03-19 15:02:07 -050047#define CONFIG_FSL_VIA
Jon Loeliger25eedb22008-03-19 15:02:07 -050048
wdenk03f5c552004-10-10 21:21:55 +000049/*
50 * When initializing flash, if we cannot find the manufacturer ID,
51 * assume this is the AMD flash associated with the CDS board.
52 * This allows booting from a promjet.
53 */
54#define CONFIG_ASSUME_AMD_FLASH
55
wdenk03f5c552004-10-10 21:21:55 +000056#ifndef __ASSEMBLY__
57extern unsigned long get_clock_freq(void);
58#endif
59#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
60
61/*
62 * These can be toggled for performance analysis, otherwise use default.
63 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020064#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk03f5c552004-10-10 21:21:55 +000065#define CONFIG_BTB /* toggle branch predition */
wdenk03f5c552004-10-10 21:21:55 +000066
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
68#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk03f5c552004-10-10 21:21:55 +000069
wdenk03f5c552004-10-10 21:21:55 +000070/*
71 * Base addresses -- Note these are effective addresses where the
72 * actual resources get mapped (not physical addresses)
73 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
75#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
76#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
77#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
wdenk03f5c552004-10-10 21:21:55 +000078
Jon Loeligeraa11d852008-03-17 15:48:18 -050079/* DDR Setup */
80#define CONFIG_FSL_DDR1
81#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
82#define CONFIG_DDR_SPD
83#undef CONFIG_FSL_DDR_INTERACTIVE
84
85#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
86
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
88#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk03f5c552004-10-10 21:21:55 +000089
Jon Loeligeraa11d852008-03-17 15:48:18 -050090#define CONFIG_NUM_DDR_CONTROLLERS 1
91#define CONFIG_DIMM_SLOTS_PER_CTLR 1
92#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
93
94/* I2C addresses of SPD EEPROMs */
95#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk03f5c552004-10-10 21:21:55 +000096
97/*
98 * Make sure required options are set
99 */
100#ifndef CONFIG_SPD_EEPROM
101#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
102#endif
103
Jon Loeliger7202d432005-07-25 11:13:26 -0500104#undef CONFIG_CLOCKS_IN_MHZ
105
wdenk03f5c552004-10-10 21:21:55 +0000106/*
Jon Loeliger7202d432005-07-25 11:13:26 -0500107 * Local Bus Definitions
wdenk03f5c552004-10-10 21:21:55 +0000108 */
Jon Loeliger7202d432005-07-25 11:13:26 -0500109
110/*
111 * FLASH on the Local Bus
112 * Two banks, 8M each, using the CFI driver.
113 * Boot from BR0/OR0 bank at 0xff00_0000
114 * Alternate BR1/OR1 bank at 0xff80_0000
115 *
116 * BR0, BR1:
117 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
118 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
119 * Port Size = 16 bits = BRx[19:20] = 10
120 * Use GPCM = BRx[24:26] = 000
121 * Valid = BRx[31] = 1
122 *
123 * 0 4 8 12 16 20 24 28
124 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
125 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
126 *
127 * OR0, OR1:
128 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
129 * Reserved ORx[17:18] = 11, confusion here?
130 * CSNT = ORx[20] = 1
131 * ACS = half cycle delay = ORx[21:22] = 11
132 * SCY = 6 = ORx[24:27] = 0110
133 * TRLX = use relaxed timing = ORx[29] = 1
134 * EAD = use external address latch delay = OR[31] = 1
135 *
136 * 0 4 8 12 16 20 24 28
137 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
138 */
139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
wdenk03f5c552004-10-10 21:21:55 +0000141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_BR0_PRELIM 0xff801001
143#define CONFIG_SYS_BR1_PRELIM 0xff001001
wdenk03f5c552004-10-10 21:21:55 +0000144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_OR0_PRELIM 0xff806e65
146#define CONFIG_SYS_OR1_PRELIM 0xff806e65
wdenk03f5c552004-10-10 21:21:55 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
149#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
150#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
151#undef CONFIG_SYS_FLASH_CHECKSUM
152#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
153#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk03f5c552004-10-10 21:21:55 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
wdenk03f5c552004-10-10 21:21:55 +0000156
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200157#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_FLASH_CFI
159#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk03f5c552004-10-10 21:21:55 +0000160
wdenk03f5c552004-10-10 21:21:55 +0000161
162/*
Jon Loeliger7202d432005-07-25 11:13:26 -0500163 * SDRAM on the Local Bus
wdenk03f5c552004-10-10 21:21:55 +0000164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
166#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk03f5c552004-10-10 21:21:55 +0000167
168/*
169 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk03f5c552004-10-10 21:21:55 +0000171 *
172 * For BR2, need:
173 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
174 * port-size = 32-bits = BR2[19:20] = 11
175 * no parity checking = BR2[21:22] = 00
176 * SDRAM for MSEL = BR2[24:26] = 011
177 * Valid = BR[31] = 1
178 *
179 * 0 4 8 12 16 20 24 28
180 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
181 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk03f5c552004-10-10 21:21:55 +0000183 * FIXME: the top 17 bits of BR2.
184 */
185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk03f5c552004-10-10 21:21:55 +0000187
188/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk03f5c552004-10-10 21:21:55 +0000190 *
191 * For OR2, need:
192 * 64MB mask for AM, OR2[0:7] = 1111 1100
193 * XAM, OR2[17:18] = 11
194 * 9 columns OR2[19-21] = 010
195 * 13 rows OR2[23-25] = 100
196 * EAD set for extra time OR[31] = 1
197 *
198 * 0 4 8 12 16 20 24 28
199 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
200 */
201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk03f5c552004-10-10 21:21:55 +0000203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
205#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
206#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
207#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
wdenk03f5c552004-10-10 21:21:55 +0000208
209/*
wdenk03f5c552004-10-10 21:21:55 +0000210 * Common settings for all Local Bus SDRAM commands.
211 * At run time, either BSMA1516 (for CPU 1.1)
212 * or BSMA1617 (for CPU 1.0) (old)
213 * is OR'ed in too.
214 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500215#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
216 | LSDMR_PRETOACT7 \
217 | LSDMR_ACTTORW7 \
218 | LSDMR_BL8 \
219 | LSDMR_WRC4 \
220 | LSDMR_CL3 \
221 | LSDMR_RFEN \
wdenk03f5c552004-10-10 21:21:55 +0000222 )
223
224/*
225 * The CADMUS registers are connected to CS3 on CDS.
226 * The new memory map places CADMUS at 0xf8000000.
227 *
228 * For BR3, need:
229 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
230 * port-size = 8-bits = BR[19:20] = 01
231 * no parity checking = BR[21:22] = 00
232 * GPMC for MSEL = BR[24:26] = 000
233 * Valid = BR[31] = 1
234 *
235 * 0 4 8 12 16 20 24 28
236 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
237 *
238 * For OR3, need:
239 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
240 * disable buffer ctrl OR[19] = 0
241 * CSNT OR[20] = 1
242 * ACS OR[21:22] = 11
243 * XACS OR[23] = 1
244 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
245 * SETA OR[28] = 0
246 * TRLX OR[29] = 1
247 * EHTR OR[30] = 1
248 * EAD extra time OR[31] = 1
249 *
250 * 0 4 8 12 16 20 24 28
251 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
252 */
253
Jon Loeliger25eedb22008-03-19 15:02:07 -0500254#define CONFIG_FSL_CADMUS
255
wdenk03f5c552004-10-10 21:21:55 +0000256#define CADMUS_BASE_ADDR 0xf8000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_BR3_PRELIM 0xf8000801
258#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
wdenk03f5c552004-10-10 21:21:55 +0000259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_INIT_RAM_LOCK 1
261#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
262#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenk03f5c552004-10-10 21:21:55 +0000263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
265#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
266#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk03f5c552004-10-10 21:21:55 +0000267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
269#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk03f5c552004-10-10 21:21:55 +0000270
271/* Serial Port */
272#define CONFIG_CONS_INDEX 2
273#undef CONFIG_SERIAL_SOFTWARE_FIFO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_NS16550
275#define CONFIG_SYS_NS16550_SERIAL
276#define CONFIG_SYS_NS16550_REG_SIZE 1
277#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk03f5c552004-10-10 21:21:55 +0000278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk03f5c552004-10-10 21:21:55 +0000280 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
283#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk03f5c552004-10-10 21:21:55 +0000284
285/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_HUSH_PARSER
287#ifdef CONFIG_SYS_HUSH_PARSER
288#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk03f5c552004-10-10 21:21:55 +0000289#endif
290
Matthew McClintock0e163872006-06-28 10:43:36 -0500291/* pass open firmware flat tree */
Kumar Galab90d2542007-11-29 00:11:44 -0600292#define CONFIG_OF_LIBFDT 1
293#define CONFIG_OF_BOARD_SETUP 1
294#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500295
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_64BIT_VSPRINTF 1
297#define CONFIG_SYS_64BIT_STRTOUL 1
Jon Loeligeraa11d852008-03-17 15:48:18 -0500298
Jon Loeliger20476722006-10-20 15:50:15 -0500299/*
300 * I2C
301 */
302#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
303#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk03f5c552004-10-10 21:21:55 +0000304#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
306#define CONFIG_SYS_I2C_SLAVE 0x7F
307#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
308#define CONFIG_SYS_I2C_OFFSET 0x3000
wdenk03f5c552004-10-10 21:21:55 +0000309
Timur Tabie8d18542008-07-18 16:52:23 +0200310/* EEPROM */
311#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_I2C_EEPROM_CCID
313#define CONFIG_SYS_ID_EEPROM
314#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
315#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabie8d18542008-07-18 16:52:23 +0200316
wdenk03f5c552004-10-10 21:21:55 +0000317/*
318 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300319 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk03f5c552004-10-10 21:21:55 +0000320 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600321#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600322#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600323#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600325#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600326#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
328#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000329
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600330#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600331#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600332#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600334#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600335#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
337#define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000338
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700339#ifdef CONFIG_LEGACY
340#define BRIDGE_ID 17
341#define VIA_ID 2
342#else
343#define BRIDGE_ID 28
344#define VIA_ID 4
345#endif
wdenk03f5c552004-10-10 21:21:55 +0000346
347#if defined(CONFIG_PCI)
348
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500349#define CONFIG_MPC85XX_PCI2
wdenk03f5c552004-10-10 21:21:55 +0000350#define CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200351#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk03f5c552004-10-10 21:21:55 +0000352
353#undef CONFIG_EEPRO100
354#undef CONFIG_TULIP
355
wdenk03f5c552004-10-10 21:21:55 +0000356#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk03f5c552004-10-10 21:21:55 +0000358
359#endif /* CONFIG_PCI */
360
361
362#if defined(CONFIG_TSEC_ENET)
363
364#ifndef CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200365#define CONFIG_NET_MULTI 1
wdenk03f5c552004-10-10 21:21:55 +0000366#endif
367
368#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500369#define CONFIG_TSEC1 1
370#define CONFIG_TSEC1_NAME "TSEC0"
371#define CONFIG_TSEC2 1
372#define CONFIG_TSEC2_NAME "TSEC1"
wdenk03f5c552004-10-10 21:21:55 +0000373#define TSEC1_PHY_ADDR 0
374#define TSEC2_PHY_ADDR 1
wdenk03f5c552004-10-10 21:21:55 +0000375#define TSEC1_PHYIDX 0
376#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500377#define TSEC1_FLAGS TSEC_GIGABIT
378#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500379
380/* Options are: TSEC[0-1] */
381#define CONFIG_ETHPRIME "TSEC0"
wdenk03f5c552004-10-10 21:21:55 +0000382
383#endif /* CONFIG_TSEC_ENET */
384
wdenk03f5c552004-10-10 21:21:55 +0000385/*
386 * Environment
387 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200388#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200390#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
391#define CONFIG_ENV_SIZE 0x2000
wdenk03f5c552004-10-10 21:21:55 +0000392
393#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk03f5c552004-10-10 21:21:55 +0000395
Jon Loeliger2835e512007-06-13 13:22:08 -0500396/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500397 * BOOTP options
398 */
399#define CONFIG_BOOTP_BOOTFILESIZE
400#define CONFIG_BOOTP_BOOTPATH
401#define CONFIG_BOOTP_GATEWAY
402#define CONFIG_BOOTP_HOSTNAME
403
404
405/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500406 * Command line configuration.
407 */
408#include <config_cmd_default.h>
409
410#define CONFIG_CMD_PING
411#define CONFIG_CMD_I2C
412#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600413#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500414#define CONFIG_CMD_IRQ
415#define CONFIG_CMD_SETEXPR
Jon Loeliger2835e512007-06-13 13:22:08 -0500416
wdenk03f5c552004-10-10 21:21:55 +0000417#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500418 #define CONFIG_CMD_PCI
wdenk03f5c552004-10-10 21:21:55 +0000419#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500420
wdenk03f5c552004-10-10 21:21:55 +0000421
422#undef CONFIG_WATCHDOG /* watchdog disabled */
423
424/*
425 * Miscellaneous configurable options
426 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kumar Gala22abb2d2007-11-29 10:34:28 -0600428#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
430#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger2835e512007-06-13 13:22:08 -0500431#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000433#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000435#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
437#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
438#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
439#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk03f5c552004-10-10 21:21:55 +0000440
441/*
442 * For booting Linux, the board info and command line data
443 * have to be in the first 8 MB of memory, since this is
444 * the maximum mapped by the Linux kernel during initialization.
445 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
wdenk03f5c552004-10-10 21:21:55 +0000447
wdenk03f5c552004-10-10 21:21:55 +0000448/*
449 * Internal Definitions
450 *
451 * Boot Flags
452 */
453#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
454#define BOOTFLAG_WARM 0x02 /* Software reboot */
455
Jon Loeliger2835e512007-06-13 13:22:08 -0500456#if defined(CONFIG_CMD_KGDB)
wdenk03f5c552004-10-10 21:21:55 +0000457#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
458#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
459#endif
460
wdenk03f5c552004-10-10 21:21:55 +0000461/*
462 * Environment Configuration
463 */
464
465/* The mac addresses for all ethernet interface */
466#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500467#define CONFIG_HAS_ETH0
wdenk03f5c552004-10-10 21:21:55 +0000468#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000469#define CONFIG_HAS_ETH1
wdenk03f5c552004-10-10 21:21:55 +0000470#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000471#define CONFIG_HAS_ETH2
wdenk03f5c552004-10-10 21:21:55 +0000472#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
473#endif
474
475#define CONFIG_IPADDR 192.168.1.253
476
477#define CONFIG_HOSTNAME unknown
478#define CONFIG_ROOTPATH /nfsroot
479#define CONFIG_BOOTFILE your.uImage
480
481#define CONFIG_SERVERIP 192.168.1.1
482#define CONFIG_GATEWAYIP 192.168.1.1
483#define CONFIG_NETMASK 255.255.255.0
484
485#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
486
487#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
488#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
489
490#define CONFIG_BAUDRATE 115200
491
492#define CONFIG_EXTRA_ENV_SETTINGS \
493 "netdev=eth0\0" \
494 "consoledev=ttyS1\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500495 "ramdiskaddr=600000\0" \
496 "ramdiskfile=your.ramdisk.u-boot\0" \
497 "fdtaddr=400000\0" \
498 "fdtfile=your.fdt.dtb\0"
wdenk03f5c552004-10-10 21:21:55 +0000499
500#define CONFIG_NFSBOOTCOMMAND \
501 "setenv bootargs root=/dev/nfs rw " \
502 "nfsroot=$serverip:$rootpath " \
503 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
504 "console=$consoledev,$baudrate $othbootargs;" \
505 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500506 "tftp $fdtaddr $fdtfile;" \
507 "bootm $loadaddr - $fdtaddr"
wdenk03f5c552004-10-10 21:21:55 +0000508
509#define CONFIG_RAMBOOTCOMMAND \
510 "setenv bootargs root=/dev/ram rw " \
511 "console=$consoledev,$baudrate $othbootargs;" \
512 "tftp $ramdiskaddr $ramdiskfile;" \
513 "tftp $loadaddr $bootfile;" \
514 "bootm $loadaddr $ramdiskaddr"
515
516#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
517
wdenk03f5c552004-10-10 21:21:55 +0000518#endif /* __CONFIG_H */