blob: 60a015c2ecc386ae28edd22ea29abfa8c32020b3 [file] [log] [blame]
wdenke887afc2002-08-27 09:44:07 +00001/*
2 * (C) Copyright 2000
3 * Subodh Nijsure, SkyStream Networks, snijsure@skystream.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
wdenke887afc2002-08-27 09:44:07 +000026#if defined(CONFIG_8xx)
27#include <mpc8xx.h>
28#elif defined (CONFIG_405GP)
29#include <asm/processor.h>
wdenk0db5bca2003-03-31 17:27:09 +000030#elif defined (CONFIG_5xx)
31#include <mpc5xx.h>
wdenke887afc2002-08-27 09:44:07 +000032#endif
33#if (CONFIG_COMMANDS & CFG_CMD_REGINFO)
34
35int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
36{
37#if defined(CONFIG_8xx)
38 volatile immap_t *immap = (immap_t *)CFG_IMMR;
39 volatile memctl8xx_t *memctl = &immap->im_memctl;
40 volatile sysconf8xx_t *sysconf = &immap->im_siu_conf;
41 volatile sit8xx_t *timers = &immap->im_sit;
42
43 /* Hopefully more PowerPC knowledgable people will add code to display
44 * other useful registers
45 */
46
47 printf("\nSystem Configuration registers\n");
48
49 printf("\tIMMR\t0x%08X\n", get_immr(0));
50
51 printf("\tSIUMCR\t0x%08X", sysconf->sc_siumcr);
52 printf("\tSYPCR\t0x%08X\n",sysconf->sc_sypcr);
53
54 printf("\tSWT\t0x%08X", sysconf->sc_swt);
55 printf("\tSWSR\t0x%04X\n", sysconf->sc_swsr);
56
57 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X\n",
58 sysconf->sc_sipend, sysconf->sc_simask);
59 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X\n",
60 sysconf->sc_siel, sysconf->sc_sivec);
61 printf("\tTESR\t0x%08X\tSDCR\t0x%08X\n",
62 sysconf->sc_tesr, sysconf->sc_sdcr);
63
64 printf("Memory Controller Registers\n");
65
66 printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
67 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
68 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
69 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
70 printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", memctl->memc_br4, memctl->memc_or4);
71 printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", memctl->memc_br5, memctl->memc_or5);
72 printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", memctl->memc_br6, memctl->memc_or6);
73 printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", memctl->memc_br7, memctl->memc_or7);
74 printf("\n");
75
76 printf("\tmamr\t0x%08X\tmbmr\t0x%08X \n",
77 memctl->memc_mamr, memctl->memc_mbmr );
78 printf("\tmstat\t0x%08X\tmptpr\t0x%08X \n",
79 memctl->memc_mstat, memctl->memc_mptpr );
80 printf("\tmdr\t0x%08X \n", memctl->memc_mdr);
81
82 printf("\nSystem Integration Timers\n");
83 printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n",
84 timers->sit_tbscr, timers->sit_rtcsc);
85 printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
86
87 /*
88 * May be some CPM info here?
89 */
90
91/* DBU[dave@cray.com] For the CRAY-L1, but should be generically 405gp */
stroeseb867d702003-05-23 11:18:02 +000092#elif defined (CONFIG_405GP) || defined(CONFIG_405EP)
wdenke887afc2002-08-27 09:44:07 +000093 printf("\n405GP registers; MSR=%x\n",mfmsr());
94 printf ("\nUniversal Interrupt Controller Regs\n"
95"uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
96"\n"
97"%08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
98 mfdcr(uicsr),
99 mfdcr(uicsrs),
100 mfdcr(uicer),
101 mfdcr(uiccr),
102 mfdcr(uicpr),
103 mfdcr(uictr),
104 mfdcr(uicmsr),
105 mfdcr(uicvr),
106 mfdcr(uicvcr));
107
108 printf ("\nMemory (SDRAM) Configuration\n"
109"besra besrsa besrb besrsb bear mcopt1 rtr pmit\n");
110
111 mtdcr(memcfga,mem_besra); printf ("%08x ", mfdcr(memcfgd));
112 mtdcr(memcfga,mem_besrsa); printf ("%08x ", mfdcr(memcfgd));
113 mtdcr(memcfga,mem_besrb); printf ("%08x ", mfdcr(memcfgd));
114 mtdcr(memcfga,mem_besrsb); printf ("%08x ", mfdcr(memcfgd));
115 mtdcr(memcfga,mem_bear); printf ("%08x ", mfdcr(memcfgd));
116 mtdcr(memcfga,mem_mcopt1); printf ("%08x ", mfdcr(memcfgd));
117 mtdcr(memcfga,mem_rtr); printf ("%08x ", mfdcr(memcfgd));
118 mtdcr(memcfga,mem_pmit); printf ("%08x ", mfdcr(memcfgd));
119
120 printf ("\n"
121"mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n");
122 mtdcr(memcfga,mem_mb0cf); printf ("%08x ", mfdcr(memcfgd));
123 mtdcr(memcfga,mem_mb1cf); printf ("%08x ", mfdcr(memcfgd));
124 mtdcr(memcfga,mem_mb2cf); printf ("%08x ", mfdcr(memcfgd));
125 mtdcr(memcfga,mem_mb3cf); printf ("%08x ", mfdcr(memcfgd));
126 mtdcr(memcfga,mem_sdtr1); printf ("%08x ", mfdcr(memcfgd));
127 mtdcr(memcfga,mem_ecccf); printf ("%08x ", mfdcr(memcfgd));
128 mtdcr(memcfga,mem_eccerr); printf ("%08x ", mfdcr(memcfgd));
129
130 printf ("\n\n"
131"DMA Channels\n"
132"dmasr dmasgc dmaadr\n" "%08x %08x %08x\n"
133"dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n"
134"dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n",
135mfdcr(dmasr), mfdcr(dmasgc),mfdcr(dmaadr),
136mfdcr(dmacr0), mfdcr(dmact0),mfdcr(dmada0), mfdcr(dmasa0), mfdcr(dmasb0),
137mfdcr(dmacr1), mfdcr(dmact1),mfdcr(dmada1), mfdcr(dmasa1), mfdcr(dmasb1));
138
139 printf (
140"dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n"
141"dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n",
142mfdcr(dmacr2), mfdcr(dmact2),mfdcr(dmada2), mfdcr(dmasa2), mfdcr(dmasb2),
143mfdcr(dmacr3), mfdcr(dmact3),mfdcr(dmada3), mfdcr(dmasa3), mfdcr(dmasb3) );
144
145 printf ("\n"
146"External Bus\n"
147"pbear pbesr0 pbesr1 epcr\n");
148 mtdcr(ebccfga,pbear); printf ("%08x ", mfdcr(ebccfgd));
149 mtdcr(ebccfga,pbesr0); printf ("%08x ", mfdcr(ebccfgd));
150 mtdcr(ebccfga,pbesr1); printf ("%08x ", mfdcr(ebccfgd));
151 mtdcr(ebccfga,epcr); printf ("%08x ", mfdcr(ebccfgd));
152
153 printf ("\n"
154"pb0cr pb0ap pb1cr bp1ap pb2cr pb2ap pb3cr pb3ap\n");
155 mtdcr(ebccfga,pb0cr); printf ("%08x ", mfdcr(ebccfgd));
156 mtdcr(ebccfga,pb0ap); printf ("%08x ", mfdcr(ebccfgd));
157 mtdcr(ebccfga,pb1cr); printf ("%08x ", mfdcr(ebccfgd));
158 mtdcr(ebccfga,pb1ap); printf ("%08x ", mfdcr(ebccfgd));
159 mtdcr(ebccfga,pb2cr); printf ("%08x ", mfdcr(ebccfgd));
160 mtdcr(ebccfga,pb2ap); printf ("%08x ", mfdcr(ebccfgd));
161 mtdcr(ebccfga,pb3cr); printf ("%08x ", mfdcr(ebccfgd));
162 mtdcr(ebccfga,pb3ap); printf ("%08x ", mfdcr(ebccfgd));
163
164 printf ("\n"
165"pb4cr pb4ap pb5cr bp5ap pb6cr pb6ap pb7cr pb7ap\n");
166 mtdcr(ebccfga,pb4cr); printf ("%08x ", mfdcr(ebccfgd));
167 mtdcr(ebccfga,pb4ap); printf ("%08x ", mfdcr(ebccfgd));
168 mtdcr(ebccfga,pb5cr); printf ("%08x ", mfdcr(ebccfgd));
169 mtdcr(ebccfga,pb5ap); printf ("%08x ", mfdcr(ebccfgd));
170 mtdcr(ebccfga,pb6cr); printf ("%08x ", mfdcr(ebccfgd));
171 mtdcr(ebccfga,pb6ap); printf ("%08x ", mfdcr(ebccfgd));
172 mtdcr(ebccfga,pb7cr); printf ("%08x ", mfdcr(ebccfgd));
173 mtdcr(ebccfga,pb7ap); printf ("%08x ", mfdcr(ebccfgd));
174
175 printf ("\n\n");
wdenk0db5bca2003-03-31 17:27:09 +0000176#elif defined(CONFIG_5xx)
wdenke887afc2002-08-27 09:44:07 +0000177
wdenk0db5bca2003-03-31 17:27:09 +0000178 volatile immap_t *immap = (immap_t *)CFG_IMMR;
179 volatile memctl5xx_t *memctl = &immap->im_memctl;
180 volatile sysconf5xx_t *sysconf = &immap->im_siu_conf;
181 volatile sit5xx_t *timers = &immap->im_sit;
182 volatile car5xx_t *car = &immap->im_clkrst;
183 volatile uimb5xx_t *uimb = &immap->im_uimb;
184
185 printf("\nSystem Configuration registers\n");
186 printf("\tIMMR\t0x%08X\tSIUMCR\t0x%08X \n", get_immr(0), sysconf->sc_siumcr);
187 printf("\tSYPCR\t0x%08X\tSWSR\t0x%04X \n" ,sysconf->sc_sypcr, sysconf->sc_swsr);
188 printf("\tSIPEND\t0x%08X\tSIMASK\t0x%08X \n", sysconf->sc_sipend, sysconf->sc_simask);
189 printf("\tSIEL\t0x%08X\tSIVEC\t0x%08X \n", sysconf->sc_siel, sysconf->sc_sivec);
190 printf("\tTESR\t0x%08X\n", sysconf->sc_tesr);
191
192 printf("\nMemory Controller Registers\n");
193 printf("\tBR0\t0x%08X\tOR0\t0x%08X \n", memctl->memc_br0, memctl->memc_or0);
194 printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", memctl->memc_br1, memctl->memc_or1);
195 printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", memctl->memc_br2, memctl->memc_or2);
196 printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", memctl->memc_br3, memctl->memc_or3);
197 printf("\tDMBR\t0x%08X\tDMOR\t0x%08X \n", memctl->memc_dmbr, memctl->memc_dmor );
198 printf("\tMSTAT\t0x%08X\n", memctl->memc_mstat);
199
200 printf("\nSystem Integration Timers\n");
201 printf("\tTBSCR\t0x%08X\tRTCSC\t0x%08X \n", timers->sit_tbscr, timers->sit_rtcsc);
202 printf("\tPISCR\t0x%08X \n", timers->sit_piscr);
203
204 printf("\nClocks and Reset\n");
205 printf("\tSCCR\t0x%08X\tPLPRCR\t0x%08X \n", car->car_sccr, car->car_plprcr);
206
207 printf("\nU-Bus to IMB3 Bus Interface\n");
208 printf("\tUMCR\t0x%08X\tUIPEND\t0x%08X \n", uimb->uimb_umcr, uimb->uimb_uipend);
209 printf ("\n\n");
210#endif /* CONFIG_5xx */
wdenke887afc2002-08-27 09:44:07 +0000211 return 0;
212}
213
wdenk0db5bca2003-03-31 17:27:09 +0000214#endif /* CONFIG_COMMANDS & CFG_CMD_REGINFO */
wdenk8bde7f72003-06-27 21:31:46 +0000215
216
217 /**************************************************/
218
219#if (defined(CONFIG_8xx) || defined(CONFIG_405GP)) && \
220 (CONFIG_COMMANDS & CFG_CMD_REGINFO)
221
wdenk0d498392003-07-01 21:06:45 +0000222U_BOOT_CMD(
223 reginfo, 2, 1, do_reginfo,
wdenk8bde7f72003-06-27 21:31:46 +0000224 "reginfo - print register information\n",
225);
226#endif