| Anton Staaf | 72d4dd4 | 2011-10-17 16:46:11 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011 The Chromium OS Authors. |
| 3 | * See file CREDITS for list of people who contributed to this |
| 4 | * project. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 | * MA 02111-1307 USA |
| 20 | */ |
| 21 | |
| 22 | #ifndef __MIPS_CACHE_H__ |
| 23 | #define __MIPS_CACHE_H__ |
| 24 | |
| 25 | /* |
| 26 | * The maximum L1 data cache line size on MIPS seems to be 128 bytes. We use |
| 27 | * that as a default for aligning DMA buffers unless the board config has |
| 28 | * specified another cache line size. |
| 29 | */ |
| 30 | #ifdef CONFIG_SYS_CACHELINE_SIZE |
| 31 | #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE |
| 32 | #else |
| 33 | #define ARCH_DMA_MINALIGN 128 |
| 34 | #endif |
| 35 | |
| 36 | #endif /* __MIPS_CACHE_H__ */ |