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wdenk56f94be2002-11-05 16:35:14 +00001/*
wdenk0608e042004-03-25 19:29:38 +00002 * (C) Copyright 2000-2004
wdenk56f94be2002-11-05 16:35:14 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
Heiko Schochere604e402010-07-19 23:46:48 +020026#include <command.h>
Heiko Schocher8011ec62010-07-19 23:47:08 +020027#include <libfdt.h>
wdenk56f94be2002-11-05 16:35:14 +000028#include <mpc8xx.h>
Heiko Schochere604e402010-07-19 23:46:48 +020029#include <hwconfig.h>
30#include <i2c.h>
wdenk0608e042004-03-25 19:29:38 +000031#include "../common/kup.h"
Heiko Schochere604e402010-07-19 23:46:48 +020032#include <asm/io.h>
33
34static unsigned char swapbyte(unsigned char c);
35static int read_diag(void);
wdenk56f94be2002-11-05 16:35:14 +000036
Wolfgang Denkd87080b2006-03-31 18:32:53 +020037DECLARE_GLOBAL_DATA_PTR;
38
Heiko Schochere604e402010-07-19 23:46:48 +020039/* ----------------------------------------------------------------------- */
wdenk56f94be2002-11-05 16:35:14 +000040
41#define _NOT_USED_ 0xFFFFFFFF
42
wdenk0608e042004-03-25 19:29:38 +000043const uint sdram_table[] = {
wdenk56f94be2002-11-05 16:35:14 +000044 /*
45 * Single Read. (Offset 0 in UPMA RAM)
46 */
wdenk682011f2003-06-03 23:54:09 +000047 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
Heiko Schochere604e402010-07-19 23:46:48 +020048 0x1FF77C47, /* last */
wdenk56f94be2002-11-05 16:35:14 +000049
50 /*
51 * SDRAM Initialization (offset 5 in UPMA RAM)
52 *
53 * This is no UPM entry point. The following definition uses
54 * the remaining space to establish an initialization
55 * sequence, which is executed by a RUN command.
56 *
57 */
Heiko Schochere604e402010-07-19 23:46:48 +020058 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
wdenk56f94be2002-11-05 16:35:14 +000059
60 /*
61 * Burst Read. (Offset 8 in UPMA RAM)
62 */
wdenk682011f2003-06-03 23:54:09 +000063 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
Heiko Schochere604e402010-07-19 23:46:48 +020064 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
wdenk56f94be2002-11-05 16:35:14 +000065 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
67
68 /*
69 * Single Write. (Offset 18 in UPMA RAM)
70 */
Heiko Schochere604e402010-07-19 23:46:48 +020071 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
wdenk56f94be2002-11-05 16:35:14 +000072 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
73
74 /*
75 * Burst Write. (Offset 20 in UPMA RAM)
76 */
wdenk682011f2003-06-03 23:54:09 +000077 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
Heiko Schochere604e402010-07-19 23:46:48 +020078 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
79 _NOT_USED_,
wdenk56f94be2002-11-05 16:35:14 +000080 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
81 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
82
83 /*
84 * Refresh (Offset 30 in UPMA RAM)
85 */
wdenk682011f2003-06-03 23:54:09 +000086 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
Heiko Schochere604e402010-07-19 23:46:48 +020087 0xFFFFFC84, 0xFFFFFC07, /* last */
88 _NOT_USED_, _NOT_USED_,
wdenk56f94be2002-11-05 16:35:14 +000089 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
90
91 /*
92 * Exception. (Offset 3c in UPMA RAM)
93 */
Heiko Schochere604e402010-07-19 23:46:48 +020094 0x7FFFFC07, /* last */
95 _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenk56f94be2002-11-05 16:35:14 +000096};
97
Heiko Schochere604e402010-07-19 23:46:48 +020098/* ----------------------------------------------------------------------- */
wdenk56f94be2002-11-05 16:35:14 +000099
100/*
101 * Check Board Identity:
102 */
103
Heiko Schochere604e402010-07-19 23:46:48 +0200104int checkboard(void)
wdenk56f94be2002-11-05 16:35:14 +0000105{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Heiko Schochere604e402010-07-19 23:46:48 +0200107 uchar rev,mod,tmp,pcf,ak_rev,ak_mod;
wdenk56f94be2002-11-05 16:35:14 +0000108
wdenk0608e042004-03-25 19:29:38 +0000109 /*
110 * Init ChipSelect #4 (CAN + HW-Latch)
111 */
Heiko Schochere604e402010-07-19 23:46:48 +0200112 out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
113 out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
114
115 /*
116 * Init ChipSelect #5 (S1D13768)
117 */
118 out_be32(&immap->im_memctl.memc_or5, CONFIG_SYS_OR5);
119 out_be32(&immap->im_memctl.memc_br5, CONFIG_SYS_BR5);
120
121 tmp = swapbyte(in_8((unsigned char*) LATCH_ADDR));
122 rev = (tmp & 0xF8) >> 3;
123 mod = (tmp & 0x07);
124
125 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
126
127 if (read_diag())
128 gd->flags &= ~GD_FLG_SILENT;
129
130 printf("Board: KUP4K Rev %d.%d AK:",rev,mod);
131 /*
132 * TI Application report: Before using the IO as an input,
133 * a high must be written to the IO first
134 */
135 pcf = 0xFF;
136 i2c_write(0x21, 0, 0 , &pcf, 1);
137 if (i2c_read(0x21, 0, 0, &pcf, 1)) {
138 puts("n/a\n");
139 } else {
140 ak_rev = (pcf & 0xF8) >> 3;
141 ak_mod = (pcf & 0x07);
142 printf("%d.%d\n", ak_rev, ak_mod);
143 }
144 return 0;
wdenk56f94be2002-11-05 16:35:14 +0000145}
146
Heiko Schochere604e402010-07-19 23:46:48 +0200147/* ----------------------------------------------------------------------- */
wdenk56f94be2002-11-05 16:35:14 +0000148
Heiko Schochere604e402010-07-19 23:46:48 +0200149
150phys_size_t initdram(int board_type)
wdenk56f94be2002-11-05 16:35:14 +0000151{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk682011f2003-06-03 23:54:09 +0000153 volatile memctl8xx_t *memctl = &immap->im_memctl;
Heiko Schochere604e402010-07-19 23:46:48 +0200154 long int size = 0;
Wolfgang Denkb8221a32011-11-04 15:55:34 +0000155 uchar *latch, rev, tmp;
wdenk56f94be2002-11-05 16:35:14 +0000156
wdenk682011f2003-06-03 23:54:09 +0000157 /*
Heiko Schochere604e402010-07-19 23:46:48 +0200158 * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision
159 * Rev 1..6 -> 48 MB RAM; Rev >= 7 -> 96 MB
wdenk682011f2003-06-03 23:54:09 +0000160 */
Heiko Schochere604e402010-07-19 23:46:48 +0200161 out_be32(&immap->im_memctl.memc_or4, CONFIG_SYS_OR4);
162 out_be32(&immap->im_memctl.memc_br4, CONFIG_SYS_BR4);
wdenk56f94be2002-11-05 16:35:14 +0000163
Heiko Schochere604e402010-07-19 23:46:48 +0200164 latch = (uchar *)0x90000200;
165 tmp = swapbyte(*latch);
166 rev = (tmp & 0xF8) >> 3;
wdenk56f94be2002-11-05 16:35:14 +0000167
Heiko Schochere604e402010-07-19 23:46:48 +0200168 upmconfig(UPMA, (uint *) sdram_table,
169 sizeof (sdram_table) / sizeof (uint));
wdenk682011f2003-06-03 23:54:09 +0000170
Heiko Schochere604e402010-07-19 23:46:48 +0200171 out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
wdenk56f94be2002-11-05 16:35:14 +0000172
Heiko Schochere604e402010-07-19 23:46:48 +0200173 out_be32(&memctl->memc_mar, 0x00000088);
174 /* no refresh yet */
175 if(rev >= 7) {
176 out_be32(&memctl->memc_mamr,
177 CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)));
178 } else {
179 out_be32(&memctl->memc_mamr,
180 CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)));
181 }
wdenk56f94be2002-11-05 16:35:14 +0000182
Heiko Schochere604e402010-07-19 23:46:48 +0200183 udelay(200);
wdenk56f94be2002-11-05 16:35:14 +0000184
wdenk682011f2003-06-03 23:54:09 +0000185 /* perform SDRAM initializsation sequence */
wdenk56f94be2002-11-05 16:35:14 +0000186
Heiko Schochere604e402010-07-19 23:46:48 +0200187 /* SDRAM bank 0 */
188 out_be32(&memctl->memc_mcr, 0x80002105);
189 udelay(1);
190 out_be32(&memctl->memc_mcr, 0x80002830); /* execute twice */
191 udelay(1);
192 out_be32(&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */
193 udelay(1);
wdenk56f94be2002-11-05 16:35:14 +0000194
Heiko Schochere604e402010-07-19 23:46:48 +0200195 /* SDRAM bank 1 */
196 out_be32(&memctl->memc_mcr, 0x80004105);
197 udelay(1);
198 out_be32(&memctl->memc_mcr, 0x80004830); /* execute twice */
199 udelay(1);
200 out_be32(&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */
201 udelay(1);
wdenk56f94be2002-11-05 16:35:14 +0000202
Heiko Schochere604e402010-07-19 23:46:48 +0200203 /* SDRAM bank 2 */
204 out_be32(&memctl->memc_mcr, 0x80006105);
205 udelay(1);
206 out_be32(&memctl->memc_mcr, 0x80006830); /* execute twice */
207 udelay(1);
208 out_be32(&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */
209 udelay(1);
wdenk56f94be2002-11-05 16:35:14 +0000210
Heiko Schochere604e402010-07-19 23:46:48 +0200211 setbits_be32(&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */
212 udelay(1000);
wdenk56f94be2002-11-05 16:35:14 +0000213
Heiko Schochere604e402010-07-19 23:46:48 +0200214 out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
215 udelay(1000);
216 if(rev >= 7) {
217 size = 32 * 3 * 1024 * 1024;
218 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_9COL);
219 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_9COL);
220 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_9COL);
221 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_9COL);
222 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_9COL);
223 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_9COL);
224 } else {
225 size = 16 * 3 * 1024 * 1024;
226 out_be32(&memctl->memc_or1, CONFIG_SYS_OR1_8COL);
227 out_be32(&memctl->memc_br1, CONFIG_SYS_BR1_8COL);
228 out_be32(&memctl->memc_or2, CONFIG_SYS_OR2_8COL);
229 out_be32(&memctl->memc_br2, CONFIG_SYS_BR2_8COL);
230 out_be32(&memctl->memc_or3, CONFIG_SYS_OR3_8COL);
231 out_be32(&memctl->memc_br3, CONFIG_SYS_BR3_8COL);
232 }
233 return (size);
wdenk56f94be2002-11-05 16:35:14 +0000234}
235
Heiko Schochere604e402010-07-19 23:46:48 +0200236/* ----------------------------------------------------------------------- */
wdenk56f94be2002-11-05 16:35:14 +0000237
Heiko Schochere604e402010-07-19 23:46:48 +0200238
239int misc_init_r(void)
wdenk56f94be2002-11-05 16:35:14 +0000240{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk56f94be2002-11-05 16:35:14 +0000242
wdenk1f53a412002-12-04 23:39:58 +0000243#ifdef CONFIG_IDE_LED
244 /* Configure PA8 as output port */
Heiko Schochere604e402010-07-19 23:46:48 +0200245 setbits_be16(&immap->im_ioport.iop_padir, PA_8);
246 setbits_be16(&immap->im_ioport.iop_paodr, PA_8);
247 clrbits_be16(&immap->im_ioport.iop_papar, PA_8);
248 setbits_be16(&immap->im_ioport.iop_padat, PA_8); /* turn it off */
wdenk1f53a412002-12-04 23:39:58 +0000249#endif
Mike Frysinger9c150102009-02-11 20:09:52 -0500250 load_sernum_ethaddr();
wdenk0608e042004-03-25 19:29:38 +0000251 setenv("hw","4k");
252 poweron_key();
wdenk682011f2003-06-03 23:54:09 +0000253 return (0);
wdenk56f94be2002-11-05 16:35:14 +0000254}
255
wdenk56f94be2002-11-05 16:35:14 +0000256
Heiko Schochere604e402010-07-19 23:46:48 +0200257static int read_diag(void)
wdenk682011f2003-06-03 23:54:09 +0000258{
Heiko Schochere604e402010-07-19 23:46:48 +0200259 int diag;
260 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
wdenk682011f2003-06-03 23:54:09 +0000261
Heiko Schochere604e402010-07-19 23:46:48 +0200262 clrbits_be16(&immr->im_ioport.iop_pcdir, PC_4); /* input */
263 clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
264 setbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* output */
265 clrbits_be16(&immr->im_ioport.iop_pcpar, PC_4); /* gpio */
266 setbits_be16(&immr->im_ioport.iop_pcdat, PC_5); /* 1 */
267 udelay(500);
268 if (in_be16(&immr->im_ioport.iop_pcdat) & PC_4) {
269 clrbits_be16(&immr->im_ioport.iop_pcdat, PC_5);/* 0 */
270 udelay(500);
271 if(in_be16(&immr->im_ioport.iop_pcdat) & PC_4)
272 diag = 0;
wdenk0608e042004-03-25 19:29:38 +0000273 else
Heiko Schochere604e402010-07-19 23:46:48 +0200274 diag = 1;
wdenk0608e042004-03-25 19:29:38 +0000275 } else {
Heiko Schochere604e402010-07-19 23:46:48 +0200276 diag = 0;
wdenk56f94be2002-11-05 16:35:14 +0000277 }
Heiko Schochere604e402010-07-19 23:46:48 +0200278 clrbits_be16(&immr->im_ioport.iop_pcdir, PC_5); /* input */
279 return (diag);
wdenk56f94be2002-11-05 16:35:14 +0000280}
Heiko Schochere604e402010-07-19 23:46:48 +0200281
282static unsigned char swapbyte(unsigned char c)
283{
284 unsigned char result = 0;
285 int i = 0;
286
287 for(i = 0; i < 8; ++i) {
288 result = result << 1;
289 result |= (c & 1);
290 c = c >> 1;
291 }
292 return result;
293}
Heiko Schocher8011ec62010-07-19 23:47:08 +0200294
295/*
296 * Device Tree Support
297 */
298#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
299void ft_board_setup(void *blob, bd_t *bd)
300{
301 ft_cpu_setup(blob, bd);
302}
303#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */