blob: 992443a8e2f6b104e5fb70ae4bf477c98a9ca495 [file] [log] [blame]
Matthias Fuchs99d8b232009-07-22 13:56:21 +02001/*
2 * (C) Copyright 2009
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd.eu
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#define CONFIG_405EP 1 /* This is a PPC405 CPU */
28#define CONFIG_4xx 1 /* ...member of PPC4xx family */
29#define CONFIG_PMC405DE 1 /* ...on a PMC405DE board */
30
Wolfgang Denk2ae18242010-10-06 09:05:45 +020031#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
32
Matthias Fuchs99d8b232009-07-22 13:56:21 +020033#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
34#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
35#define CONFIG_BOARD_TYPES 1 /* support board types */
36
37#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
38
39#define CONFIG_BAUDRATE 115200
40#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
41
42#undef CONFIG_BOOTARGS
43#undef CONFIG_BOOTCOMMAND
44
45#define CONFIG_PREBOOT /* enable preboot variable */
46
47#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change*/
48
Matthias Fuchs99d8b232009-07-22 13:56:21 +020049#define CONFIG_HAS_ETH1
50
51#define CONFIG_PPC4xx_EMAC
52#define CONFIG_MII 1 /* MII PHY management */
53#define CONFIG_PHY_ADDR 1 /* PHY address */
54#define CONFIG_PHY1_ADDR 2 /* 2nd PHY address */
55
56#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
57
58/*
59 * BOOTP options
60 */
61#define CONFIG_BOOTP_SUBNETMASK
62#define CONFIG_BOOTP_GATEWAY
63#define CONFIG_BOOTP_HOSTNAME
64#define CONFIG_BOOTP_BOOTPATH
65#define CONFIG_BOOTP_DNS
66#define CONFIG_BOOTP_DNS2
67#define CONFIG_BOOTP_SEND_HOSTNAME
68
69/*
70 * Command line configuration.
71 */
72#include <config_cmd_default.h>
73
74#define CONFIG_CMD_BSP
75#define CONFIG_CMD_CHIP_CONFIG
76#define CONFIG_CMD_DATE
77#define CONFIG_CMD_DHCP
78#define CONFIG_CMD_EEPROM
79#define CONFIG_CMD_ELF
80#define CONFIG_CMD_I2C
81#define CONFIG_CMD_IRQ
82#define CONFIG_CMD_MII
83#define CONFIG_CMD_NFS
84#define CONFIG_CMD_PCI
85#define CONFIG_CMD_PING
86
87#define CONFIG_OF_LIBFDT
88#define CONFIG_OF_BOARD_SETUP
89
90#undef CONFIG_WATCHDOG /* watchdog disabled */
91#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
92#define CONFIG_PRAM 0
93
94/*
95 * Miscellaneous configurable options
96 */
97#define CONFIG_SYS_LONGHELP
98#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
99
100#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
101#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
102#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
103#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
104
105#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
106#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */
107
108#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
109#define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */
110
Stefan Roese550650d2010-09-20 16:05:31 +0200111#define CONFIG_CONS_INDEX 2 /* Use UART1 */
112#define CONFIG_SYS_NS16550
113#define CONFIG_SYS_NS16550_SERIAL
114#define CONFIG_SYS_NS16550_REG_SIZE 1
115#define CONFIG_SYS_NS16550_CLK get_serial_clock()
116
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200117#undef CONFIG_SYS_EXT_SERIAL_CLOCK
118#define CONFIG_SYS_BASE_BAUD 691200
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200119
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200120#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
121#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
122
123#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
124
125#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
126#define CONFIG_LOOPW 1 /* enable loopw command */
127#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
128#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
129#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
130
131#define CONFIG_AUTOBOOT_KEYED 1
132#define CONFIG_AUTOBOOT_PROMPT \
133 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
134#undef CONFIG_AUTOBOOT_DELAY_STR
135#define CONFIG_AUTOBOOT_STOP_STR " "
136
137/*
138 * PCI stuff
139 */
140#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
141#define PCI_HOST_FORCE 1 /* configure as pci host */
142#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
143
144#define CONFIG_PCI /* include pci support */
145#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
146#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
147
148#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
149
150/*
151 * PCI identification
152 */
153#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
154#define CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH 0x040e /* Dev ID: Non-Monarch */
155#define CONFIG_SYS_PCI_SUBSYS_ID_MONARCH 0x040f /* Dev ID: Monarch */
156#define CONFIG_SYS_PCI_CLASSCODE_NONMONARCH PCI_CLASS_PROCESSOR_POWERPC
157#define CONFIG_SYS_PCI_CLASSCODE_MONARCH PCI_CLASS_BRIDGE_HOST
158
159#define CONFIG_SYS_PCI_CLASSCODE CONFIG_SYS_PCI_CLASSCODE_MONARCH
160#define CONFIG_SYS_PCI_SUBSYS_DEVICEID CONFIG_SYS_PCI_SUBSYS_ID_MONARCH
161
162#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
163#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable=1 */
164#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
165#define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to CPLD, GPIO */
166#define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable=1 */
167#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
168
Matthias Fuchs82379b52009-09-07 17:00:41 +0200169#define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
170
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200171/*
172 * For booting Linux, the board info and command line data
173 * have to be in the first 8 MB of memory, since this is
174 * the maximum mapped by the Linux kernel during initialization.
175 */
176#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
177/*
178 * FLASH organization
179 */
180#define CONFIG_SYS_FLASH_CFI 1 /* CFI compatible */
181#define CONFIG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
182
183#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
184
185#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max. no. memory banks */
186#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per chip */
187
188#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* erase timeout (in ms) */
189#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* write timeout (in ms) */
190
191#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* buffered writes (faster) */
192#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */
193
194#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* 'E' for empty sector (flinfo) */
195#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
196
197
198/*
199 * Start addresses for the final memory configuration
200 * (Set up by the startup code)
201 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
202 */
203#define CONFIG_SYS_SDRAM_BASE 0x00000000
204#define CONFIG_SYS_FLASH_BASE 0xfe000000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200205#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
206#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200207#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
208
209/*
210 * Environment in EEPROM setup
211 */
212#define CONFIG_ENV_IS_IN_EEPROM 1
213#define CONFIG_ENV_OFFSET 0x100
214#define CONFIG_ENV_SIZE 0x700
215
216/*
217 * I2C EEPROM (24W16) for environment
218 */
219#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200220#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200221#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
222#define CONFIG_SYS_I2C_SLAVE 0x7F
223
224#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24W16 */
225#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
226/* mask of address bits that overflow into the "EEPROM chip address" */
227#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
228#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
229 /* 16 byte page write mode using*/
230 /* last 4 bits of the address */
231#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
232#define CONFIG_SYS_EEPROM_WREN 1
233
234#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
235#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0x40
236#define CONFIG_4xx_CONFIG_BLOCKSIZE 0x20
237
238/*
239 * RTC
240 */
241#define CONFIG_RTC_RX8025
242
243/*
244 * External Bus Controller (EBC) Setup
245 * (max. 55MHZ EBC clock)
246 */
247/* Memory Bank 0 (NOR flash) BAS=0xFE0,BS=32MB,BU=R/W,BW=16bit */
248#define CONFIG_SYS_EBC_PB0AP 0x03017200
249#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xba000)
250
251/* Memory Bank 1 (CPLD) BAS=0xEF0,BS=16MB,BU=R/W,BW=16bit */
252#define CONFIG_SYS_CPLD_BASE 0xef000000
253#define CONFIG_SYS_EBC_PB1AP 0x00800000
254#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
255
256/*
257 * Definitions for initial stack pointer and data area (in data cache)
258 */
259/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
260#define CONFIG_SYS_TEMP_STACK_OCM 1
261
262/* On Chip Memory location */
263#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
264#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
265/* inside SDRAM */
266#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
267/* End of used area in RAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200268#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200269
Wolfgang Denk553f0982010-10-26 13:32:32 +0200270#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200271 GENERATED_GBL_DATA_SIZE)
Matthias Fuchs99d8b232009-07-22 13:56:21 +0200272#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
273
274/*
275 * GPIO Configuration
276 */
277#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alt1 */ \
278{ \
279/* GPIO Core 0 */ \
280{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
281{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
282{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
283{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
284{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
285{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
286{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO6 TS4 */ \
287{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 TS5 */ \
288{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
289{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO9 TrcClk */ \
290{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
291{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
292{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
293{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
294{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
295{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
296{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
297{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
298{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
299{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
300{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
301{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
302{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
303{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
304{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
305{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
306{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
307{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
308{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
309{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
310{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
311{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
312} \
313}
314
315#define CONFIG_SYS_GPIO_HWREV_MASK (0xf0000000 >> 1) /* GPIO1..4 */
316#define CONFIG_SYS_GPIO_HWREV_SHIFT 27
317#define CONFIG_SYS_GPIO_LEDRUN_N (0x80000000 >> 5) /* GPIO5 */
318#define CONFIG_SYS_GPIO_LEDA_N (0x80000000 >> 6) /* GPIO6 */
319#define CONFIG_SYS_GPIO_LEDB_N (0x80000000 >> 7) /* GPIO7 */
320#define CONFIG_SYS_GPIO_SELFRST_N (0x80000000 >> 8) /* GPIO8 */
321#define CONFIG_SYS_GPIO_EEPROM_WP (0x80000000 >> 9) /* GPIO9 */
322#define CONFIG_SYS_GPIO_MONARCH_N (0x80000000 >> 11) /* GPIO11 */
323#define CONFIG_SYS_GPIO_EREADY (0x80000000 >> 12) /* GPIO12 */
324#define CONFIG_SYS_GPIO_M66EN (0x80000000 >> 13) /* GPIO13 */
325
326/*
327 * Default speed selection (cpu_plb_opb_ebc) in mhz.
328 * This value will be set if iic boot eprom is disabled.
329 */
330#undef CONFIG_SYS_FCPU333MHZ
331#define CONFIG_SYS_FCPU266MHZ
332#undef CONFIG_SYS_FCPU133MHZ
333
334#if defined(CONFIG_SYS_FCPU333MHZ)
335/*
336 * CPU: 333MHz
337 * PLB/SDRAM/MAL: 111MHz
338 * OPB: 55MHz
339 * EBC: 55MHz
340 * PCI: 55MHz (111MHz on M66EN=1)
341 */
342#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
343 PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \
344 PLL_MALDIV_1 | PLL_PCIDIV_2)
345#define PLLMR1_DEFAULT (PLL_FBKDIV_10 | \
346 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
347 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
348#endif
349
350#if defined(CONFIG_SYS_FCPU266MHZ)
351/*
352 * CPU: 266MHz
353 * PLB/SDRAM/MAL: 133MHz
354 * OPB: 66MHz
355 * EBC: 44MHz
356 * PCI: 44MHz (66MHz on M66EN=1)
357 */
358#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
359 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
360 PLL_MALDIV_1 | PLL_PCIDIV_3)
361#define PLLMR1_DEFAULT (PLL_FBKDIV_8 | \
362 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
363 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
364#endif
365
366#if defined(CONFIG_SYS_FCPU133MHZ)
367/*
368 * CPU: 133MHz
369 * PLB/SDRAM/MAL: 133MHz
370 * OPB: 66MHz
371 * EBC: 44MHz
372 * PCI: 44MHz (66MHz on M66EN=1)
373 */
374#define PLLMR0_DEFAULT (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
375 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
376 PLL_MALDIV_1 | PLL_PCIDIV_3)
377#define PLLMR1_DEFAULT (PLL_FBKDIV_4 | \
378 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
379 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
380#endif
381
382#endif /* __CONFIG_H */