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dzu@denx.de6ca24c62006-04-21 18:30:47 +02001/*
2 * -- Version 1.1 --
3 *
4 * (C) Copyright 2003-2005
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * (C) Copyright 2004-2005
8 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
9 *
10 * (C) Copyright 2005
11 * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
12 *
13 * History:
14 * 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
15 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020016 * SPDX-License-Identifier: GPL-2.0+
dzu@denx.de6ca24c62006-04-21 18:30:47 +020017 */
18
19#ifndef __CONFIG_H
20#define __CONFIG_H
21
22/*
23 * High Level Configuration Options
24 */
25#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
26#define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
27#define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
28
Wolfgang Denk610cf362006-05-03 01:24:04 +020029#define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
30#define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
31#define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
dzu@denx.de6ca24c62006-04-21 18:30:47 +020032#define CONFIG_BC3450_USB 1 /* + USB support */
33# define CONFIG_FAT 1 /* + FAT support */
34# define CONFIG_EXT2 1 /* + EXT2 support */
35#undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
36#undef CONFIG_BC3450_CAN /* + CAN transceiver */
37#undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
Wolfgang Denk610cf362006-05-03 01:24:04 +020038#undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
39#undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
dzu@denx.de6ca24c62006-04-21 18:30:47 +020040#define CONFIG_BC3450_FP 1 /* + enable FP O/P */
41#undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
42
Wolfgang Denk2ae18242010-10-06 09:05:45 +020043/*
44 * Valid values for CONFIG_SYS_TEXT_BASE are:
45 * 0xFC000000 boot low (standard configuration with room for
46 * max 64 MByte Flash ROM)
47 * 0x00100000 boot from RAM (for testing only)
48 */
49#ifndef CONFIG_SYS_TEXT_BASE
50#define CONFIG_SYS_TEXT_BASE 0xFC000000
51#endif
52
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
dzu@denx.de6ca24c62006-04-21 18:30:47 +020054
Becky Bruce31d82672008-05-08 19:02:12 -050055#define CONFIG_HIGH_BATS 1 /* High BATs supported */
56
dzu@denx.de6ca24c62006-04-21 18:30:47 +020057/*
58 * Serial console configuration
59 */
60#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
61#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
dzu@denx.de6ca24c62006-04-21 18:30:47 +020063
64/*
65 * AT-PS/2 Multiplexer
66 */
67#ifdef CONFIG_BC3450_PS2
68# define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
69# define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
70# define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071# define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
dzu@denx.de6ca24c62006-04-21 18:30:47 +020072# define CONFIG_BOARD_EARLY_INIT_R
73#endif /* CONFIG_BC3450_PS2 */
74
75/*
76 * PCI Mapping:
77 * 0x40000000 - 0x4fffffff - PCI Memory
78 * 0x50000000 - 0x50ffffff - PCI IO Space
79 */
80# define CONFIG_PCI 1
81# define CONFIG_PCI_PNP 1
Wolfgang Denk610cf362006-05-03 01:24:04 +020082/* #define CONFIG_PCI_SCAN_SHOW 1 */
TsiChung Liewf33fca22008-03-30 01:19:06 -050083#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
dzu@denx.de6ca24c62006-04-21 18:30:47 +020084
85#define CONFIG_PCI_MEM_BUS 0x40000000
86#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
87#define CONFIG_PCI_MEM_SIZE 0x10000000
88
89#define CONFIG_PCI_IO_BUS 0x50000000
90#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
91#define CONFIG_PCI_IO_SIZE 0x01000000
92
dzu@denx.de6ca24c62006-04-21 18:30:47 +020093/*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
dzu@denx.de6ca24c62006-04-21 18:30:47 +020095#define CONFIG_NS8382X 1
96
dzu@denx.de6ca24c62006-04-21 18:30:47 +020097/*
98 * Video console
99 */
100# define CONFIG_VIDEO
101# define CONFIG_VIDEO_SM501
102# define CONFIG_VIDEO_SM501_32BPP
103# define CONFIG_CFB_CONSOLE
104# define CONFIG_VIDEO_LOGO
105# define CONFIG_VGA_AS_SINGLE_DEVICE
106# define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
107# define CONFIG_VIDEO_SW_CURSOR
108# define CONFIG_SPLASH_SCREEN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109# define CONFIG_SYS_CONSOLE_IS_IN_ENV
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200110
Wolfgang Denk610cf362006-05-03 01:24:04 +0200111/*
112 * Partitions
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200113 */
114#define CONFIG_MAC_PARTITION
115#define CONFIG_DOS_PARTITION
116#define CONFIG_ISO_PARTITION
117
Wolfgang Denk610cf362006-05-03 01:24:04 +0200118/*
119 * USB
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200120 */
121#ifdef CONFIG_BC3450_USB
122# define CONFIG_USB_OHCI
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200123# define CONFIG_USB_STORAGE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200124#endif /* CONFIG_BC3450_USB */
125
Wolfgang Denk610cf362006-05-03 01:24:04 +0200126/*
127 * POST support
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200128 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
130 CONFIG_SYS_POST_CPU | \
131 CONFIG_SYS_POST_I2C)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200132
133#ifdef CONFIG_POST
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200134/* preserve space for the post_word at end of on-chip SRAM */
135# define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200136#endif /* CONFIG_POST */
137
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500138
Wolfgang Denk610cf362006-05-03 01:24:04 +0200139/*
Jon Loeliger11799432007-07-10 09:02:57 -0500140 * BOOTP options
141 */
142#define CONFIG_BOOTP_BOOTFILESIZE
143#define CONFIG_BOOTP_BOOTPATH
144#define CONFIG_BOOTP_GATEWAY
145#define CONFIG_BOOTP_HOSTNAME
146
147
148/*
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500149 * Command line configuration.
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200150 */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500151#include <config_cmd_default.h>
152
153#define CONFIG_CMD_ASKENV
154#define CONFIG_CMD_DATE
155#define CONFIG_CMD_DHCP
156#define CONFIG_CMD_ECHO
157#define CONFIG_CMD_EEPROM
158#define CONFIG_CMD_I2C
159#define CONFIG_CMD_JFFS2
160#define CONFIG_CMD_MII
161#define CONFIG_CMD_NFS
162#define CONFIG_CMD_PING
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500163#define CONFIG_CMD_REGINFO
164#define CONFIG_CMD_SNTP
165#define CONFIG_CMD_BSP
166
167#ifdef CONFIG_VIDEO
168 #define CONFIG_CMD_BMP
169#endif
170
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200171#ifdef CONFIG_BC3450_IDE
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500172 #define CONFIG_CMD_IDE
173#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200174
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500175#if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
176 #ifdef CONFIG_FAT
177 #define CONFIG_CMD_FAT
178 #endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200179
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500180 #ifdef CONFIG_EXT2
181 #define CONFIG_CMD_EXT2
182 #endif
183#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200184
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500185#ifdef CONFIG_BC3450_USB
186 #define CONFIG_CMD_USB
187#endif
Wolfgang Denk5728be32007-08-06 01:01:49 +0200188
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500189#ifdef CONFIG_PCI
190 #define CONFIG_CMD_PCI
191#endif
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200192
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500193#ifdef CONFIG_POST
194 #define CONFIG_CMD_DIAG
195#endif
196
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200197
Wolfgang Denk610cf362006-05-03 01:24:04 +0200198#define CONFIG_TIMESTAMP /* display image timestamps */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200199
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200200#if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201# define CONFIG_SYS_LOWBOOT 1
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200202#endif
203
204/*
205 * Autobooting
206 */
207#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
208#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
209
210#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100211 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200212 "echo;"
213
214#undef CONFIG_BOOTARGS
215
216#define CONFIG_EXTRA_ENV_SETTINGS \
217 "netdev=eth0\0" \
218 "ipaddr=192.168.1.10\0" \
219 "serverip=192.168.1.3\0" \
220 "netmask=255.255.255.0\0" \
Wolfgang Denk610cf362006-05-03 01:24:04 +0200221 "hostname=bc3450\0" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200222 "rootpath=/opt/eldk/ppc_6xx\0" \
Wolfgang Denk610cf362006-05-03 01:24:04 +0200223 "kernel_addr=fc0a0000\0" \
224 "ramdisk_addr=fc1c0000\0" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200225 "ramargs=setenv bootargs root=/dev/ram rw\0" \
226 "nfsargs=setenv bootargs root=/dev/nfs rw " \
227 "nfsroot=$(serverip):$(rootpath)\0" \
Wolfgang Denk610cf362006-05-03 01:24:04 +0200228 "ideargs=setenv bootargs root=/dev/hda2 ro\0" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200229 "addip=setenv bootargs $(bootargs) " \
230 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
231 ":$(hostname):$(netdev):off panic=1\0" \
232 "addcons=setenv bootargs $(bootargs) " \
233 "console=ttyS0,$(baudrate) console=tty0\0" \
234 "flash_self=run ramargs addip addcons;" \
235 "bootm $(kernel_addr) $(ramdisk_addr)\0" \
236 "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
237 "net_nfs=tftp 200000 $(bootfile); " \
238 "run nfsargs addip addcons; bootm\0" \
Wolfgang Denk610cf362006-05-03 01:24:04 +0200239 "ide_nfs=run nfsargs addip addcons; " \
240 "disk 200000 0:1; bootm\0" \
241 "ide_ide=run ideargs addip addcons; " \
242 "disk 200000 0:1; bootm\0" \
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200243 "usb_self=run usbload; run ramargs addip addcons; " \
244 "bootm 200000 400000\0" \
245 "usbload=usb reset; usb scan; usbboot 200000 0:1; " \
246 "usbboot 400000 0:2\0" \
247 "bootfile=uImage\0" \
248 "load=tftp 200000 $(u-boot)\0" \
249 "u-boot=u-boot.bin\0" \
250 "update=protect off FC000000 FC05FFFF;" \
251 "erase FC000000 FC05FFFF;" \
252 "cp.b 200000 FC000000 $(filesize);" \
253 "protect on FC000000 FC05FFFF\0" \
254 ""
255
256#define CONFIG_BOOTCOMMAND "run flash_self"
257
258/*
259 * IPB Bus clocking configuration.
260 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200262
263/*
264 * PCI Bus clocking configuration
265 *
266 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200268 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200269 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
271# define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200272#endif
273
274/*
275 * I2C configuration
276 */
277#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200279
280/*
281 * I2C clock frequency
282 *
283 * Please notice, that the resulting clock frequency could differ from the
284 * configured value. This is because the I2C clock is derived from system
285 * clock over a frequency divider with only a few divider values. U-boot
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200287 * approximation allways lies below the configured value, never above.
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
290#define CONFIG_SYS_I2C_SLAVE 0x7F
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200291
292/*
Wolfgang Denk610cf362006-05-03 01:24:04 +0200293 * EEPROM configuration for I²C EEPROM M24C32
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200294 * M24C64 should work also. For other EEPROMs config should be verified.
Wolfgang Denk610cf362006-05-03 01:24:04 +0200295 *
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200296 * The TQM5200 module may hold an EEPROM at address 0x50.
297 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
299#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
300#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
301#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200302
303/*
304 * RTC configuration
305 */
306#if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
307# define CONFIG_RTC_M41T11 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308# define CONFIG_SYS_I2C_RTC_ADDR 0x68
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200309#else
310# define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
311# define CONFIG_BOARD_EARLY_INIT_R
312#endif
313
314/*
315 * Flash configuration
316 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200317#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200318
319/* use CFI flash driver if no module variant is spezified */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200321#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
323#define CONFIG_SYS_FLASH_EMPTY_INFO
324#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
325#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
326#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#if !defined(CONFIG_SYS_LOWBOOT)
329#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
330#else /* CONFIG_SYS_LOWBOOT */
331#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
332#endif /* CONFIG_SYS_LOWBOOT */
333#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200334 (= chip selects) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
336#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200337
338/* Dynamic MTD partition support */
Stefan Roese68d7d652009-03-19 13:30:36 +0100339#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200340#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
341#define CONFIG_FLASH_CFI_MTD
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200342#define MTDIDS_DEFAULT "nor0=TQM5200-0"
343#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
344 "1408k(kernel)," \
345 "2m(initrd)," \
346 "4m(small-fs)," \
347 "16m(big-fs)," \
348 "8m(misc)"
349
350/*
351 * Environment settings
352 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200353#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200354#define CONFIG_ENV_SIZE 0x10000
355#define CONFIG_ENV_SECT_SIZE 0x20000
356#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
357#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200358
359/*
360 * Memory map
361 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_MBAR 0xF0000000
363#define CONFIG_SYS_SDRAM_BASE 0x00000000
364#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200365
366/* Use ON-Chip SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200368#ifdef CONFIG_POST
369/* preserve space for the post_word at end of on-chip SRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200370# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200371#else
Wolfgang Denk553f0982010-10-26 13:32:32 +0200372# define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200373#endif /*CONFIG_POST*/
374
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200375#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200377
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200378#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
380# define CONFIG_SYS_RAMBOOT 1
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200381#endif
382
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
384#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
385#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200386
387/*
388 * Ethernet configuration
389 *
Ben Warren86321fc2009-02-05 23:58:25 -0800390 * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200391 */
392#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800393#define CONFIG_MPC5xxx_FEC_MII100
394#undef CONFIG_MPC5xxx_MII10
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200395#define CONFIG_PHY_ADDR 0x00
396
397/*
398 * GPIO configuration on BC3450
399 *
Wolfgang Denk610cf362006-05-03 01:24:04 +0200400 * PSC1: UART1 (Service-UART) [0x xxxxxxx4]
401 * PSC2: UART2 [0x xxxxxx4x]
402 * or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
403 * PSC3: USB2 [0x xxxxx1xx]
404 * USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
405 * (this has to match
406 * CONFIG_USB_CONFIG which is
407 * used by usb_ohci.c to set
408 * the USB ports)
409 * Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
410 * (this is reset to '5'
411 * in FEC driver: fec.c)
412 * PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
413 * ATA/CS: ??? [0x x1xxxxxx]
414 * FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200415 * CS1: Use Pin gpio_wkup_6 as second
Wolfgang Denk610cf362006-05-03 01:24:04 +0200416 * SDRAM chip select (mem_cs1)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200417 * Timer: CAN2 / SPI
Wolfgang Denk610cf362006-05-03 01:24:04 +0200418 * I2C: CAN1 / I²C2 [0x bxxxxxxx]
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200419 */
420#ifdef CONFIG_BC3450_AC97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200422#else /* PSC2=UART2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423# define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200424#endif
425
426/*
427 * Miscellaneous configurable options
428 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500430#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200432#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200434#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
436#define CONFIG_SYS_MAXARGS 16 /* max no of command args */
437#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200438
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200440 /* more extensive mem test */
441
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
443#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200446
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500448#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500450#endif
451
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200452/*
Jon Loeliger11799432007-07-10 09:02:57 -0500453 * Enable loopw command.
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200454 */
455#define CONFIG_LOOPW
456
457/*
458 * Various low-level settings
459 */
Detlev Zundelfd428c02010-03-12 10:01:12 +0100460#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
461#define CONFIG_SYS_HID0_FINAL HID0_ICE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200462
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
464#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
465#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
466# define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200467#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468# define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200469#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
471#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200472
473/* automatic configuration of chip selects */
474#ifdef CONFIG_TQM5200
475# define CONFIG_LAST_STAGE_INIT
476#endif /* CONFIG_TQM5200 */
477
478/*
479 * SRAM - Do not map below 2 GB in address space, because this area is used
480 * for SDRAM autosizing.
481 */
482#ifdef CONFIG_TQM5200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200483# define CONFIG_SYS_CS2_START 0xE5000000
484# define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
485# define CONFIG_SYS_CS2_CFG 0x0004D930
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200486#endif /* CONFIG_TQM5200 */
487
488/*
489 * Grafic controller - Do not map below 2 GB in address space, because this
490 * area is used for SDRAM autosizing.
491 */
492#ifdef CONFIG_TQM5200
493# define SM501_FB_BASE 0xE0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494# define CONFIG_SYS_CS1_START (SM501_FB_BASE)
495# define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
496# define CONFIG_SYS_CS1_CFG 0x8F48FF70
497# define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200498#endif /* CONFIG_TQM5200 */
499
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_CS_BURST 0x00000000
501#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200502 /* flash and SM501 */
503
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_RESET_ADDRESS 0xff000000
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200505
506/*
507 * USB stuff
508 */
509#define CONFIG_USB_CLOCK 0x0001BBBB
Wolfgang Denk610cf362006-05-03 01:24:04 +0200510#define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200511
512/*
513 * IDE/ATA stuff Supports IDE harddisk
514 */
515#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
516
Wolfgang Denk610cf362006-05-03 01:24:04 +0200517#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
518#undef CONFIG_IDE_LED /* LED for ide not supported */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200519
Wolfgang Denk610cf362006-05-03 01:24:04 +0200520#define CONFIG_IDE_RESET /* reset for ide supported */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200521#define CONFIG_IDE_PREINIT
522
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
524#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200525
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200526#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200527
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200528#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200529
530/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200531#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200532
533/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200534#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200535
536/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200537#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200538
539/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540#define CONFIG_SYS_ATA_STRIDE 4
dzu@denx.de6ca24c62006-04-21 18:30:47 +0200541
542#endif /* __CONFIG_H */