blob: 66893688e6aa51b937e2f05812f344143a45ad36 [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +00007 */
8
wdenk0ac6f8b2004-07-09 23:27:13 +00009/*
10 * mpc8540ads board configuration file
11 *
12 * Please refer to doc/README.mpc85xx for more info.
13 *
14 * Make sure you change the MAC address and other network params first,
15 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
wdenk42d1f032003-10-15 23:53:47 +000016 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21/* High Level Configuration Options */
wdenk0ac6f8b2004-07-09 23:27:13 +000022#define CONFIG_BOOKE 1 /* BOOKE */
23#define CONFIG_E500 1 /* BOOKE e500 family */
24#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
25#define CONFIG_MPC8540 1 /* MPC8540 specific */
26#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
wdenk42d1f032003-10-15 23:53:47 +000027
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028/*
29 * default CCARBAR is at 0xff700000
30 * assume U-Boot is less than 0.5MB
31 */
32#define CONFIG_SYS_TEXT_BASE 0xfff80000
33
Jon Loeliger288693a2005-07-25 12:14:54 -050034#ifndef CONFIG_HAS_FEC
35#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
36#endif
37
wdenk0ac6f8b2004-07-09 23:27:13 +000038#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000039#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala0151cba2008-10-21 11:33:58 -050040#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020041#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000042#define CONFIG_ENV_OVERWRITE
Kumar Gala7232a272008-01-16 01:32:06 -060043#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk42d1f032003-10-15 23:53:47 +000044
wdenk0ac6f8b2004-07-09 23:27:13 +000045/*
46 * sysclk for MPC85xx
47 *
48 * Two valid values are:
49 * 33000000
50 * 66000000
51 *
52 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000053 * is likely the desired value here, so that is now the default.
54 * The board, however, can run at 66MHz. In any event, this value
55 * must match the settings of some switches. Details can be found
56 * in the README.mpc85xxads.
Matthew McClintock34c3c0e2006-06-28 10:47:03 -050057 *
58 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
59 * 33MHz to accommodate, based on a PCI pin.
60 * Note that PCI-X won't work at 33MHz.
wdenk0ac6f8b2004-07-09 23:27:13 +000061 */
62
wdenk9aea9532004-08-01 23:02:45 +000063#ifndef CONFIG_SYS_CLK_FREQ
Matthew McClintock34c3c0e2006-06-28 10:47:03 -050064#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000065#endif
66
wdenk9aea9532004-08-01 23:02:45 +000067
wdenk0ac6f8b2004-07-09 23:27:13 +000068/*
69 * These can be toggled for performance analysis, otherwise use default.
70 */
71#define CONFIG_L2_CACHE /* toggle L2 cache */
72#define CONFIG_BTB /* toggle branch predition */
wdenk42d1f032003-10-15 23:53:47 +000073
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
75#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk42d1f032003-10-15 23:53:47 +000076
Timur Tabie46fedf2011-08-04 18:03:41 -050077#define CONFIG_SYS_CCSRBAR 0xe0000000
78#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk42d1f032003-10-15 23:53:47 +000079
Kumar Gala9617c8d2008-06-06 13:12:18 -050080/* DDR Setup */
81#define CONFIG_FSL_DDR1
82#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
83#define CONFIG_DDR_SPD
84#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk9aea9532004-08-01 23:02:45 +000085
Kumar Gala9617c8d2008-06-06 13:12:18 -050086#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
87
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
89#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +000090
Kumar Gala9617c8d2008-06-06 13:12:18 -050091#define CONFIG_NUM_DDR_CONTROLLERS 1
92#define CONFIG_DIMM_SLOTS_PER_CTLR 1
93#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk9aea9532004-08-01 23:02:45 +000094
Kumar Gala9617c8d2008-06-06 13:12:18 -050095/* I2C addresses of SPD EEPROMs */
96#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk9aea9532004-08-01 23:02:45 +000097
Kumar Gala9617c8d2008-06-06 13:12:18 -050098/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
100#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
101#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
102#define CONFIG_SYS_DDR_TIMING_1 0x37344321
103#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
104#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
105#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
106#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk42d1f032003-10-15 23:53:47 +0000107
wdenk0ac6f8b2004-07-09 23:27:13 +0000108/*
109 * SDRAM on the Local Bus
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
112#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
115#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
118#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
119#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
120#undef CONFIG_SYS_FLASH_CHECKSUM
121#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
122#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000123
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200124#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk0ac6f8b2004-07-09 23:27:13 +0000125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
127#define CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000128#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#undef CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000130#endif
131
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200132#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_FLASH_CFI
134#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk42d1f032003-10-15 23:53:47 +0000135
wdenk42d1f032003-10-15 23:53:47 +0000136#undef CONFIG_CLOCKS_IN_MHZ
137
wdenk0ac6f8b2004-07-09 23:27:13 +0000138
139/*
140 * Local Bus Definitions
141 */
142
143/*
144 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk0ac6f8b2004-07-09 23:27:13 +0000146 *
147 * For BR2, need:
148 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
149 * port-size = 32-bits = BR2[19:20] = 11
150 * no parity checking = BR2[21:22] = 00
151 * SDRAM for MSEL = BR2[24:26] = 011
152 * Valid = BR[31] = 1
153 *
154 * 0 4 8 12 16 20 24 28
155 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
156 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk0ac6f8b2004-07-09 23:27:13 +0000158 * FIXME: the top 17 bits of BR2.
159 */
160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk0ac6f8b2004-07-09 23:27:13 +0000162
163/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk0ac6f8b2004-07-09 23:27:13 +0000165 *
166 * For OR2, need:
167 * 64MB mask for AM, OR2[0:7] = 1111 1100
168 * XAM, OR2[17:18] = 11
169 * 9 columns OR2[19-21] = 010
170 * 13 rows OR2[23-25] = 100
171 * EAD set for extra time OR[31] = 1
172 *
173 * 0 4 8 12 16 20 24 28
174 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
175 */
176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
180#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
181#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
182#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000183
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500184#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
185 | LSDMR_RFCR5 \
186 | LSDMR_PRETOACT3 \
187 | LSDMR_ACTTORW3 \
188 | LSDMR_BL8 \
189 | LSDMR_WRC2 \
190 | LSDMR_CL3 \
191 | LSDMR_RFEN \
wdenk0ac6f8b2004-07-09 23:27:13 +0000192 )
193
194/*
195 * SDRAM Controller configuration sequence.
196 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500197#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
198#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
199#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
200#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
201#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000202
wdenk42d1f032003-10-15 23:53:47 +0000203
wdenk9aea9532004-08-01 23:02:45 +0000204/*
205 * 32KB, 8-bit wide for ADS config reg
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_BR4_PRELIM 0xf8000801
208#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
209#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk42d1f032003-10-15 23:53:47 +0000210
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_INIT_RAM_LOCK 1
212#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200213#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000214
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200215#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
219#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000220
221/* Serial Port */
222#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_NS16550
224#define CONFIG_SYS_NS16550_SERIAL
225#define CONFIG_SYS_NS16550_REG_SIZE 1
226#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk42d1f032003-10-15 23:53:47 +0000227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk42d1f032003-10-15 23:53:47 +0000229 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
232#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk42d1f032003-10-15 23:53:47 +0000233
234/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_HUSH_PARSER
236#ifdef CONFIG_SYS_HUSH_PARSER
wdenk42d1f032003-10-15 23:53:47 +0000237#endif
238
Matthew McClintock0e163872006-06-28 10:43:36 -0500239/* pass open firmware flat tree */
Kumar Gala0fd5ec62007-11-28 22:54:27 -0600240#define CONFIG_OF_LIBFDT 1
241#define CONFIG_OF_BOARD_SETUP 1
242#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500243
Jon Loeliger20476722006-10-20 15:50:15 -0500244/*
245 * I2C
246 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200247#define CONFIG_SYS_I2C
248#define CONFIG_SYS_I2C_FSL
249#define CONFIG_SYS_FSL_I2C_SPEED 400000
250#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
251#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
252#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk42d1f032003-10-15 23:53:47 +0000253
wdenk0ac6f8b2004-07-09 23:27:13 +0000254/* RapidIO MMU */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600255#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala10795f42008-12-02 16:08:36 -0600256#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600257#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000259
260/*
261 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300262 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk0ac6f8b2004-07-09 23:27:13 +0000263 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600264#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600265#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600266#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600268#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600269#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
271#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000272
wdenk42d1f032003-10-15 23:53:47 +0000273#if defined(CONFIG_PCI)
wdenk0ac6f8b2004-07-09 23:27:13 +0000274
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200275#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk0ac6f8b2004-07-09 23:27:13 +0000276
wdenk42d1f032003-10-15 23:53:47 +0000277#undef CONFIG_EEPRO100
wdenk0ac6f8b2004-07-09 23:27:13 +0000278#undef CONFIG_TULIP
279
280#if !defined(CONFIG_PCI_PNP)
281 #define PCI_ENET0_IOADDR 0xe0000000
282 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200283 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000284#endif
285
wdenk0ac6f8b2004-07-09 23:27:13 +0000286#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk0ac6f8b2004-07-09 23:27:13 +0000288
289#endif /* CONFIG_PCI */
290
291
292#if defined(CONFIG_TSEC_ENET)
293
wdenk0ac6f8b2004-07-09 23:27:13 +0000294#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500295#define CONFIG_TSEC1 1
296#define CONFIG_TSEC1_NAME "TSEC0"
297#define CONFIG_TSEC2 1
298#define CONFIG_TSEC2_NAME "TSEC1"
wdenk0ac6f8b2004-07-09 23:27:13 +0000299#define TSEC1_PHY_ADDR 0
300#define TSEC2_PHY_ADDR 1
wdenk0ac6f8b2004-07-09 23:27:13 +0000301#define TSEC1_PHYIDX 0
302#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500303#define TSEC1_FLAGS TSEC_GIGABIT
304#define TSEC2_FLAGS TSEC_GIGABIT
wdenk9aea9532004-08-01 23:02:45 +0000305
Jon Loeliger288693a2005-07-25 12:14:54 -0500306
307#if CONFIG_HAS_FEC
wdenk9aea9532004-08-01 23:02:45 +0000308#define CONFIG_MPC85XX_FEC 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500309#define CONFIG_MPC85XX_FEC_NAME "FEC"
wdenk9aea9532004-08-01 23:02:45 +0000310#define FEC_PHY_ADDR 3
wdenk0ac6f8b2004-07-09 23:27:13 +0000311#define FEC_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500312#define FEC_FLAGS 0
Jon Loeliger288693a2005-07-25 12:14:54 -0500313#endif
wdenk9aea9532004-08-01 23:02:45 +0000314
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500315/* Options are: TSEC[0-1], FEC */
316#define CONFIG_ETHPRIME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000317
318#endif /* CONFIG_TSEC_ENET */
319
320
321/*
322 * Environment
323 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200325 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200327 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
328 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000329#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200331 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200333 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000334#endif
335
wdenk0ac6f8b2004-07-09 23:27:13 +0000336#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000338
Jon Loeliger2835e512007-06-13 13:22:08 -0500339
340/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500341 * BOOTP options
342 */
343#define CONFIG_BOOTP_BOOTFILESIZE
344#define CONFIG_BOOTP_BOOTPATH
345#define CONFIG_BOOTP_GATEWAY
346#define CONFIG_BOOTP_HOSTNAME
347
348
349/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500350 * Command line configuration.
351 */
352#include <config_cmd_default.h>
353
354#define CONFIG_CMD_PING
355#define CONFIG_CMD_I2C
Kumar Gala82ac8c92007-12-07 12:04:30 -0600356#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500357#define CONFIG_CMD_IRQ
358#define CONFIG_CMD_SETEXPR
Jon Loeliger2835e512007-06-13 13:22:08 -0500359
360#if defined(CONFIG_PCI)
361 #define CONFIG_CMD_PCI
wdenk42d1f032003-10-15 23:53:47 +0000362#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000363
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500365 #undef CONFIG_CMD_SAVEENV
Jon Loeliger2835e512007-06-13 13:22:08 -0500366 #undef CONFIG_CMD_LOADS
367#endif
368
wdenk42d1f032003-10-15 23:53:47 +0000369
wdenk0ac6f8b2004-07-09 23:27:13 +0000370#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000371
372/*
373 * Miscellaneous configurable options
374 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500376#define CONFIG_CMDLINE_EDITING /* Command-line editing */
377#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
wdenk0ac6f8b2004-07-09 23:27:13 +0000379
Jon Loeliger2835e512007-06-13 13:22:08 -0500380#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000382#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000384#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
387#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
388#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000389
390/*
391 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500392 * have to be in the first 64 MB of memory, since this is
wdenk42d1f032003-10-15 23:53:47 +0000393 * the maximum mapped by the Linux kernel during initialization.
394 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500395#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
396#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk42d1f032003-10-15 23:53:47 +0000397
Jon Loeliger2835e512007-06-13 13:22:08 -0500398#if defined(CONFIG_CMD_KGDB)
wdenk42d1f032003-10-15 23:53:47 +0000399#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
400#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
401#endif
402
wdenk9aea9532004-08-01 23:02:45 +0000403
404/*
405 * Environment Configuration
406 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000407
408/* The mac addresses for all ethernet interface */
wdenk42d1f032003-10-15 23:53:47 +0000409#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500410#define CONFIG_HAS_ETH0
wdenk0ac6f8b2004-07-09 23:27:13 +0000411#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000412#define CONFIG_HAS_ETH1
wdenk0ac6f8b2004-07-09 23:27:13 +0000413#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000414#define CONFIG_HAS_ETH2
wdenk0ac6f8b2004-07-09 23:27:13 +0000415#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
wdenk42d1f032003-10-15 23:53:47 +0000416#endif
417
wdenk0ac6f8b2004-07-09 23:27:13 +0000418#define CONFIG_IPADDR 192.168.1.253
419
420#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000421#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000422#define CONFIG_BOOTFILE "your.uImage"
wdenk0ac6f8b2004-07-09 23:27:13 +0000423
424#define CONFIG_SERVERIP 192.168.1.1
425#define CONFIG_GATEWAYIP 192.168.1.1
426#define CONFIG_NETMASK 255.255.255.0
427
428#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
429
430#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
431#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
432
433#define CONFIG_BAUDRATE 115200
434
wdenk9aea9532004-08-01 23:02:45 +0000435#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk0ac6f8b2004-07-09 23:27:13 +0000436 "netdev=eth0\0" \
437 "consoledev=ttyS0\0" \
Andy Flemingd3ec0d92007-05-10 17:50:01 -0500438 "ramdiskaddr=1000000\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500439 "ramdiskfile=your.ramdisk.u-boot\0" \
440 "fdtaddr=400000\0" \
441 "fdtfile=your.fdt.dtb\0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000442
wdenk9aea9532004-08-01 23:02:45 +0000443#define CONFIG_NFSBOOTCOMMAND \
wdenk0ac6f8b2004-07-09 23:27:13 +0000444 "setenv bootargs root=/dev/nfs rw " \
445 "nfsroot=$serverip:$rootpath " \
446 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
447 "console=$consoledev,$baudrate $othbootargs;" \
448 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500449 "tftp $fdtaddr $fdtfile;" \
450 "bootm $loadaddr - $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000451
452#define CONFIG_RAMBOOTCOMMAND \
453 "setenv bootargs root=/dev/ram rw " \
454 "console=$consoledev,$baudrate $othbootargs;" \
455 "tftp $ramdiskaddr $ramdiskfile;" \
456 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500457 "tftp $fdtaddr $fdtfile;" \
Andy Flemingd3ec0d92007-05-10 17:50:01 -0500458 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000459
460#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000461
462#endif /* __CONFIG_H */