blob: e24c5974530875b59489a8a6ec00823d3ac9abef [file] [log] [blame]
wdenk03f5c552004-10-10 21:21:55 +00001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk03f5c552004-10-10 21:21:55 +00003 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
wdenk03f5c552004-10-10 21:21:55 +00005 */
6
7/*
8 * mpc8541cds board configuration file
9 *
10 * Please refer to doc/README.mpc85xxcds for more info.
11 *
12 */
wdenk03f5c552004-10-10 21:21:55 +000013#ifndef __CONFIG_H
14#define __CONFIG_H
15
16/* High Level Configuration Options */
17#define CONFIG_BOOKE 1 /* BOOKE */
18#define CONFIG_E500 1 /* BOOKE e500 family */
19#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050020#define CONFIG_CPM2 1 /* has CPM2 */
wdenk03f5c552004-10-10 21:21:55 +000021#define CONFIG_MPC8541 1 /* MPC8541 specific */
22#define CONFIG_MPC8541CDS 1 /* MPC8541CDS board specific */
23
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0xfff80000
25
wdenk03f5c552004-10-10 21:21:55 +000026#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000027#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala0151cba2008-10-21 11:33:58 -050028#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020029#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk03f5c552004-10-10 21:21:55 +000030#define CONFIG_ENV_OVERWRITE
Jon Loeligerd9b94f22005-07-25 14:05:07 -050031
Kumar Gala2cfaa1a2008-01-16 01:45:10 -060032#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk03f5c552004-10-10 21:21:55 +000033
Jon Loeliger25eedb22008-03-19 15:02:07 -050034#define CONFIG_FSL_VIA
Jon Loeliger25eedb22008-03-19 15:02:07 -050035
wdenk03f5c552004-10-10 21:21:55 +000036#ifndef __ASSEMBLY__
37extern unsigned long get_clock_freq(void);
38#endif
39#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
40
41/*
42 * These can be toggled for performance analysis, otherwise use default.
43 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020044#define CONFIG_L2_CACHE /* toggle L2 cache */
wdenk03f5c552004-10-10 21:21:55 +000045#define CONFIG_BTB /* toggle branch predition */
wdenk03f5c552004-10-10 21:21:55 +000046
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
48#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk03f5c552004-10-10 21:21:55 +000049
Timur Tabie46fedf2011-08-04 18:03:41 -050050#define CONFIG_SYS_CCSRBAR 0xe0000000
51#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk03f5c552004-10-10 21:21:55 +000052
Jon Loeligeraa11d852008-03-17 15:48:18 -050053/* DDR Setup */
54#define CONFIG_FSL_DDR1
55#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
56#define CONFIG_DDR_SPD
57#undef CONFIG_FSL_DDR_INTERACTIVE
58
59#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
60
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
62#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk03f5c552004-10-10 21:21:55 +000063
Jon Loeligeraa11d852008-03-17 15:48:18 -050064#define CONFIG_NUM_DDR_CONTROLLERS 1
65#define CONFIG_DIMM_SLOTS_PER_CTLR 1
66#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
67
68/* I2C addresses of SPD EEPROMs */
69#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk03f5c552004-10-10 21:21:55 +000070
71/*
72 * Make sure required options are set
73 */
74#ifndef CONFIG_SPD_EEPROM
75#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
76#endif
77
Jon Loeliger7202d432005-07-25 11:13:26 -050078#undef CONFIG_CLOCKS_IN_MHZ
79
wdenk03f5c552004-10-10 21:21:55 +000080/*
Jon Loeliger7202d432005-07-25 11:13:26 -050081 * Local Bus Definitions
wdenk03f5c552004-10-10 21:21:55 +000082 */
Jon Loeliger7202d432005-07-25 11:13:26 -050083
84/*
85 * FLASH on the Local Bus
86 * Two banks, 8M each, using the CFI driver.
87 * Boot from BR0/OR0 bank at 0xff00_0000
88 * Alternate BR1/OR1 bank at 0xff80_0000
89 *
90 * BR0, BR1:
91 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
92 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
93 * Port Size = 16 bits = BRx[19:20] = 10
94 * Use GPCM = BRx[24:26] = 000
95 * Valid = BRx[31] = 1
96 *
97 * 0 4 8 12 16 20 24 28
98 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
99 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
100 *
101 * OR0, OR1:
102 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
103 * Reserved ORx[17:18] = 11, confusion here?
104 * CSNT = ORx[20] = 1
105 * ACS = half cycle delay = ORx[21:22] = 11
106 * SCY = 6 = ORx[24:27] = 0110
107 * TRLX = use relaxed timing = ORx[29] = 1
108 * EAD = use external address latch delay = OR[31] = 1
109 *
110 * 0 4 8 12 16 20 24 28
111 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
112 */
113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
wdenk03f5c552004-10-10 21:21:55 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_BR0_PRELIM 0xff801001
117#define CONFIG_SYS_BR1_PRELIM 0xff001001
wdenk03f5c552004-10-10 21:21:55 +0000118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_OR0_PRELIM 0xff806e65
120#define CONFIG_SYS_OR1_PRELIM 0xff806e65
wdenk03f5c552004-10-10 21:21:55 +0000121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
123#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
124#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
125#undef CONFIG_SYS_FLASH_CHECKSUM
126#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
127#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk03f5c552004-10-10 21:21:55 +0000128
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200129#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk03f5c552004-10-10 21:21:55 +0000130
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200131#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_FLASH_CFI
133#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk03f5c552004-10-10 21:21:55 +0000134
wdenk03f5c552004-10-10 21:21:55 +0000135
136/*
Jon Loeliger7202d432005-07-25 11:13:26 -0500137 * SDRAM on the Local Bus
wdenk03f5c552004-10-10 21:21:55 +0000138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
140#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk03f5c552004-10-10 21:21:55 +0000141
142/*
143 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk03f5c552004-10-10 21:21:55 +0000145 *
146 * For BR2, need:
147 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
148 * port-size = 32-bits = BR2[19:20] = 11
149 * no parity checking = BR2[21:22] = 00
150 * SDRAM for MSEL = BR2[24:26] = 011
151 * Valid = BR[31] = 1
152 *
153 * 0 4 8 12 16 20 24 28
154 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
155 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk03f5c552004-10-10 21:21:55 +0000157 * FIXME: the top 17 bits of BR2.
158 */
159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk03f5c552004-10-10 21:21:55 +0000161
162/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk03f5c552004-10-10 21:21:55 +0000164 *
165 * For OR2, need:
166 * 64MB mask for AM, OR2[0:7] = 1111 1100
167 * XAM, OR2[17:18] = 11
168 * 9 columns OR2[19-21] = 010
169 * 13 rows OR2[23-25] = 100
170 * EAD set for extra time OR[31] = 1
171 *
172 * 0 4 8 12 16 20 24 28
173 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
174 */
175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk03f5c552004-10-10 21:21:55 +0000177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
179#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
180#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
181#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
wdenk03f5c552004-10-10 21:21:55 +0000182
183/*
wdenk03f5c552004-10-10 21:21:55 +0000184 * Common settings for all Local Bus SDRAM commands.
185 * At run time, either BSMA1516 (for CPU 1.1)
186 * or BSMA1617 (for CPU 1.0) (old)
187 * is OR'ed in too.
188 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500189#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
190 | LSDMR_PRETOACT7 \
191 | LSDMR_ACTTORW7 \
192 | LSDMR_BL8 \
193 | LSDMR_WRC4 \
194 | LSDMR_CL3 \
195 | LSDMR_RFEN \
wdenk03f5c552004-10-10 21:21:55 +0000196 )
197
198/*
199 * The CADMUS registers are connected to CS3 on CDS.
200 * The new memory map places CADMUS at 0xf8000000.
201 *
202 * For BR3, need:
203 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
204 * port-size = 8-bits = BR[19:20] = 01
205 * no parity checking = BR[21:22] = 00
206 * GPMC for MSEL = BR[24:26] = 000
207 * Valid = BR[31] = 1
208 *
209 * 0 4 8 12 16 20 24 28
210 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
211 *
212 * For OR3, need:
213 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
214 * disable buffer ctrl OR[19] = 0
215 * CSNT OR[20] = 1
216 * ACS OR[21:22] = 11
217 * XACS OR[23] = 1
218 * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
219 * SETA OR[28] = 0
220 * TRLX OR[29] = 1
221 * EHTR OR[30] = 1
222 * EAD extra time OR[31] = 1
223 *
224 * 0 4 8 12 16 20 24 28
225 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
226 */
227
Jon Loeliger25eedb22008-03-19 15:02:07 -0500228#define CONFIG_FSL_CADMUS
229
wdenk03f5c552004-10-10 21:21:55 +0000230#define CADMUS_BASE_ADDR 0xf8000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_BR3_PRELIM 0xf8000801
232#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
wdenk03f5c552004-10-10 21:21:55 +0000233
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_INIT_RAM_LOCK 1
235#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200236#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk03f5c552004-10-10 21:21:55 +0000237
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200238#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk03f5c552004-10-10 21:21:55 +0000240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
242#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk03f5c552004-10-10 21:21:55 +0000243
244/* Serial Port */
245#define CONFIG_CONS_INDEX 2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_NS16550
247#define CONFIG_SYS_NS16550_SERIAL
248#define CONFIG_SYS_NS16550_REG_SIZE 1
249#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk03f5c552004-10-10 21:21:55 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk03f5c552004-10-10 21:21:55 +0000252 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
255#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk03f5c552004-10-10 21:21:55 +0000256
257/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_HUSH_PARSER
259#ifdef CONFIG_SYS_HUSH_PARSER
wdenk03f5c552004-10-10 21:21:55 +0000260#endif
261
Matthew McClintock0e163872006-06-28 10:43:36 -0500262/* pass open firmware flat tree */
Kumar Galab90d2542007-11-29 00:11:44 -0600263#define CONFIG_OF_LIBFDT 1
264#define CONFIG_OF_BOARD_SETUP 1
265#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500266
Jon Loeliger20476722006-10-20 15:50:15 -0500267/*
268 * I2C
269 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200270#define CONFIG_SYS_I2C
271#define CONFIG_SYS_I2C_FSL
272#define CONFIG_SYS_FSL_I2C_SPEED 400000
273#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
274#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
275#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk03f5c552004-10-10 21:21:55 +0000276
Timur Tabie8d18542008-07-18 16:52:23 +0200277/* EEPROM */
278#define CONFIG_ID_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_I2C_EEPROM_CCID
280#define CONFIG_SYS_ID_EEPROM
281#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
282#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Timur Tabie8d18542008-07-18 16:52:23 +0200283
wdenk03f5c552004-10-10 21:21:55 +0000284/*
285 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300286 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk03f5c552004-10-10 21:21:55 +0000287 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600288#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600289#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600290#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600292#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600293#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
295#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000296
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600297#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
Kumar Gala10795f42008-12-02 16:08:36 -0600298#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600299#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600301#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600302#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
304#define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */
wdenk03f5c552004-10-10 21:21:55 +0000305
Randy Vinson7f3f2bd2007-02-27 19:42:22 -0700306#ifdef CONFIG_LEGACY
307#define BRIDGE_ID 17
308#define VIA_ID 2
309#else
310#define BRIDGE_ID 28
311#define VIA_ID 4
312#endif
wdenk03f5c552004-10-10 21:21:55 +0000313
314#if defined(CONFIG_PCI)
315
Matthew McClintockbf1dfff2006-06-28 10:46:13 -0500316#define CONFIG_MPC85XX_PCI2
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200317#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk03f5c552004-10-10 21:21:55 +0000318
319#undef CONFIG_EEPRO100
320#undef CONFIG_TULIP
321
wdenk03f5c552004-10-10 21:21:55 +0000322#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk03f5c552004-10-10 21:21:55 +0000324
325#endif /* CONFIG_PCI */
326
327
328#if defined(CONFIG_TSEC_ENET)
329
wdenk03f5c552004-10-10 21:21:55 +0000330#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500331#define CONFIG_TSEC1 1
332#define CONFIG_TSEC1_NAME "TSEC0"
333#define CONFIG_TSEC2 1
334#define CONFIG_TSEC2_NAME "TSEC1"
wdenk03f5c552004-10-10 21:21:55 +0000335#define TSEC1_PHY_ADDR 0
336#define TSEC2_PHY_ADDR 1
wdenk03f5c552004-10-10 21:21:55 +0000337#define TSEC1_PHYIDX 0
338#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500339#define TSEC1_FLAGS TSEC_GIGABIT
340#define TSEC2_FLAGS TSEC_GIGABIT
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500341
342/* Options are: TSEC[0-1] */
343#define CONFIG_ETHPRIME "TSEC0"
wdenk03f5c552004-10-10 21:21:55 +0000344
345#endif /* CONFIG_TSEC_ENET */
346
wdenk03f5c552004-10-10 21:21:55 +0000347/*
348 * Environment
349 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200350#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200352#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
353#define CONFIG_ENV_SIZE 0x2000
wdenk03f5c552004-10-10 21:21:55 +0000354
355#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk03f5c552004-10-10 21:21:55 +0000357
Jon Loeliger2835e512007-06-13 13:22:08 -0500358/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500359 * BOOTP options
360 */
361#define CONFIG_BOOTP_BOOTFILESIZE
362#define CONFIG_BOOTP_BOOTPATH
363#define CONFIG_BOOTP_GATEWAY
364#define CONFIG_BOOTP_HOSTNAME
365
366
367/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500368 * Command line configuration.
369 */
370#include <config_cmd_default.h>
371
372#define CONFIG_CMD_PING
373#define CONFIG_CMD_I2C
374#define CONFIG_CMD_MII
Kumar Gala82ac8c92007-12-07 12:04:30 -0600375#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500376#define CONFIG_CMD_IRQ
377#define CONFIG_CMD_SETEXPR
Becky Bruce199e2622010-06-17 11:37:25 -0500378#define CONFIG_CMD_REGINFO
Jon Loeliger2835e512007-06-13 13:22:08 -0500379
wdenk03f5c552004-10-10 21:21:55 +0000380#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500381 #define CONFIG_CMD_PCI
wdenk03f5c552004-10-10 21:21:55 +0000382#endif
Jon Loeliger2835e512007-06-13 13:22:08 -0500383
wdenk03f5c552004-10-10 21:21:55 +0000384
385#undef CONFIG_WATCHDOG /* watchdog disabled */
386
387/*
388 * Miscellaneous configurable options
389 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500391#define CONFIG_CMDLINE_EDITING /* Command-line editing */
392#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeliger2835e512007-06-13 13:22:08 -0500394#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000396#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000398#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
400#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
401#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk03f5c552004-10-10 21:21:55 +0000402
403/*
404 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500405 * have to be in the first 64 MB of memory, since this is
wdenk03f5c552004-10-10 21:21:55 +0000406 * the maximum mapped by the Linux kernel during initialization.
407 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500408#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
409#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk03f5c552004-10-10 21:21:55 +0000410
Jon Loeliger2835e512007-06-13 13:22:08 -0500411#if defined(CONFIG_CMD_KGDB)
wdenk03f5c552004-10-10 21:21:55 +0000412#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
413#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
414#endif
415
wdenk03f5c552004-10-10 21:21:55 +0000416/*
417 * Environment Configuration
418 */
419
420/* The mac addresses for all ethernet interface */
421#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500422#define CONFIG_HAS_ETH0
wdenk03f5c552004-10-10 21:21:55 +0000423#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000424#define CONFIG_HAS_ETH1
wdenk03f5c552004-10-10 21:21:55 +0000425#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000426#define CONFIG_HAS_ETH2
wdenk03f5c552004-10-10 21:21:55 +0000427#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
428#endif
429
430#define CONFIG_IPADDR 192.168.1.253
431
432#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000433#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000434#define CONFIG_BOOTFILE "your.uImage"
wdenk03f5c552004-10-10 21:21:55 +0000435
436#define CONFIG_SERVERIP 192.168.1.1
437#define CONFIG_GATEWAYIP 192.168.1.1
438#define CONFIG_NETMASK 255.255.255.0
439
440#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
441
442#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
443#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
444
445#define CONFIG_BAUDRATE 115200
446
447#define CONFIG_EXTRA_ENV_SETTINGS \
448 "netdev=eth0\0" \
449 "consoledev=ttyS1\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500450 "ramdiskaddr=600000\0" \
451 "ramdiskfile=your.ramdisk.u-boot\0" \
452 "fdtaddr=400000\0" \
453 "fdtfile=your.fdt.dtb\0"
wdenk03f5c552004-10-10 21:21:55 +0000454
455#define CONFIG_NFSBOOTCOMMAND \
456 "setenv bootargs root=/dev/nfs rw " \
457 "nfsroot=$serverip:$rootpath " \
458 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
459 "console=$consoledev,$baudrate $othbootargs;" \
460 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500461 "tftp $fdtaddr $fdtfile;" \
462 "bootm $loadaddr - $fdtaddr"
wdenk03f5c552004-10-10 21:21:55 +0000463
464#define CONFIG_RAMBOOTCOMMAND \
465 "setenv bootargs root=/dev/ram rw " \
466 "console=$consoledev,$baudrate $othbootargs;" \
467 "tftp $ramdiskaddr $ramdiskfile;" \
468 "tftp $loadaddr $bootfile;" \
469 "bootm $loadaddr $ramdiskaddr"
470
471#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
472
wdenk03f5c552004-10-10 21:21:55 +0000473#endif /* __CONFIG_H */