blob: efdf1aa670dab2dd6f7e8de8fa76f6eb6fb58125 [file] [log] [blame]
Andre Schwarzc005b932008-06-10 09:13:16 +02001/*
2 * Copyright (C) Matrix Vision GmbH 2008
3 *
4 * Matrix Vision mvBlueLYNX-M7 configuration file
5 * based on Freescale's MPC8349ITX.
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Andre Schwarzc005b932008-06-10 09:13:16 +02008 */
9
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Andre Schwarz5ed546f2008-07-02 18:54:08 +020014#include <version.h>
Andre Schwarzc005b932008-06-10 09:13:16 +020015
16/*
17 * High Level Configuration Options
18 */
19#define CONFIG_E300 1
Peter Tyser0f898602009-05-22 17:23:24 -050020#define CONFIG_MPC83xx 1
Peter Tyser2c7920a2009-05-22 17:23:25 -050021#define CONFIG_MPC834x 1
Andre Schwarzc005b932008-06-10 09:13:16 +020022#define CONFIG_MPC8343 1
23
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0xFFF00000
25
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_IMMR 0xE0000000
Andre Schwarzc005b932008-06-10 09:13:16 +020027
28#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000029#define CONFIG_PCI_INDIRECT_BRIDGE
Andre Schwarzc005b932008-06-10 09:13:16 +020030#define CONFIG_PCI_SKIP_HOST_BRIDGE
Andre Schwarzc005b932008-06-10 09:13:16 +020031#define CONFIG_TSEC_ENET
32#define CONFIG_MPC8XXX_SPI
33#define CONFIG_HARD_SPI
34#define MVBLM7_MMC_CS 0x04000000
André Schwarz28887d82009-08-27 14:48:35 +020035#define CONFIG_MISC_INIT_R
Andre Schwarzc005b932008-06-10 09:13:16 +020036
37/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +020038#define CONFIG_SYS_I2C
39#define CONFIG_SYS_I2C_FSL
40#define CONFIG_SYS_FSL_I2C_SPEED 100000
41#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
42#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
43#define CONFIG_SYS_FSL_I2C2_SPEED 100000
44#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
45#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Andre Schwarzc005b932008-06-10 09:13:16 +020046
47/*
48 * DDR Setup
49 */
André Schwarz28887d82009-08-27 14:48:35 +020050#undef CONFIG_SPD_EEPROM
51
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_DDR_BASE 0x00000000
53#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
54#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
55#define CONFIG_SYS_83XX_DDR_USES_CS0 1
56#define CONFIG_SYS_MEMTEST_START (60<<20)
57#define CONFIG_SYS_MEMTEST_END (70<<20)
André Schwarz28887d82009-08-27 14:48:35 +020058#define CONFIG_VERY_BIG_RAM
Andre Schwarzc005b932008-06-10 09:13:16 +020059
Joe Hershberger2fef4022011-10-11 23:57:29 -050060#define CONFIG_SYS_DDRCDR (DDRCDR_PZ_HIZ \
61 | DDRCDR_NZ_HIZ \
62 | DDRCDR_Q_DRN)
63 /* 0x22000001 */
André Schwarz28887d82009-08-27 14:48:35 +020064#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Andre Schwarzc005b932008-06-10 09:13:16 +020065
André Schwarz28887d82009-08-27 14:48:35 +020066#define CONFIG_SYS_DDR_SIZE 512
Andre Schwarzc005b932008-06-10 09:13:16 +020067
André Schwarz28887d82009-08-27 14:48:35 +020068#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
Andre Schwarzc005b932008-06-10 09:13:16 +020069
André Schwarz28887d82009-08-27 14:48:35 +020070#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
Andre Schwarzc005b932008-06-10 09:13:16 +020071
André Schwarz28887d82009-08-27 14:48:35 +020072#define CONFIG_SYS_DDR_TIMING_0 0x00260802
73#define CONFIG_SYS_DDR_TIMING_1 0x3837c322
74#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6
75#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Andre Schwarzc005b932008-06-10 09:13:16 +020076
André Schwarz28887d82009-08-27 14:48:35 +020077#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
André Schwarz28887d82009-08-27 14:48:35 +020079#define CONFIG_SYS_DDR_INTERVAL 0x02000100
Andre Schwarzc005b932008-06-10 09:13:16 +020080
André Schwarz28887d82009-08-27 14:48:35 +020081#define CONFIG_SYS_DDR_MODE 0x04040242
82#define CONFIG_SYS_DDR_MODE2 0x00800000
Andre Schwarzc005b932008-06-10 09:13:16 +020083
84/* Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020086#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Andre Schwarzc005b932008-06-10 09:13:16 +020088
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_FLASH_BASE 0xFF800000
90#define CONFIG_SYS_FLASH_SIZE 8
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_FLASH_EMPTY_INFO
92#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
93#define CONFIG_SYS_FLASH_WRITE_TOUT 500
94#define CONFIG_SYS_MAX_FLASH_BANKS 1
95#define CONFIG_SYS_MAX_FLASH_SECT 256
Andre Schwarzc005b932008-06-10 09:13:16 +020096
Joe Hershberger7d6a0982011-10-11 23:57:30 -050097#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
98 | BR_PS_16 \
99 | BR_MS_GPCM \
100 | BR_V)
101#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500102 | OR_UPM_XAM \
103 | OR_GPCM_CSNT \
104 | OR_GPCM_ACS_DIV2 \
105 | OR_GPCM_XACS \
106 | OR_GPCM_SCY_15 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500107 | OR_GPCM_TRLX_SET \
108 | OR_GPCM_EHTR_SET \
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500109 | OR_GPCM_EAD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500111#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
Andre Schwarzc005b932008-06-10 09:13:16 +0200112
113/*
114 * U-Boot memory configuration
115 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200116#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#undef CONFIG_SYS_RAMBOOT
Andre Schwarzc005b932008-06-10 09:13:16 +0200118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_INIT_RAM_LOCK
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500120#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
121#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Andre Schwarzc005b932008-06-10 09:13:16 +0200122
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500123#define CONFIG_SYS_GBL_DATA_OFFSET \
124 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Andre Schwarzc005b932008-06-10 09:13:16 +0200126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
128#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
129#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
Andre Schwarzc005b932008-06-10 09:13:16 +0200130
131/*
132 * Local Bus LCRR and LBCR regs
133 * LCRR: DLL bypass, Clock divider is 4
134 * External Local Bus rate is
135 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
136 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500137#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
138#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_LBC_LBCR 0x00000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200140
141/* LB sdram refresh timer, about 6us */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_LBC_LSRT 0x32000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200143/* LB refresh timer prescal, 266MHz/32*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LBC_MRTPR 0x20000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200145
146/*
147 * Serial Port
148 */
149#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_NS16550
151#define CONFIG_SYS_NS16550_SERIAL
152#define CONFIG_SYS_NS16550_REG_SIZE 1
153#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Andre Schwarzc005b932008-06-10 09:13:16 +0200154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500156 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Andre Schwarzc005b932008-06-10 09:13:16 +0200157
158#define CONFIG_CONSOLE ttyS0
159#define CONFIG_BAUDRATE 115200
160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
162#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
Andre Schwarzc005b932008-06-10 09:13:16 +0200163
164/* pass open firmware flat tree */
165#define CONFIG_OF_LIBFDT 1
166#define CONFIG_OF_BOARD_SETUP 1
167#define CONFIG_OF_STDOUT_VIA_ALIAS 1
168#define MV_DTB_NAME "mvblm7.dtb"
169
170/*
171 * PCI
172 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
174#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
175#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500176#define CONFIG_SYS_PCI1_MMIO_BASE \
177 (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
179#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
180#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
181#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
182#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200183
Andre Schwarzc005b932008-06-10 09:13:16 +0200184#define CONFIG_NET_RETRY_COUNT 3
185
Wolfgang Denk2ae18242010-10-06 09:05:45 +0200186#define CONFIG_PCI_66M
Andre Schwarzc005b932008-06-10 09:13:16 +0200187#define CONFIG_83XX_CLKIN 66666667
188#define CONFIG_PCI_PNP
189#define CONFIG_PCI_SCAN_SHOW
190
191/* TSEC */
192#define CONFIG_GMII
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_VSC8601_SKEWFIX
194#define CONFIG_SYS_VSC8601_SKEW_TX 3
195#define CONFIG_SYS_VSC8601_SKEW_RX 3
Andre Schwarzc005b932008-06-10 09:13:16 +0200196
197#define CONFIG_TSEC1
198#define CONFIG_TSEC2
199
200#define CONFIG_HAS_ETH0
201#define CONFIG_TSEC1_NAME "TSEC0"
202#define CONFIG_FEC1_PHY_NORXERR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500204#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Andre Schwarzc005b932008-06-10 09:13:16 +0200205#define TSEC1_PHY_ADDR 0x10
206#define TSEC1_PHYIDX 0
207#define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
208
209#define CONFIG_HAS_ETH1
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500210#define CONFIG_TSEC2_NAME "TSEC1"
Andre Schwarzc005b932008-06-10 09:13:16 +0200211#define CONFIG_FEC2_PHY_NORXERR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500213#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Andre Schwarzc005b932008-06-10 09:13:16 +0200214#define TSEC2_PHY_ADDR 0x11
215#define TSEC2_PHYIDX 0
216#define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED)
217
218#define CONFIG_ETHPRIME "TSEC0"
219
220#define CONFIG_BOOTP_VENDOREX
221#define CONFIG_BOOTP_SUBNETMASK
222#define CONFIG_BOOTP_GATEWAY
223#define CONFIG_BOOTP_DNS
224#define CONFIG_BOOTP_DNS2
225#define CONFIG_BOOTP_HOSTNAME
226#define CONFIG_BOOTP_BOOTFILESIZE
227#define CONFIG_BOOTP_BOOTPATH
228#define CONFIG_BOOTP_NTPSERVER
229#define CONFIG_BOOTP_RANDOM_DELAY
230#define CONFIG_BOOTP_SEND_HOSTNAME
231
232/* USB */
Andre Schwarzfd194f82010-05-03 13:22:31 +0200233#define CONFIG_SYS_USB_HOST
234#define CONFIG_USB_EHCI
235#define CONFIG_USB_EHCI_FSL
Andre Schwarzc005b932008-06-10 09:13:16 +0200236#define CONFIG_HAS_FSL_DR_USB
Andre Schwarzfd194f82010-05-03 13:22:31 +0200237#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Andre Schwarzc005b932008-06-10 09:13:16 +0200238
239/*
240 * Environment
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#undef CONFIG_SYS_FLASH_PROTECTION
Andre Schwarzc005b932008-06-10 09:13:16 +0200243#define CONFIG_ENV_OVERWRITE
244
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200245#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200246#define CONFIG_ENV_ADDR 0xFF800000
247#define CONFIG_ENV_SIZE 0x2000
248#define CONFIG_ENV_SECT_SIZE 0x2000
249#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500250#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
Andre Schwarzc005b932008-06-10 09:13:16 +0200251
Wolfgang Denke093a242008-06-28 23:34:37 +0200252#define CONFIG_LOADS_ECHO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_LOADS_BAUD_CHANGE
Andre Schwarzc005b932008-06-10 09:13:16 +0200254
255/*
256 * Command line configuration.
257 */
258#include <config_cmd_default.h>
259
260#define CONFIG_CMD_CACHE
261#define CONFIG_CMD_IRQ
262#define CONFIG_CMD_NET
263#define CONFIG_CMD_MII
264#define CONFIG_CMD_PING
265#define CONFIG_CMD_DHCP
266#define CONFIG_CMD_SDRAM
267#define CONFIG_CMD_PCI
268#define CONFIG_CMD_I2C
269#define CONFIG_CMD_FPGA
Andre Schwarzfd194f82010-05-03 13:22:31 +0200270#define CONFIG_CMD_USB
271#define CONFIG_DOS_PARTITION
Andre Schwarzc005b932008-06-10 09:13:16 +0200272
273#undef CONFIG_WATCHDOG
274
275/*
276 * Miscellaneous configurable options
277 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_LONGHELP
Andre Schwarzc005b932008-06-10 09:13:16 +0200279#define CONFIG_CMDLINE_EDITING
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500280#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_HUSH_PARSER
Andre Schwarzc005b932008-06-10 09:13:16 +0200282
283/* default load address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_LOAD_ADDR 0x2000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200285/* default location for tftp and bootm */
286#define CONFIG_LOADADDR 0x200000
287
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_PROMPT "mvBL-M7> "
289#define CONFIG_SYS_CBSIZE 256
Andre Schwarzc005b932008-06-10 09:13:16 +0200290
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500291#define CONFIG_SYS_PBSIZE \
292 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_MAXARGS 16
294#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Andre Schwarzc005b932008-06-10 09:13:16 +0200295
296/*
297 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700298 * have to be in the first 256 MB of memory, since this is
Andre Schwarzc005b932008-06-10 09:13:16 +0200299 * the maximum mapped by the Linux kernel during initialization.
300 */
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500301 /* Initial Memory map for Linux*/
302#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Andre Schwarzc005b932008-06-10 09:13:16 +0200303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_HRCW_LOW 0x0
305#define CONFIG_SYS_HRCW_HIGH 0x0
Andre Schwarzc005b932008-06-10 09:13:16 +0200306
307/*
308 * System performance
309 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500311#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
313#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
Andre Schwarzc005b932008-06-10 09:13:16 +0200314
315/* clocking */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_SCCR_ENCCM 0
317#define CONFIG_SYS_SCCR_USBMPHCM 0
318#define CONFIG_SYS_SCCR_USBDRCM 2
319#define CONFIG_SYS_SCCR_TSEC1CM 1
320#define CONFIG_SYS_SCCR_TSEC2CM 1
Andre Schwarzc005b932008-06-10 09:13:16 +0200321
Andre Schwarz116ef542010-10-22 11:21:46 +0200322#define CONFIG_SYS_SICRH 0x1fef0003
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0)
Andre Schwarzc005b932008-06-10 09:13:16 +0200324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_HID0_INIT 0x000000000
Kim Phillips1a2e2032010-04-20 19:37:54 -0500326#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \
327 HID0_ENABLE_INSTRUCTION_CACHE)
Andre Schwarzc005b932008-06-10 09:13:16 +0200328
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_HID2 HID2_HBE
Andre Schwarz5ed546f2008-07-02 18:54:08 +0200330#define CONFIG_HIGH_BATS 1
Andre Schwarzc005b932008-06-10 09:13:16 +0200331
332/* DDR */
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500333#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500334 | BATL_PP_RW \
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500335 | BATL_MEMCOHERENCE)
336#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
337 | BATU_BL_256M \
338 | BATU_VS \
339 | BATU_VP)
Andre Schwarzc005b932008-06-10 09:13:16 +0200340
341/* PCI */
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500342#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500343 | BATL_PP_RW \
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500344 | BATL_MEMCOHERENCE)
345#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
346 | BATU_BL_256M \
347 | BATU_VS \
348 | BATU_VP)
349#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500350 | BATL_PP_RW \
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500351 | BATL_CACHEINHIBIT \
352 | BATL_GUARDEDSTORAGE)
353#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
354 | BATU_BL_256M \
355 | BATU_VS \
356 | BATU_VP)
Andre Schwarzc005b932008-06-10 09:13:16 +0200357
358/* no PCI2 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_IBAT3L 0
360#define CONFIG_SYS_IBAT3U 0
361#define CONFIG_SYS_IBAT4L 0
362#define CONFIG_SYS_IBAT4U 0
Andre Schwarzc005b932008-06-10 09:13:16 +0200363
364/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500365#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500366 | BATL_PP_RW \
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500367 | BATL_CACHEINHIBIT \
368 | BATL_GUARDEDSTORAGE)
369#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
370 | BATU_BL_256M \
371 | BATU_VS \
372 | BATU_VP)
Andre Schwarzc005b932008-06-10 09:13:16 +0200373
374/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500375#define CONFIG_SYS_IBAT6L (0xF0000000 \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500376 | BATL_PP_RW \
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500377 | BATL_MEMCOHERENCE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500378 | BATL_GUARDEDSTORAGE)
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500379#define CONFIG_SYS_IBAT6U (0xF0000000 \
380 | BATU_BL_256M \
381 | BATU_VS \
382 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_IBAT7L 0
384#define CONFIG_SYS_IBAT7U 0
Andre Schwarzc005b932008-06-10 09:13:16 +0200385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
387#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
388#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
389#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
390#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
391#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
392#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
393#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
394#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
395#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
396#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
397#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
398#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
399#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
400#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
401#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Andre Schwarzc005b932008-06-10 09:13:16 +0200402
403/*
Andre Schwarzc005b932008-06-10 09:13:16 +0200404 * Environment Configuration
405 */
406#define CONFIG_ENV_OVERWRITE
407
408#define CONFIG_NETDEV eth0
409
410/* Default path and filenames */
411#define CONFIG_BOOTDELAY 5
412#define CONFIG_AUTOBOOT_KEYED
413#define CONFIG_AUTOBOOT_STOP_STR "s"
414#define CONFIG_ZERO_BOOTDELAY_CHECK
415#define CONFIG_RESET_TO_RETRY 1000
416
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500417#define MV_CI "mvBL-M7"
418#define MV_VCI "mvBL-M7"
André Schwarz28887d82009-08-27 14:48:35 +0200419#define MV_FPGA_DATA 0xfff40000
420#define MV_FPGA_SIZE 0
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200421#define MV_KERNEL_ADDR 0xff810000
422#define MV_INITRD_ADDR 0xffb00000
Peter Tyser3202d332009-09-16 21:38:10 -0500423#define MV_SCRIPT_ADDR 0xff804000
424#define MV_SCRIPT_ADDR2 0xff806000
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200425#define MV_DTB_ADDR 0xff808000
426#define MV_INITRD_LENGTH 0x00400000
Andre Schwarzc005b932008-06-10 09:13:16 +0200427
428#define CONFIG_SHOW_BOOT_PROGRESS 1
429
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200430#define MV_KERNEL_ADDR_RAM 0x00100000
431#define MV_DTB_ADDR_RAM 0x00600000
432#define MV_INITRD_ADDR_RAM 0x01000000
Andre Schwarzc005b932008-06-10 09:13:16 +0200433
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500434#define CONFIG_BOOTCOMMAND "if imi ${script_addr}; " \
435 "then source ${script_addr}; " \
436 "else source ${script_addr2}; " \
437 "fi;"
Andre Schwarzc005b932008-06-10 09:13:16 +0200438#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
439
440#define CONFIG_EXTRA_ENV_SETTINGS \
441 "console_nr=0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200442 "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" \
Andre Schwarzc005b932008-06-10 09:13:16 +0200443 "stdin=serial\0" \
444 "stdout=serial\0" \
445 "stderr=serial\0" \
446 "fpga=0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200447 "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
448 "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
449 "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
450 "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
451 "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
452 "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
453 "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
454 "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
455 "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
456 "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
457 "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
458 "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
Andre Schwarz5ed546f2008-07-02 18:54:08 +0200459 "mv_version=" U_BOOT_VERSION "\0" \
Joe Hershbergerb2773a52011-10-11 23:57:20 -0500460 "dhcp_client_id=" MV_CI "\0" \
461 "dhcp_vendor-class-identifier=" MV_VCI "\0" \
Andre Schwarzc005b932008-06-10 09:13:16 +0200462 "netretry=no\0" \
463 "use_static_ipaddr=no\0" \
464 "static_ipaddr=192.168.90.10\0" \
465 "static_netmask=255.255.255.0\0" \
466 "static_gateway=0.0.0.0\0" \
André Schwarz28887d82009-08-27 14:48:35 +0200467 "initrd_name=uInitrd.mvBL-M7-rfs\0" \
Andre Schwarzc005b932008-06-10 09:13:16 +0200468 "zcip=no\0" \
469 "netboot=yes\0" \
470 "mvtest=Ff\0" \
471 "tried_bootfromflash=no\0" \
472 "tried_bootfromnet=no\0" \
473 "bootfile=mvblm72625.boot\0" \
474 "use_dhcp=yes\0" \
475 "gev_start=yes\0" \
476 "mvbcdma_debug=0\0" \
477 "mvbcia_debug=0\0" \
478 "propdev_debug=0\0" \
479 "gevss_debug=0\0" \
480 "watchdog=0\0" \
481 "usb_dr_mode=host\0" \
Andre Schwarz1a9eeb72008-08-20 11:11:52 +0200482 "sensor_cnt=2\0" \
Andre Schwarzc005b932008-06-10 09:13:16 +0200483 ""
484
485#define CONFIG_FPGA_COUNT 1
Michal Simekb03b25c2013-05-01 18:05:56 +0200486#define CONFIG_FPGA
Andre Schwarzc005b932008-06-10 09:13:16 +0200487#define CONFIG_FPGA_ALTERA
488#define CONFIG_FPGA_CYCLON2
489
490#endif