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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Dinh Nguyen2ac71882018-04-04 17:18:20 -05002/*
3 * Socfpga Reset Controller Driver
4 *
5 * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
6 *
7 * based on
8 * Allwinner SoCs Reset Controller driver
9 *
10 * Copyright 2013 Maxime Ripard
11 *
12 * Maxime Ripard <maxime.ripard@free-electrons.com>
Dinh Nguyen2ac71882018-04-04 17:18:20 -050013 */
14
15#include <common.h>
16#include <dm.h>
Simon Goldschmidtef72ba02019-07-15 21:47:55 +020017#include <dm/lists.h>
Dinh Nguyen2ac71882018-04-04 17:18:20 -050018#include <dm/of_access.h>
19#include <reset-uclass.h>
20#include <linux/bitops.h>
21#include <linux/io.h>
22#include <linux/sizes.h>
23
24#define BANK_INCREMENT 4
25#define NR_BANKS 8
26
27struct socfpga_reset_data {
Simon Goldschmidt1ea97502019-03-01 20:12:30 +010028 void __iomem *modrst_base;
Dinh Nguyen2ac71882018-04-04 17:18:20 -050029};
30
Simon Goldschmidtede6e7b2019-03-01 20:12:32 +010031/*
32 * For compatibility with Kernels that don't support peripheral reset, this
33 * driver can keep the old behaviour of not asserting peripheral reset before
34 * starting the OS and deasserting all peripheral resets (enabling all
35 * peripherals).
36 *
37 * For that, the reset driver checks the environment variable
38 * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not
39 * reset again once taken out of reset and all peripherals in 'permodrst' are
40 * taken out of reset before booting into the OS.
41 * Note that this should be required for gen5 systems only that are running
42 * Linux kernels without proper peripheral reset support for all drivers used.
43 */
44static bool socfpga_reset_keep_enabled(void)
45{
46#if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT)
47 const char *env_str;
48 long val;
49
50 env_str = env_get("socfpga_legacy_reset_compat");
51 if (env_str) {
52 val = simple_strtol(env_str, NULL, 0);
53 if (val == 1)
54 return true;
55 }
56#endif
57
58 return false;
59}
60
Dinh Nguyen2ac71882018-04-04 17:18:20 -050061static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
62{
63 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
64 int id = reset_ctl->id;
65 int reg_width = sizeof(u32);
66 int bank = id / (reg_width * BITS_PER_BYTE);
67 int offset = id % (reg_width * BITS_PER_BYTE);
68
Simon Goldschmidt1ea97502019-03-01 20:12:30 +010069 setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
Dinh Nguyen2ac71882018-04-04 17:18:20 -050070 return 0;
71}
72
73static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
74{
75 struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
76 int id = reset_ctl->id;
77 int reg_width = sizeof(u32);
78 int bank = id / (reg_width * BITS_PER_BYTE);
79 int offset = id % (reg_width * BITS_PER_BYTE);
80
Simon Goldschmidt1ea97502019-03-01 20:12:30 +010081 clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset));
Dinh Nguyen2ac71882018-04-04 17:18:20 -050082 return 0;
83}
84
85static int socfpga_reset_request(struct reset_ctl *reset_ctl)
86{
87 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__,
88 reset_ctl, reset_ctl->dev, reset_ctl->id);
89
90 return 0;
91}
92
93static int socfpga_reset_free(struct reset_ctl *reset_ctl)
94{
95 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
96 reset_ctl->dev, reset_ctl->id);
97
98 return 0;
99}
100
101static const struct reset_ops socfpga_reset_ops = {
102 .request = socfpga_reset_request,
103 .free = socfpga_reset_free,
104 .rst_assert = socfpga_reset_assert,
105 .rst_deassert = socfpga_reset_deassert,
106};
107
108static int socfpga_reset_probe(struct udevice *dev)
109{
110 struct socfpga_reset_data *data = dev_get_priv(dev);
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500111 u32 modrst_offset;
Simon Goldschmidt1ea97502019-03-01 20:12:30 +0100112 void __iomem *membase;
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500113
Simon Goldschmidt1ea97502019-03-01 20:12:30 +0100114 membase = devfdt_get_addr_ptr(dev);
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500115
Simon Goldschmidt6cdd0a42019-05-09 22:11:59 +0200116 modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10);
Simon Goldschmidt1ea97502019-03-01 20:12:30 +0100117 data->modrst_base = membase + modrst_offset;
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500118
119 return 0;
120}
121
Simon Goldschmidtede6e7b2019-03-01 20:12:32 +0100122static int socfpga_reset_remove(struct udevice *dev)
123{
124 struct socfpga_reset_data *data = dev_get_priv(dev);
125
126 if (socfpga_reset_keep_enabled()) {
127 puts("Deasserting all peripheral resets\n");
128 writel(0, data->modrst_base + 4);
129 }
130
131 return 0;
132}
133
Simon Goldschmidtef72ba02019-07-15 21:47:55 +0200134static int socfpga_reset_bind(struct udevice *dev)
135{
136 int ret;
137 struct udevice *sys_child;
138
139 /*
140 * The sysreset driver does not have a device node, so bind it here.
141 * Bind it to the node, too, so that it can get its base address.
142 */
143 ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
144 dev->node, &sys_child);
145 if (ret)
146 debug("Warning: No sysreset driver: ret=%d\n", ret);
147
148 return 0;
149}
150
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500151static const struct udevice_id socfpga_reset_match[] = {
152 { .compatible = "altr,rst-mgr" },
153 { /* sentinel */ },
154};
155
156U_BOOT_DRIVER(socfpga_reset) = {
157 .name = "socfpga-reset",
158 .id = UCLASS_RESET,
159 .of_match = socfpga_reset_match,
Simon Goldschmidtef72ba02019-07-15 21:47:55 +0200160 .bind = socfpga_reset_bind,
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500161 .probe = socfpga_reset_probe,
162 .priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
163 .ops = &socfpga_reset_ops,
Simon Goldschmidtede6e7b2019-03-01 20:12:32 +0100164 .remove = socfpga_reset_remove,
165 .flags = DM_FLAG_OS_PREPARE,
Dinh Nguyen2ac71882018-04-04 17:18:20 -0500166};