Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Socfpga Reset Controller Driver |
| 4 | * |
| 5 | * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de> |
| 6 | * |
| 7 | * based on |
| 8 | * Allwinner SoCs Reset Controller driver |
| 9 | * |
| 10 | * Copyright 2013 Maxime Ripard |
| 11 | * |
| 12 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <common.h> |
| 16 | #include <dm.h> |
Simon Goldschmidt | ef72ba0 | 2019-07-15 21:47:55 +0200 | [diff] [blame] | 17 | #include <dm/lists.h> |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 18 | #include <dm/of_access.h> |
| 19 | #include <reset-uclass.h> |
| 20 | #include <linux/bitops.h> |
| 21 | #include <linux/io.h> |
| 22 | #include <linux/sizes.h> |
| 23 | |
| 24 | #define BANK_INCREMENT 4 |
| 25 | #define NR_BANKS 8 |
| 26 | |
| 27 | struct socfpga_reset_data { |
Simon Goldschmidt | 1ea9750 | 2019-03-01 20:12:30 +0100 | [diff] [blame] | 28 | void __iomem *modrst_base; |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 29 | }; |
| 30 | |
Simon Goldschmidt | ede6e7b | 2019-03-01 20:12:32 +0100 | [diff] [blame] | 31 | /* |
| 32 | * For compatibility with Kernels that don't support peripheral reset, this |
| 33 | * driver can keep the old behaviour of not asserting peripheral reset before |
| 34 | * starting the OS and deasserting all peripheral resets (enabling all |
| 35 | * peripherals). |
| 36 | * |
| 37 | * For that, the reset driver checks the environment variable |
| 38 | * "socfpga_legacy_reset_compat". If this variable is '1', perihperals are not |
| 39 | * reset again once taken out of reset and all peripherals in 'permodrst' are |
| 40 | * taken out of reset before booting into the OS. |
| 41 | * Note that this should be required for gen5 systems only that are running |
| 42 | * Linux kernels without proper peripheral reset support for all drivers used. |
| 43 | */ |
| 44 | static bool socfpga_reset_keep_enabled(void) |
| 45 | { |
| 46 | #if !defined(CONFIG_SPL_BUILD) || CONFIG_IS_ENABLED(ENV_SUPPORT) |
| 47 | const char *env_str; |
| 48 | long val; |
| 49 | |
| 50 | env_str = env_get("socfpga_legacy_reset_compat"); |
| 51 | if (env_str) { |
| 52 | val = simple_strtol(env_str, NULL, 0); |
| 53 | if (val == 1) |
| 54 | return true; |
| 55 | } |
| 56 | #endif |
| 57 | |
| 58 | return false; |
| 59 | } |
| 60 | |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 61 | static int socfpga_reset_assert(struct reset_ctl *reset_ctl) |
| 62 | { |
| 63 | struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); |
| 64 | int id = reset_ctl->id; |
| 65 | int reg_width = sizeof(u32); |
| 66 | int bank = id / (reg_width * BITS_PER_BYTE); |
| 67 | int offset = id % (reg_width * BITS_PER_BYTE); |
| 68 | |
Simon Goldschmidt | 1ea9750 | 2019-03-01 20:12:30 +0100 | [diff] [blame] | 69 | setbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset)); |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 70 | return 0; |
| 71 | } |
| 72 | |
| 73 | static int socfpga_reset_deassert(struct reset_ctl *reset_ctl) |
| 74 | { |
| 75 | struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev); |
| 76 | int id = reset_ctl->id; |
| 77 | int reg_width = sizeof(u32); |
| 78 | int bank = id / (reg_width * BITS_PER_BYTE); |
| 79 | int offset = id % (reg_width * BITS_PER_BYTE); |
| 80 | |
Simon Goldschmidt | 1ea9750 | 2019-03-01 20:12:30 +0100 | [diff] [blame] | 81 | clrbits_le32(data->modrst_base + (bank * BANK_INCREMENT), BIT(offset)); |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 82 | return 0; |
| 83 | } |
| 84 | |
| 85 | static int socfpga_reset_request(struct reset_ctl *reset_ctl) |
| 86 | { |
| 87 | debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, |
| 88 | reset_ctl, reset_ctl->dev, reset_ctl->id); |
| 89 | |
| 90 | return 0; |
| 91 | } |
| 92 | |
| 93 | static int socfpga_reset_free(struct reset_ctl *reset_ctl) |
| 94 | { |
| 95 | debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, |
| 96 | reset_ctl->dev, reset_ctl->id); |
| 97 | |
| 98 | return 0; |
| 99 | } |
| 100 | |
| 101 | static const struct reset_ops socfpga_reset_ops = { |
| 102 | .request = socfpga_reset_request, |
| 103 | .free = socfpga_reset_free, |
| 104 | .rst_assert = socfpga_reset_assert, |
| 105 | .rst_deassert = socfpga_reset_deassert, |
| 106 | }; |
| 107 | |
| 108 | static int socfpga_reset_probe(struct udevice *dev) |
| 109 | { |
| 110 | struct socfpga_reset_data *data = dev_get_priv(dev); |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 111 | u32 modrst_offset; |
Simon Goldschmidt | 1ea9750 | 2019-03-01 20:12:30 +0100 | [diff] [blame] | 112 | void __iomem *membase; |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 113 | |
Simon Goldschmidt | 1ea9750 | 2019-03-01 20:12:30 +0100 | [diff] [blame] | 114 | membase = devfdt_get_addr_ptr(dev); |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 115 | |
Simon Goldschmidt | 6cdd0a4 | 2019-05-09 22:11:59 +0200 | [diff] [blame] | 116 | modrst_offset = dev_read_u32_default(dev, "altr,modrst-offset", 0x10); |
Simon Goldschmidt | 1ea9750 | 2019-03-01 20:12:30 +0100 | [diff] [blame] | 117 | data->modrst_base = membase + modrst_offset; |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 118 | |
| 119 | return 0; |
| 120 | } |
| 121 | |
Simon Goldschmidt | ede6e7b | 2019-03-01 20:12:32 +0100 | [diff] [blame] | 122 | static int socfpga_reset_remove(struct udevice *dev) |
| 123 | { |
| 124 | struct socfpga_reset_data *data = dev_get_priv(dev); |
| 125 | |
| 126 | if (socfpga_reset_keep_enabled()) { |
| 127 | puts("Deasserting all peripheral resets\n"); |
| 128 | writel(0, data->modrst_base + 4); |
| 129 | } |
| 130 | |
| 131 | return 0; |
| 132 | } |
| 133 | |
Simon Goldschmidt | ef72ba0 | 2019-07-15 21:47:55 +0200 | [diff] [blame] | 134 | static int socfpga_reset_bind(struct udevice *dev) |
| 135 | { |
| 136 | int ret; |
| 137 | struct udevice *sys_child; |
| 138 | |
| 139 | /* |
| 140 | * The sysreset driver does not have a device node, so bind it here. |
| 141 | * Bind it to the node, too, so that it can get its base address. |
| 142 | */ |
| 143 | ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset", |
| 144 | dev->node, &sys_child); |
| 145 | if (ret) |
| 146 | debug("Warning: No sysreset driver: ret=%d\n", ret); |
| 147 | |
| 148 | return 0; |
| 149 | } |
| 150 | |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 151 | static const struct udevice_id socfpga_reset_match[] = { |
| 152 | { .compatible = "altr,rst-mgr" }, |
| 153 | { /* sentinel */ }, |
| 154 | }; |
| 155 | |
| 156 | U_BOOT_DRIVER(socfpga_reset) = { |
| 157 | .name = "socfpga-reset", |
| 158 | .id = UCLASS_RESET, |
| 159 | .of_match = socfpga_reset_match, |
Simon Goldschmidt | ef72ba0 | 2019-07-15 21:47:55 +0200 | [diff] [blame] | 160 | .bind = socfpga_reset_bind, |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 161 | .probe = socfpga_reset_probe, |
| 162 | .priv_auto_alloc_size = sizeof(struct socfpga_reset_data), |
| 163 | .ops = &socfpga_reset_ops, |
Simon Goldschmidt | ede6e7b | 2019-03-01 20:12:32 +0100 | [diff] [blame] | 164 | .remove = socfpga_reset_remove, |
| 165 | .flags = DM_FLAG_OS_PREPARE, |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 166 | }; |