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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +05302/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +05304 */
5
6#ifndef __LS1012ARDB_H__
7#define __LS1012ARDB_H__
8
9#include "ls1012a_common.h"
10
Shengzhou Liub9e745b2016-08-26 18:30:39 +080011/* DDR */
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053012#define CONFIG_DIMM_SLOTS_PER_CTLR 1
13#define CONFIG_CHIP_SELECTS_PER_CTRL 1
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053014#define CONFIG_SYS_SDRAM_SIZE 0x40000000
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053015#define CONFIG_CMD_MEMINFO
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053016#define CONFIG_SYS_MEMTEST_START 0x80000000
17#define CONFIG_SYS_MEMTEST_END 0x9fffffff
18
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053019
20/*
21 * I2C IO expander
22 */
23
Yangbo Lu481fb012017-12-08 15:35:35 +080024#define I2C_MUX_IO_ADDR 0x24
Calvin Johnson7ab16472018-03-08 15:30:30 +053025#define I2C_MUX_IO2_ADDR 0x25
Yangbo Lu481fb012017-12-08 15:35:35 +080026#define I2C_MUX_IO_0 0
27#define I2C_MUX_IO_1 1
28#define SW_BOOT_MASK 0x03
29#define SW_BOOT_EMU 0x02
30#define SW_BOOT_BANK1 0x00
31#define SW_BOOT_BANK2 0x01
32#define SW_REV_MASK 0xF8
33#define SW_REV_A 0xF8
34#define SW_REV_B 0xF0
Yangbo Lu4a47bf82017-12-08 15:35:36 +080035#define SW_REV_C 0xE8
36#define SW_REV_C1 0xE0
37#define SW_REV_C2 0xD8
38#define SW_REV_D 0xD0
39#define SW_REV_E 0xC8
Calvin Johnson7ab16472018-03-08 15:30:30 +053040#define __PHY_MASK 0xF9
41#define __PHY_ETH2_MASK 0xFB
42#define __PHY_ETH1_MASK 0xFD
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053043
44/* MMC */
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053045#ifdef CONFIG_MMC
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053046#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053047#endif
48
Prabhakar Kushwaha9e0bb4c2016-12-26 12:15:08 +053049
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053050#define CONFIG_PCIE1 /* PCIE controller 1 */
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053051
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053052#define CONFIG_PCI_SCAN_SHOW
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053053
54#define CONFIG_CMD_MEMINFO
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +053055#define CONFIG_SYS_MEMTEST_START 0x80000000
56#define CONFIG_SYS_MEMTEST_END 0x9fffffff
57
Rajesh Bhagata81357a2017-11-30 16:44:38 +053058#undef CONFIG_EXTRA_ENV_SETTINGS
59#define CONFIG_EXTRA_ENV_SETTINGS \
60 "verify=no\0" \
61 "fdt_high=0xffffffffffffffff\0" \
62 "initrd_high=0xffffffffffffffff\0" \
63 "fdt_addr=0x00f00000\0" \
64 "kernel_addr=0x01000000\0" \
Vinitha Pillai-B57223c883f352018-01-09 23:03:42 +053065 "kernelheader_addr=0x800000\0" \
Rajesh Bhagata81357a2017-11-30 16:44:38 +053066 "scriptaddr=0x80000000\0" \
Vinitha Pillai-B57223c883f352018-01-09 23:03:42 +053067 "scripthdraddr=0x80080000\0" \
Rajesh Bhagata81357a2017-11-30 16:44:38 +053068 "fdtheader_addr_r=0x80100000\0" \
69 "kernelheader_addr_r=0x80200000\0" \
70 "kernel_addr_r=0x81000000\0" \
71 "fdt_addr_r=0x90000000\0" \
72 "load_addr=0xa0000000\0" \
73 "kernel_size=0x2800000\0" \
Vinitha Pillai-B57223c883f352018-01-09 23:03:42 +053074 "kernelheader_size=0x40000\0" \
Rajesh Bhagata81357a2017-11-30 16:44:38 +053075 "console=ttyS0,115200\0" \
76 BOOTENV \
77 "boot_scripts=ls1012ardb_boot.scr\0" \
Vinitha Pillai-B57223c883f352018-01-09 23:03:42 +053078 "boot_script_hdr=hdr_ls1012ardb_bs.out\0" \
Rajesh Bhagata81357a2017-11-30 16:44:38 +053079 "scan_dev_for_boot_part=" \
80 "part list ${devtype} ${devnum} devplist; " \
81 "env exists devplist || setenv devplist 1; " \
82 "for distro_bootpart in ${devplist}; do " \
83 "if fstype ${devtype} " \
84 "${devnum}:${distro_bootpart} " \
85 "bootfstype; then " \
86 "run scan_dev_for_boot; " \
87 "fi; " \
88 "done\0" \
89 "scan_dev_for_boot=" \
90 "echo Scanning ${devtype} " \
91 "${devnum}:${distro_bootpart}...; " \
92 "for prefix in ${boot_prefixes}; do " \
93 "run scan_dev_for_scripts; " \
94 "done;" \
95 "\0" \
Vinitha Pillai-B57223c883f352018-01-09 23:03:42 +053096 "boot_a_script=" \
97 "load ${devtype} ${devnum}:${distro_bootpart} " \
98 "${scriptaddr} ${prefix}${script}; " \
99 "env exists secureboot && load ${devtype} " \
100 "${devnum}:${distro_bootpart} " \
Vinitha V Pillai78c58082019-04-23 05:52:17 +0000101 "${scripthdraddr} ${prefix}${boot_script_hdr}; " \
102 "env exists secureboot " \
Vinitha Pillai-B57223c883f352018-01-09 23:03:42 +0530103 "&& esbc_validate ${scripthdraddr};" \
104 "source ${scriptaddr}\0" \
Rajesh Bhagata81357a2017-11-30 16:44:38 +0530105 "installer=load mmc 0:2 $load_addr " \
106 "/flex_installer_arm64.itb; " \
107 "bootm $load_addr#$board\0" \
108 "qspi_bootcmd=echo Trying load from qspi..;" \
109 "sf probe && sf read $load_addr " \
Vinitha Pillai-B57223c883f352018-01-09 23:03:42 +0530110 "$kernel_addr $kernel_size; env exists secureboot " \
111 "&& sf read $kernelheader_addr_r $kernelheader_addr " \
112 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
113 "bootm $load_addr#$board\0"
Rajesh Bhagata81357a2017-11-30 16:44:38 +0530114
115#undef CONFIG_BOOTCOMMAND
Rajesh Bhagat1f6180d2018-11-05 18:02:53 +0000116#ifdef CONFIG_TFABOOT
117#undef QSPI_NOR_BOOTCOMMAND
118#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
119 "env exists secureboot && esbc_halt;"
120#else
Calvin Johnsona802d1e2018-03-08 15:30:35 +0530121#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\
Vinitha Pillai-B57223c883f352018-01-09 23:03:42 +0530122 "env exists secureboot && esbc_halt;"
Rajesh Bhagat1f6180d2018-11-05 18:02:53 +0000123#endif
Vinitha Pillai-B5722311d14bf2017-03-23 13:48:20 +0530124
125#include <asm/fsl_secure_boot.h>
126
Prabhakar Kushwaha3b6e3892016-06-03 18:41:35 +0530127#endif /* __LS1012ARDB_H__ */