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Robert Beckettd494aec2019-11-12 19:15:19 +00001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2019 Collabora Ltd
4 * Copyright 2019 General Electric Company
5 */
6
7/ {
Robert Beckett41613a72020-01-31 15:07:55 +02008 bootcount {
9 compatible = "u-boot,bootcount-i2c-eeprom";
10 i2c-eeprom = <&bootcount>;
11 };
12
Robert Beckettd494aec2019-11-12 19:15:19 +000013 wdt-reboot {
14 compatible = "wdt-reboot";
15 wdt = <&wdog1>;
16 };
Ian Raybd58b1a2020-01-31 15:07:58 +020017
18 panel-lvds0 {
19 compatible = "simple-panel";
20 };
Robert Beckettd494aec2019-11-12 19:15:19 +000021};
Robert Beckettb64088c2020-01-31 15:07:53 +020022
23&eeprom {
24 partitions {
25 compatible = "fixed-partitions";
Michal Simekf692b472020-05-28 11:48:55 +020026 #address-cells = <1>;
27 #size-cells = <1>;
Robert Beckettb64088c2020-01-31 15:07:53 +020028
Michal Simekf692b472020-05-28 11:48:55 +020029 vpd@0 {
Ian Ray559aaa22020-11-04 17:18:42 +010030 reg = <0 800>;
Robert Beckettb64088c2020-01-31 15:07:53 +020031 };
32
Robert Beckett41613a72020-01-31 15:07:55 +020033 bootcount: bootcount {
Michal Simekf692b472020-05-28 11:48:55 +020034 reg = <1022 2>;
Robert Beckettb64088c2020-01-31 15:07:53 +020035 };
36 };
37};
Sebastian Reichel4ac026a2021-04-23 16:15:08 +020038
39/*
40 * This is not done in imx6q-ba16.dtsi, since that file is shared
41 * with the kernel and the kernel should not reset the PHY, since
42 * it lacks support for configuring the reserved registeres to
43 * avoid a board specific voltage peak issue.
44 */
45&fec {
46 phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
47 phy-reset-duration = <1>;
48 phy-reset-post-delay = <0>;
49};