| Konstantin Porotchkin | 0d92f21 | 2016-12-19 17:04:42 +0200 | [diff] [blame^] | 1 | Memory Layout on Armada-8k SoC's |
| 2 | ================================ |
| 3 | |
| 4 | The below desribes the physical memory layout for Marvell's Armada-8k SoC's. |
| 5 | |
| 6 | This assumes that the SoC includes Dual CP configuration, in case the flavor is using |
| 7 | a single CP configuration, then all secondary-CP mappings are invalid. |
| 8 | |
| 9 | All "Reserved" areas below, are kept for future usage. |
| 10 | |
| 11 | Start End Use |
| 12 | -------------------------------------------------------------------------- |
| 13 | 0x00000000 0xEFFFFFFF DRAM |
| 14 | |
| 15 | 0xF0000000 0xF0FFFFFF AP Internal registers space |
| 16 | |
| 17 | 0xF1000000 0xF1FFFFFF Reserved. |
| 18 | |
| 19 | 0xF2000000 0xF3FFFFFF CP-0 Internal (configuration) registers |
| 20 | space. |
| 21 | |
| 22 | 0xF4000000 0xF5FFFFFF CP-1 Internal (configuration) registers |
| 23 | space. |
| 24 | |
| 25 | 0xF6000000 0xF6FFFFFF CP-0 / PCIe#0 Memory space. |
| 26 | |
| 27 | 0xF7000000 0xF7FFFFFF CP-0 / PCIe#1 Memory space. |
| 28 | |
| 29 | 0xF8000000 0xF8FFFFFF CP-0 / PCIe#2 Memory space. |
| 30 | |
| 31 | 0xF9000000 0xF900FFFF CP-0 / PCIe#0 IO space. |
| 32 | |
| 33 | 0xF9010000 0xF901FFFF CP-0 / PCIe#1 IO space. |
| 34 | |
| 35 | 0xF9020000 0xF902FFFF CP-0 / PCIe#2 IO space. |
| 36 | |
| 37 | 0xF9030000 0xF9FFFFFF Reserved. |
| 38 | |
| 39 | 0xFA000000 0xFAFFFFFF CP-1 / PCIe#0 Memory space. |
| 40 | |
| 41 | 0xFB000000 0xFBFFFFFF CP-1 / PCIe#1 Memory space. |
| 42 | |
| 43 | 0xFC000000 0xFCFFFFFF CP-1 / PCIe#2 Memory space. |
| 44 | |
| 45 | 0xFD000000 0xFD00FFFF CP-1 / PCIe#0 IO space. |
| 46 | |
| 47 | 0xFD010000 0xFD01FFFF CP-1 / PCIe#1 IO space. |
| 48 | |
| 49 | 0xFD020000 0xFD02FFFF CP-1 / PCIe#2 IO space. |
| 50 | |
| 51 | 0xFD030000 0xFFEFFFFF Reserved. |
| 52 | |
| 53 | 0xFFF00000 0xFFFFFFFF Bootrom |
| 54 | |
| 55 | 0x100000000 <DRAM Size>-1 DRAM |
| 56 | |