Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 0ddd969aec532bd7eae30fc09590488a3aaa629a / . / include / configs / korat.h
blob: 7d0640bbcf82645102bdbee9f71a4c3e673fa80d [file] [log] [blame]
Larry Johnson87dc0962007-12-22 15:16:25 -0500[diff] [blame]1/*
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500[diff] [blame^]2 * (C) Copyright 2007-2008
Larry Johnson87dc0962007-12-22 15:16:25 -0500[diff] [blame]3 * Larry Johnson, lrj@acm.org
4 *
5 * (C) Copyright 2006-2007
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
8 * (C) Copyright 2006
9 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
10 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28/************************************************************************
29 * korat.h - configuration for Korat board
30 ***********************************************************************/
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/*-----------------------------------------------------------------------
35 * High Level Configuration Options
36 *----------------------------------------------------------------------*/
37#define CONFIG_440EPX 1 /* Specific PPC440EPx */
38#define CONFIG_4xx 1 /* ... PPC4xx family */
39#define CONFIG_SYS_CLK_FREQ 33333333
40
41#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
42#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
43
44/*-----------------------------------------------------------------------
45 * Manufacturer's information serial EEPROM parameters
46 *----------------------------------------------------------------------*/
47#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
48#define MAN_SERIAL_NO_FIELD 2
49#define MAN_SERIAL_NO_LENGTH 13
50#define MAN_MAC_ADDR_FIELD 3
51#define MAN_MAC_ADDR_LENGTH 17
52
53/*-----------------------------------------------------------------------
54 * Base addresses -- Note these are effective addresses where the
55 * actual resources get mapped (not physical addresses)
56 *----------------------------------------------------------------------*/
57#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
58#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
59
60#define CFG_BOOT_BASE_ADDR 0xf0000000
61#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
62#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
63#define CFG_MONITOR_BASE TEXT_BASE
64#define CFG_OCM_BASE 0xe0010000 /* ocm */
65#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
66#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
67#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
68#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
69#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
70#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
71
72/* Don't change either of these */
73#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
74
75#define CFG_USB2D0_BASE 0xe0000100
76#define CFG_USB_DEVICE 0xe0000000
77#define CFG_USB_HOST 0xe0000400
78#define CFG_CPLD_BASE 0xc0000000
79
80/*-----------------------------------------------------------------------
81 * Initial RAM & stack pointer
82 *----------------------------------------------------------------------*/
83/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
84#undef CFG_INIT_RAM_DCACHE
85#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
86#define CFG_INIT_RAM_END (4 << 10)
87#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
88#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
89#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
90
91/*-----------------------------------------------------------------------
92 * Serial Port
93 *----------------------------------------------------------------------*/
94#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
95#define CONFIG_BAUDRATE 115200
96#define CONFIG_SERIAL_MULTI 1
97/* define this if you want console on UART1 */
98#undef CONFIG_UART1_CONSOLE
99
100#define CFG_BAUDRATE_TABLE \
101 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
102
103/*-----------------------------------------------------------------------
104 * Environment
105 *----------------------------------------------------------------------*/
106#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
107
108/*-----------------------------------------------------------------------
109 * FLASH related
110 *----------------------------------------------------------------------*/
111#define CFG_FLASH_CFI /* The flash is CFI compatible */
112#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
113
114#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
115
116#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
117#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
118
119#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
120#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
121
122#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
123#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */
124
125#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
126#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
127
128#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
129#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
130#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
131
132/* Address and size of Redundant Environment Sector */
133#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
134#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
135
136/*-----------------------------------------------------------------------
137 * DDR SDRAM
138 *----------------------------------------------------------------------*/
139#define CFG_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */
140#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
141#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
142#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */
143#define CONFIG_DDR_ECC /* Use ECC when available */
144#define SPD_EEPROM_ADDRESS {0x50}
145#define CONFIG_PROG_SDRAM_TLB
146#define CFG_DRAM_TEST
147
148/*-----------------------------------------------------------------------
149 * I2C
150 *----------------------------------------------------------------------*/
151#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
152#undef CONFIG_SOFT_I2C /* I2C bit-banged */
153#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
154#define CFG_I2C_SLAVE 0x7F
155
156#define CFG_I2C_MULTI_EEPROMS
157#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
158#define CFG_I2C_EEPROM_ADDR_LEN 1
159#define CFG_EEPROM_PAGE_WRITE_ENABLE
160#define CFG_EEPROM_PAGE_WRITE_BITS 3
161#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
162
163/* I2C RTC */
164#define CONFIG_RTC_M41T60 1
165#define CFG_I2C_RTC_ADDR 0x68
166
167/* I2C SYSMON (LM73) */
168#define CONFIG_DTT_LM73 1 /* National Semi's LM73 */
169#define CONFIG_DTT_SENSORS {2} /* Sensor addresses */
170#define CFG_DTT_MAX_TEMP 70
171#define CFG_DTT_MIN_TEMP -30
172
173#define CONFIG_PREBOOT "echo;" \
174 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
175 "echo"
176
177#undef CONFIG_BOOTARGS
178
179/* Setup some board specific values for the default environment variables */
180#define CONFIG_HOSTNAME korat
181#define CFG_BOOTFILE "bootfile=/tftpboot/korat/uImage\0"
182#define CFG_ROOTPATH "rootpath=/opt/eldk/ppc_4xxFP\0"
183
184#define CONFIG_EXTRA_ENV_SETTINGS \
185 CFG_BOOTFILE \
186 CFG_ROOTPATH \
187 "netdev=eth0\0" \
188 "nfsargs=setenv bootargs root=/dev/nfs rw " \
189 "nfsroot=${serverip}:${rootpath}\0" \
190 "ramargs=setenv bootargs root=/dev/ram rw\0" \
191 "addip=setenv bootargs ${bootargs} " \
192 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
193 ":${hostname}:${netdev}:off panic=1\0" \
194 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
195 "flash_nfs=run nfsargs addip addtty;" \
196 "bootm ${kernel_addr}\0" \
197 "flash_self=run ramargs addip addtty;" \
198 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
199 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
200 "bootm\0" \
201 "kernel_addr=FC000000\0" \
202 "ramdisk_addr=FC180000\0" \
203 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
204 "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
205 "cp.b 200000 FFFA0000 60000\0" \
206 "upd=run load;run update\0" \
207 ""
208#define CONFIG_BOOTCOMMAND "run flash_self"
209
210#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
211
212#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
213#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
214
215#define CONFIG_IBM_EMAC4_V4 1
216#define CONFIG_MII 1 /* MII PHY management */
217#define CONFIG_PHY_ADDR 2 /* PHY address, See schematics */
218#define CONFIG_PHY_DYNAMIC_ANEG 1
219
220#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
221#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
222
223#define CONFIG_HAS_ETH0
224#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
225
226#define CONFIG_NET_MULTI 1
227#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
228#define CONFIG_PHY1_ADDR 3
229
230/* USB */
231#define CONFIG_USB_OHCI
232#define CONFIG_USB_STORAGE
233
234/* Comment this out to enable USB 1.1 device */
235#define USB_2_0_DEVICE
236
237/* Partitions */
238#define CONFIG_MAC_PARTITION
239#define CONFIG_DOS_PARTITION
240#define CONFIG_ISO_PARTITION
241
242/*
243 * BOOTP options
244 */
245#define CONFIG_BOOTP_BOOTFILESIZE
246#define CONFIG_BOOTP_BOOTPATH
247#define CONFIG_BOOTP_GATEWAY
248#define CONFIG_BOOTP_HOSTNAME
249#define CONFIG_BOOTP_SUBNETMASK
250
251/*
252 * Command line configuration.
253 */
254#include <config_cmd_default.h>
255
256#define CONFIG_CMD_ASKENV
257#define CONFIG_CMD_DATE
258#define CONFIG_CMD_DHCP
259#define CONFIG_CMD_DTT
260#define CONFIG_CMD_DIAG
261#define CONFIG_CMD_EEPROM
262#define CONFIG_CMD_ELF
263#define CONFIG_CMD_FAT
264#define CONFIG_CMD_I2C
265#define CONFIG_I2C_CMD_TREE
266#define CONFIG_CMD_IRQ
267#define CONFIG_CMD_MII
268#define CONFIG_CMD_NET
269#define CONFIG_CMD_NFS
270#define CONFIG_CMD_PCI
271#define CONFIG_CMD_PING
272#define CONFIG_CMD_REGINFO
273#define CONFIG_CMD_SDRAM
274#define CONFIG_CMD_USB
275
276/* POST support */
277#define CONFIG_POST (CFG_POST_CACHE | \
278 CFG_POST_CPU | \
279 CFG_POST_ECC | \
280 CFG_POST_ETHER | \
281 CFG_POST_FPU | \
282 CFG_POST_I2C | \
283 CFG_POST_MEMORY | \
284 CFG_POST_RTC | \
285 CFG_POST_SPR | \
286 CFG_POST_UART)
287
288#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
289#define CONFIG_LOGBUFFER
290#define CFG_POST_CACHE_ADDR 0xC8000000 /* free virtual address */
291
292#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
293
294#define CONFIG_SUPPORT_VFAT
295
296/*-----------------------------------------------------------------------
297 * Miscellaneous configurable options
298 *----------------------------------------------------------------------*/
299#define CFG_LONGHELP /* undef to save memory */
300#define CFG_PROMPT "=> " /* Monitor Command Prompt */
301#if defined(CONFIG_CMD_KGDB)
302#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
303#else
304#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
305#endif
306#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
307#define CFG_MAXARGS 16 /* max number of command args */
308#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
309
310#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
311#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
312
313#define CFG_LOAD_ADDR 0x100000 /* default load address */
314#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
315
316#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
317
318#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
319#define CONFIG_LOOPW 1 /* enable loopw command */
320#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
321#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
322#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
323
324/*-----------------------------------------------------------------------
325 * PCI stuff
326 *----------------------------------------------------------------------*/
327/* General PCI */
328#define CONFIG_PCI /* include pci support */
329#define CONFIG_PCI_PNP /* do pci plug-and-play */
330#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
331#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
332#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
333
334/* Board-specific PCI */
335#define CFG_PCI_TARGET_INIT
336#define CFG_PCI_MASTER_INIT
337
338#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
339#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
340
341/*
342 * For booting Linux, the board info and command line data
343 * have to be in the first 8 MB of memory, since this is
344 * the maximum mapped by the Linux kernel during initialization.
345 */
346#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
347
348/*-----------------------------------------------------------------------
349 * External Bus Controller (EBC) Setup
350 *----------------------------------------------------------------------*/
351
352/* Memory Bank 0 (NOR-FLASH) initialization */
353#define CFG_EBC_PB0AP 0x04017300
354#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0x000DA000)
355
356/* Memory Bank 1 (NOR-FLASH) initialization */
357#define CFG_EBC_PB1AP 0x04017300
358#define CFG_EBC_PB1CR (0xF8000000 | 0x000DA000)
359
360/* Memory Bank 2 (CPLD) initialization */
361#define CFG_EBC_PB2AP 0x04017300
362#define CFG_EBC_PB2CR (CFG_CPLD_BASE | 0x00038000)
363
Lawrence R. Johnson0ddd9692008-01-03 15:02:02 -0500[diff] [blame^]364/*-----------------------------------------------------------------------
365 * GPIO Setup
366 *
367 * Korat GPIO usage:
368 *
369 * Init.
370 * Pin Source I/O value Function
371 * ------ ------ --- ----- ---------------------------------
372 * GPIO00 Alt1 I/O x PerAddr07
373 * GPIO01 Alt1 I/O x PerAddr06
374 * GPIO02 Alt1 I/O x PerAddr05
375 * GPIO03 GPIO x x GPIO03 to expansion bus connector
376 * GPIO04 GPIO x x GPIO04 to expansion bus connector
377 * GPIO05 GPIO x x GPIO05 to expansion bus connector
378 * GPIO06 Alt1 O x PerCS1 (2nd NOR flash)
379 * GPIO07 Alt1 O x PerCS2 (CPLD)
380 * GPIO08 Alt1 O x PerCS3 to expansion bus connector
381 * GPIO09 Alt1 O x PerCS4 to expansion bus connector
382 * GPIO10 Alt1 O x PerCS5 to expansion bus connector
383 * GPIO11 Alt1 I x PerErr
384 * GPIO12 GPIO O 0 ATMega !Reset
385 * GPIO13 GPIO O 1 SPI Atmega !SS
386 * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8)
387 * GPIO15 GPIO O 0 CPU Run LED !On
388 * GPIO16 Alt1 O x GMC1TxD0
389 * GPIO17 Alt1 O x GMC1TxD1
390 * GPIO18 Alt1 O x GMC1TxD2
391 * GPIO19 Alt1 O x GMC1TxD3
392 * GPIO20 Alt1 I x RejectPkt0
393 * GPIO21 Alt1 I x RejectPkt1
394 * GPIO22 GPIO I x PGOOD_DDR
395 * GPIO23 Alt1 O x SCPD0
396 * GPIO24 Alt1 O x GMC0TxD2
397 * GPIO25 Alt1 O x GMC0TxD3
398 * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4)
399 * GPIO27 GPIO O 0 PHY #0 1000BASE-X select
400 * GPIO28 GPIO O 0 PHY #1 1000BASE-X select
401 * GPIO29 GPIO I x Test jumper !Present
402 * GPIO30 GPIO I x SFP module #0 !Present
403 * GPIO31 GPIO I x SFP module #1 !Present
404 *
405 * GPIO32 GPIO O 1 SFP module #0 Tx !Enable
406 * GPIO33 GPIO O 1 SFP module #1 Tx !Enable
407 * GPIO34 Alt2 I x !UART1_CTS
408 * GPIO35 Alt2 O x !UART1_RTS
409 * GPIO36 Alt1 I x !UART0_CTS
410 * GPIO37 Alt1 O x !UART0_RTS
411 * GPIO38 Alt2 O x UART1_Tx
412 * GPIO39 Alt2 I x UART1_Rx
413 * GPIO40 Alt1 I x IRQ0 (Ethernet 0)
414 * GPIO41 Alt1 I x IRQ1 (Ethernet 1)
415 * GPIO42 Alt1 I x IRQ2 (PCI interrupt)
416 * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD)
417 * GPIO44 xxxx x x (grounded through pulldown)
418 * GPIO45 GPIO O 0 PHY #0 Enable
419 * GPIO46 GPIO O 0 PHY #1 Enable
420 * GPIO47 GPIO I x Reset switch !Pressed
421 * GPIO48 GPIO I x Shutdown switch !Pressed
422 * GPIO49 xxxx x x (reserved for trace port)
423 * . . . . .
424 * . . . . .
425 * . . . . .
426 * GPIO63 xxxx x x (reserved for trace port)
427*----------------------------------------------------------------------*/
428
429#define CFG_GPIO_ATMEGA_SS_ 13
430#define CFG_GPIO_PHY0_FIBER_SEL 27
431#define CFG_GPIO_PHY1_FIBER_SEL 28
432#define CFG_GPIO_SFP0_PRESENT_ 30
433#define CFG_GPIO_SFP1_PRESENT_ 31
434#define CFG_GPIO_SFP0_TX_EN_ 32
435#define CFG_GPIO_SFP1_TX_EN_ 33
436#define CFG_GPIO_PHY0_EN 45
437#define CFG_GPIO_PHY1_EN 46
438
439/*-----------------------------------------------------------------------
440 * PPC440 GPIO Configuration
441 */
442#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
443{ \
444/* GPIO Core 0 */ \
445{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
446{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
447{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
448{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
449{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
450{GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
451{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
452{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
453{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
454{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
455{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
456{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
457{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
458{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO13 */ \
459{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
460{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
461{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4) */ \
462{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5) */ \
463{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6) */ \
464{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7) */ \
465{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
466{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
467{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
468{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
469{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2) */ \
470{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3) */ \
471{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
472{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
473{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
474{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
475{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
476{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
477}, \
478{ \
479/* GPIO Core 1 */ \
480{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
481{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
482{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
483{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
484{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
485{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
486{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
487{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
488{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
489{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
490{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
491{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
492{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
493{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
494{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
495{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
496{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
497{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
498{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
499{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
500{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
501{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
502{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
503{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
504{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
505{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
506{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
507{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
508{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
509{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
510{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
511{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
512} \
513}
514
Larry Johnson87dc0962007-12-22 15:16:25 -0500[diff] [blame]515/*
516 * Internal Definitions
517 *
518 * Boot Flags
519 */
520#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
521#define BOOTFLAG_WARM 0x02 /* Software reboot */
522
523#if defined(CONFIG_CMD_KGDB)
524#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
525#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
526#endif
527#endif /* __CONFIG_H */