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Dirk Eibachab4c62c2009-07-27 08:49:48 +02001/*
2 * (C) Copyright 2009
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * Based on board/amcc/canyonlands/init.S
6 * (C) Copyright 2008
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <ppc_asm.tmpl>
29#include <config.h>
30#include <asm-ppc/mmu.h>
31
32/**************************************************************************
33 * TLB TABLE
34 *
35 * This table is used by the cpu boot code to setup the initial tlb
36 * entries. Rather than make broad assumptions in the cpu source tree,
37 * this table lets each board set things up however they like.
38 *
39 * Pointer to the table is returned in r1
40 *
41 *************************************************************************/
42 .section .bootpg,"ax"
43 .globl tlbtab
44
45tlbtab:
46 tlbtab_start
47
48 /*
49 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
50 * use the speed up boot process. It is patched after relocation to
51 * enable SA_I
52 */
53 tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
54 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
55
56 /*
57 * TLB entries for SDRAM are not needed on this platform.
58 * They are dynamically generated in the SPD DDR(2) detection
59 * routine.
60 */
61
62#ifdef CONFIG_SYS_INIT_RAM_DCACHE
63 /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
64 tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
65 0, AC_R|AC_W|AC_X|SA_G)
66#endif
67
68 tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC,
69 AC_R|AC_W|SA_G|SA_I)
70 tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC,
71 AC_R|AC_W|SA_G|SA_I)
72
73 /* TLB-entry for NVRAM */
74 tlbentry(CONFIG_SYS_NVRAM_BASE, SZ_1M, CONFIG_SYS_NVRAM_BASE, 4,
75 AC_R|AC_W|SA_G|SA_I)
76
77 /* TLB-entry for UART */
78 tlbentry(CONFIG_SYS_UART_BASE, SZ_16K, CONFIG_SYS_UART_BASE, 4,
79 AC_R|AC_W|SA_G|SA_I)
80
81 /* TLB-entry for IO */
82 tlbentry(CONFIG_SYS_IO_BASE, SZ_16K, CONFIG_SYS_IO_BASE, 4,
83 AC_R|AC_W|SA_G|SA_I)
84
85 /* TLB-entry for OCM */
86 tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
87 AC_R|AC_W|AC_X|SA_I)
88
89 /* TLB-entry for Local Configuration registers => peripherals */
90 tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS,
91 4, AC_R|AC_W|AC_X|SA_G|SA_I)
92
93 /* AHB: Internal USB Peripherals (USB, SATA) */
94 tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4,
95 AC_R|AC_W|AC_X|SA_G|SA_I)
96
97 tlbtab_end