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Nobuhiro Iwamatsue92c95182008-03-12 12:15:29 +09001#ifndef __ASM_SH_CACHE_H
2#define __ASM_SH_CACHE_H
3
4#if defined(CONFIG_SH4) || defined(CONFIG_SH4A)
5
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +09006int cache_control(unsigned int cmd);
7
Nobuhiro Iwamatsue92c95182008-03-12 12:15:29 +09008#define L1_CACHE_BYTES 32
9struct __large_struct { unsigned long buf[100]; };
10#define __m(x) (*(struct __large_struct *)(x))
11
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +090012void dcache_wback_range(u32 start, u32 end)
Nobuhiro Iwamatsue92c95182008-03-12 12:15:29 +090013{
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070014 u32 v;
Nobuhiro Iwamatsue92c95182008-03-12 12:15:29 +090015
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070016 start &= ~(L1_CACHE_BYTES - 1);
17 for (v = start; v < end; v += L1_CACHE_BYTES) {
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +090018 asm volatile ("ocbwb %0" : /* no output */
19 : "m" (__m(v)));
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070020 }
Nobuhiro Iwamatsue92c95182008-03-12 12:15:29 +090021}
22
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +090023void dcache_invalid_range(u32 start, u32 end)
Nobuhiro Iwamatsue92c95182008-03-12 12:15:29 +090024{
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070025 u32 v;
Nobuhiro Iwamatsue92c95182008-03-12 12:15:29 +090026
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070027 start &= ~(L1_CACHE_BYTES - 1);
28 for (v = start; v < end; v += L1_CACHE_BYTES) {
Nobuhiro Iwamatsub5d10a12008-09-18 19:34:36 +090029 asm volatile ("ocbi %0" : /* no output */
30 : "m" (__m(v)));
Wolfgang Denk1aeed8d2008-04-13 09:59:26 -070031 }
Nobuhiro Iwamatsue92c95182008-03-12 12:15:29 +090032}
33#endif /* CONFIG_SH4 || CONFIG_SH4A */
34
35#endif /* __ASM_SH_CACHE_H */