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wdenka87589d2005-06-10 10:00:19 +00001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27/*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
34#define CONFIG_HMI1001 1 /* HMI1001 board */
35
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
wdenka87589d2005-06-10 10:00:19 +000037
38#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39#define BOOTFLAG_WARM 0x02 /* Software reboot */
40
wdenka87589d2005-06-10 10:00:19 +000041#define CONFIG_BOARD_EARLY_INIT_R
42
Becky Bruce31d82672008-05-08 19:02:12 -050043#define CONFIG_HIGH_BATS 1 /* High BATs supported */
44
wdenka87589d2005-06-10 10:00:19 +000045/*
46 * Serial console configuration
47 */
48#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenka87589d2005-06-10 10:00:19 +000051
Wolfgang Denk08abe152005-07-21 15:23:29 +020052/* Partitions */
53#define CONFIG_DOS_PARTITION
54
wdenka87589d2005-06-10 10:00:19 +000055
Jon Loeliger48d5d102007-07-04 22:32:25 -050056/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050057 * BOOTP options
58 */
59#define CONFIG_BOOTP_BOOTFILESIZE
60#define CONFIG_BOOTP_BOOTPATH
61#define CONFIG_BOOTP_GATEWAY
62#define CONFIG_BOOTP_HOSTNAME
63
64
65/*
Jon Loeliger48d5d102007-07-04 22:32:25 -050066 * Command line configuration.
67 */
68#include <config_cmd_default.h>
69
70#define CONFIG_CMD_DATE
71#define CONFIG_CMD_DISPLAY
72#define CONFIG_CMD_DHCP
73#define CONFIG_CMD_EEPROM
74#define CONFIG_CMD_I2C
75#define CONFIG_CMD_IDE
76#define CONFIG_CMD_NFS
77#define CONFIG_CMD_PCI
78#define CONFIG_CMD_SNTP
79
wdenka87589d2005-06-10 10:00:19 +000080
81#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
82
83#if (TEXT_BASE == 0xFFF00000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084# define CONFIG_SYS_LOWBOOT 1
wdenka87589d2005-06-10 10:00:19 +000085#endif
86
87/*
88 * Autobooting
89 */
90#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
91
92#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010093 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
wdenka87589d2005-06-10 10:00:19 +000094 "echo"
95
96#undef CONFIG_BOOTARGS
97
98#define CONFIG_EXTRA_ENV_SETTINGS \
99 "netdev=eth0\0" \
100 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100101 "nfsroot=${serverip}:${rootpath}\0" \
wdenka87589d2005-06-10 10:00:19 +0000102 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100103 "addip=setenv bootargs ${bootargs} " \
104 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
105 ":${hostname}:${netdev}:off panic=1\0" \
wdenka87589d2005-06-10 10:00:19 +0000106 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100107 "bootm ${kernel_addr}\0" \
108 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenka87589d2005-06-10 10:00:19 +0000109 "rootpath=/opt/eldk/ppc_82xx\0" \
110 ""
111
112#define CONFIG_BOOTCOMMAND "run net_nfs"
113
Wolfgang Denk9f96ae42005-08-30 13:04:12 +0200114#define CONFIG_MISC_INIT_R 1
115
wdenka87589d2005-06-10 10:00:19 +0000116/*
117 * IPB Bus clocking configuration.
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
wdenka87589d2005-06-10 10:00:19 +0000120
121/*
wdenk342717f2005-06-27 13:30:03 +0000122 * I2C configuration
123 */
124#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
wdenk342717f2005-06-27 13:30:03 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
128#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk342717f2005-06-27 13:30:03 +0000129
130/*
131 * EEPROM configuration
132 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
134#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
135#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
136#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenk342717f2005-06-27 13:30:03 +0000137
138/*
139 * RTC configuration
140 */
141#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenk342717f2005-06-27 13:30:03 +0000143
144/*
wdenka87589d2005-06-10 10:00:19 +0000145 * Flash configuration
146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_FLASH_BASE 0xFF800000
wdenka87589d2005-06-10 10:00:19 +0000148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
150#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
wdenka87589d2005-06-10 10:00:19 +0000151
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200152#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
wdenka87589d2005-06-10 10:00:19 +0000154 (= chip selects) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
156#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenka87589d2005-06-10 10:00:19 +0000157
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200158#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_FLASH_CFI
160#define CONFIG_SYS_FLASH_EMPTY_INFO
161#define CONFIG_SYS_FLASH_CFI_AMD_RESET
wdenka87589d2005-06-10 10:00:19 +0000162
163/*
164 * Environment settings
165 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200166#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200167#define CONFIG_ENV_SIZE 0x4000
168#define CONFIG_ENV_SECT_SIZE 0x20000
169#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
170#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenka87589d2005-06-10 10:00:19 +0000171
172/*
173 * Memory map
174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_MBAR 0xF0000000
176#define CONFIG_SYS_SDRAM_BASE 0x00000000
177#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
178#define CONFIG_SYS_DISPLAY_BASE 0x80600000
179#define CONFIG_SYS_STATUS1_BASE 0x80600200
180#define CONFIG_SYS_STATUS2_BASE 0x80600300
wdenka87589d2005-06-10 10:00:19 +0000181
182/* Settings for XLB = 132 MHz */
183#define SDRAM_DDR 1
184#define SDRAM_MODE 0x018D0000
185#define SDRAM_EMODE 0x40090000
186#define SDRAM_CONTROL 0x714f0f00
187#define SDRAM_CONFIG1 0x73722930
188#define SDRAM_CONFIG2 0x47770000
189#define SDRAM_TAPDELAY 0x10000000
190
191/* Use ON-Chip SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
wdenka87589d2005-06-10 10:00:19 +0000193#ifdef CONFIG_POST
194/* preserve space for the post_word at end of on-chip SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
wdenka87589d2005-06-10 10:00:19 +0000196#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
wdenka87589d2005-06-10 10:00:19 +0000198#endif
199
200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
202#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
203#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenka87589d2005-06-10 10:00:19 +0000204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
206#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
207# define CONFIG_SYS_RAMBOOT 1
wdenka87589d2005-06-10 10:00:19 +0000208#endif
209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
211#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
212#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenka87589d2005-06-10 10:00:19 +0000213
214/*
215 * Ethernet configuration
216 */
217#define CONFIG_MPC5xxx_FEC 1
Ben Warren86321fc2009-02-05 23:58:25 -0800218#define CONFIG_MPC5xxx_FEC_MII100
wdenka87589d2005-06-10 10:00:19 +0000219#define CONFIG_PHY_ADDR 0x00
Wolfgang Denk8d7e2732007-03-07 16:19:46 +0100220#define CONFIG_MII 1 /* MII PHY management */
wdenka87589d2005-06-10 10:00:19 +0000221
222/*
223 * GPIO configuration
224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_GPS_PORT_CONFIG 0x01051004
wdenka87589d2005-06-10 10:00:19 +0000226
227/*
wdenka87589d2005-06-10 10:00:19 +0000228 * Miscellaneous configurable options
229 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_LONGHELP /* undef to save memory */
231#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger48d5d102007-07-04 22:32:25 -0500232#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenka87589d2005-06-10 10:00:19 +0000234#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenka87589d2005-06-10 10:00:19 +0000236#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
238#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
239#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenka87589d2005-06-10 10:00:19 +0000240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeliger48d5d102007-07-04 22:32:25 -0500242#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger48d5d102007-07-04 22:32:25 -0500244#endif
245
wdenka87589d2005-06-10 10:00:19 +0000246/* Enable an alternate, more extensive memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_ALT_MEMTEST
wdenka87589d2005-06-10 10:00:19 +0000248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
250#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
wdenka87589d2005-06-10 10:00:19 +0000251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenka87589d2005-06-10 10:00:19 +0000253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenka87589d2005-06-10 10:00:19 +0000255
256/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500257 * Enable loopw command.
wdenka87589d2005-06-10 10:00:19 +0000258 */
259#define CONFIG_LOOPW
260
261/*
262 * Various low-level settings
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
265#define CONFIG_SYS_HID0_FINAL HID0_ICE
wdenka87589d2005-06-10 10:00:19 +0000266
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
268#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
269#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00
270#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
271#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
wdenka87589d2005-06-10 10:00:19 +0000272
273/* 8Mbit SRAM @0x80100000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_CS1_START 0x80100000
275#define CONFIG_SYS_CS1_SIZE 0x00100000
276#define CONFIG_SYS_CS1_CFG 0x19B00
wdenka87589d2005-06-10 10:00:19 +0000277
278/* FRAM 32Kbyte @0x80700000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_CS2_START 0x80700000
280#define CONFIG_SYS_CS2_SIZE 0x00008000
281#define CONFIG_SYS_CS2_CFG 0x19800
wdenka87589d2005-06-10 10:00:19 +0000282
283/* Display H1, Status Inputs, EPLD @0x80600000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_CS3_START 0x80600000
285#define CONFIG_SYS_CS3_SIZE 0x00100000
286#define CONFIG_SYS_CS3_CFG 0x00019800
wdenka87589d2005-06-10 10:00:19 +0000287
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_CS_BURST 0x00000000
289#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
wdenka87589d2005-06-10 10:00:19 +0000290
Wolfgang Denk08abe152005-07-21 15:23:29 +0200291/*-----------------------------------------------------------------------
292 * IDE/ATA stuff Supports IDE harddisk
293 *-----------------------------------------------------------------------
294 */
295
296#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
297
298#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
299#undef CONFIG_IDE_LED /* LED for ide not supported */
300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
302#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
Wolfgang Denk08abe152005-07-21 15:23:29 +0200303
Wolfgang Denk9d3338d2005-08-10 10:06:25 +0200304#define CONFIG_IDE_PREINIT 1
305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Wolfgang Denk08abe152005-07-21 15:23:29 +0200307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
Wolfgang Denk08abe152005-07-21 15:23:29 +0200309
310/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
Wolfgang Denk08abe152005-07-21 15:23:29 +0200312
313/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
Wolfgang Denk08abe152005-07-21 15:23:29 +0200315
316/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
Wolfgang Denk08abe152005-07-21 15:23:29 +0200318
319/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_ATA_STRIDE 4
Wolfgang Denk08abe152005-07-21 15:23:29 +0200321
322#define CONFIG_ATAPI 1
323
Wolfgang Denkccd9d3d2005-09-03 01:21:50 +0200324#define CONFIG_VIDEO_SMI_LYNXEM
325#define CONFIG_CFB_CONSOLE
326#define CONFIG_VGA_AS_SINGLE_DEVICE
327#define CONFIG_VIDEO_LOGO
328
Wolfgang Denk98128f32005-08-16 15:17:53 +0200329/*
330 * PCI Mapping:
331 * 0x40000000 - 0x4fffffff - PCI Memory
332 * 0x50000000 - 0x50ffffff - PCI IO Space
333 */
334#define CONFIG_PCI 1
335#define CONFIG_PCI_PNP 1
336#define CONFIG_PCI_SCAN_SHOW 1
TsiChung Liewf33fca22008-03-30 01:19:06 -0500337#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
Wolfgang Denk98128f32005-08-16 15:17:53 +0200338
339#define CONFIG_PCI_MEM_BUS 0x40000000
340#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
341#define CONFIG_PCI_MEM_SIZE 0x10000000
342
343#define CONFIG_PCI_IO_BUS 0x50000000
344#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
345#define CONFIG_PCI_IO_SIZE 0x01000000
346
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS
Wolfgang Denkccd9d3d2005-09-03 01:21:50 +0200348
Wolfgang Denk9f96ae42005-08-30 13:04:12 +0200349/*---------------------------------------------------------------------*/
350/* Display addresses */
351/*---------------------------------------------------------------------*/
352
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
354#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
Wolfgang Denk9f96ae42005-08-30 13:04:12 +0200355
wdenka87589d2005-06-10 10:00:19 +0000356#endif /* __CONFIG_H */