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Wolfgang Denkeece1592005-08-10 11:03:05 +02001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2005
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 * (easy to change)
33 */
34
35#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
39#define CONFIG_STK52XX 1 /* ... on a STK52XX base board */
40#define CONFIG_STK52XX_REV100 1 /* define for revision 100 baseboards */
41
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
Wolfgang Denkeece1592005-08-10 11:03:05 +020043
44#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
45#define BOOTFLAG_WARM 0x02 /* Software reboot */
46
Becky Bruce31d82672008-05-08 19:02:12 -050047#define CONFIG_HIGH_BATS 1 /* High BATs supported */
48
Wolfgang Denkeece1592005-08-10 11:03:05 +020049/*
50 * Serial console configuration
51 */
52#define CONFIG_PSC_CONSOLE 6 /* console is on PSC6 */
53#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Wolfgang Denkeece1592005-08-10 11:03:05 +020055
56#ifdef CONFIG_STK52XX
57#undef CONFIG_PS2KBD /* AT-PS/2 Keyboard */
58#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
59#define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
Wolfgang Denkeece1592005-08-10 11:03:05 +020061#define CONFIG_BOARD_EARLY_INIT_R
62#endif /* CONFIG_STK52XX */
63
64/*
65 * PCI Mapping:
66 * 0x40000000 - 0x4fffffff - PCI Memory
67 * 0x50000000 - 0x50ffffff - PCI IO Space
68 */
69#ifdef CONFIG_STK52XX
70#define CONFIG_PCI 1
71#define CONFIG_PCI_PNP 1
72/* #define CONFIG_PCI_SCAN_SHOW 1 */
73
74#define CONFIG_PCI_MEM_BUS 0x40000000
75#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
76#define CONFIG_PCI_MEM_SIZE 0x10000000
77
78#define CONFIG_PCI_IO_BUS 0x50000000
79#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
80#define CONFIG_PCI_IO_SIZE 0x01000000
81
82#define CONFIG_NET_MULTI 1
83#define CONFIG_EEPRO100 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
Wolfgang Denkeece1592005-08-10 11:03:05 +020085#define CONFIG_NS8382X 1
86#endif /* CONFIG_STK52XX */
87
Wolfgang Denkeece1592005-08-10 11:03:05 +020088/*
89 * Video console
90 */
91#if 1
92#define CONFIG_VIDEO
93#define CONFIG_VIDEO_SM501
94#define CONFIG_VIDEO_SM501_32BPP
95#define CONFIG_CFB_CONSOLE
96#define CONFIG_VIDEO_LOGO
97#define CONFIG_VGA_AS_SINGLE_DEVICE
98#define CONFIG_CONSOLE_EXTRA_INFO
99#define CONFIG_VIDEO_SW_CURSOR
100#define CONFIG_SPLASH_SCREEN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Wolfgang Denkeece1592005-08-10 11:03:05 +0200102#endif
103
Wolfgang Denkeece1592005-08-10 11:03:05 +0200104/* Partitions */
105#define CONFIG_MAC_PARTITION
106#define CONFIG_DOS_PARTITION
107#define CONFIG_ISO_PARTITION
108
109/* USB */
110#ifdef CONFIG_STK52XX
111#define CONFIG_USB_OHCI
Wolfgang Denkeece1592005-08-10 11:03:05 +0200112#define CONFIG_USB_STORAGE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200113#endif
114
115/* POST support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
117 CONFIG_SYS_POST_CPU | \
118 CONFIG_SYS_POST_I2C)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200119
120#ifdef CONFIG_POST
Wolfgang Denkeece1592005-08-10 11:03:05 +0200121/* preserve space for the post_word at end of on-chip SRAM */
122#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
Wolfgang Denkeece1592005-08-10 11:03:05 +0200123#endif
124
Wolfgang Denkeece1592005-08-10 11:03:05 +0200125
126/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500127 * BOOTP options
128 */
129#define CONFIG_BOOTP_BOOTFILESIZE
130#define CONFIG_BOOTP_BOOTPATH
131#define CONFIG_BOOTP_GATEWAY
132#define CONFIG_BOOTP_HOSTNAME
133
134
135/*
Jon Loeliger46da1e92007-07-04 22:33:30 -0500136 * Command line configuration.
Wolfgang Denkeece1592005-08-10 11:03:05 +0200137 */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500138#include <config_cmd_default.h>
Wolfgang Denkeece1592005-08-10 11:03:05 +0200139
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500140#define CONFIG_CMD_ASKENV
141#define CONFIG_CMD_DATE
142#define CONFIG_CMD_DHCP
143#define CONFIG_CMD_ECHO
144#define CONFIG_CMD_EEPROM
145#define CONFIG_CMD_I2C
146#define CONFIG_CMD_MII
147#define CONFIG_CMD_NFS
148#define CONFIG_CMD_PING
149#define CONFIG_CMD_REGINFO
150#define CONFIG_CMD_SNTP
151
Jon Loeliger46da1e92007-07-04 22:33:30 -0500152#if defined(CONFIG_MINIFAP) || defined(CONFIG_STK52XX)
153 #define CONFIG_CMD_IDE
154 #define CONFIG_CMD_FAT
155 #define CONFIG_CMD_EXT2
156#endif
157
158#ifdef CONFIG_STK52XX
159 #define CONFIG_CMD_USB
160 #define CONFIG_CMD_FAT
161#endif
162
163#ifdef CONFIG_VIDEO
164 #define CONFIG_CMD_BMP
165#endif
166
167#ifdef CONFIG_PCI
168 #define CONFIG_CMD_PCI
TsiChung Liewf33fca22008-03-30 01:19:06 -0500169 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
Jon Loeliger46da1e92007-07-04 22:33:30 -0500170#endif
171
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500172#ifdef CONFIG_POST
173#define CONFIG_CMD_DIAG
174#endif
Jon Loeliger46da1e92007-07-04 22:33:30 -0500175
Wolfgang Denkeece1592005-08-10 11:03:05 +0200176
177#define CONFIG_TIMESTAMP /* display image timestamps */
178
179#if (TEXT_BASE == 0xFC000000) /* Boot low */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180# define CONFIG_SYS_LOWBOOT 1
Wolfgang Denkeece1592005-08-10 11:03:05 +0200181#endif
182
183/*
184 * Autobooting
185 */
186#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
187
188#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100189 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200190 "echo"
191
192#undef CONFIG_BOOTARGS
193
Wolfgang Denkeece1592005-08-10 11:03:05 +0200194#define CONFIG_EXTRA_ENV_SETTINGS \
195 "netdev=eth0\0" \
196 "rootpath=/opt/eldk/ppc_6xx\0" \
197 "ramargs=setenv bootargs root=/dev/ram rw\0" \
198 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100199 "nfsroot=${serverip}:${rootpath}\0" \
200 "addip=setenv bootargs ${bootargs} " \
201 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
202 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200203 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100204 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200205 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100206 "bootm ${kernel_addr}\0" \
207 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200208 "bootfile=/tftpboot/tqm5200/uImage\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100209 "load=tftp 200000 ${u-boot}\0" \
Wolfgang Denkcd65a3d2006-06-16 16:11:34 +0200210 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200211 "update=protect off FC000000 FC05FFFF;" \
212 "erase FC000000 FC05FFFF;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100213 "cp.b 200000 FC000000 ${filesize};" \
Wolfgang Denkeece1592005-08-10 11:03:05 +0200214 "protect on FC000000 FC05FFFF\0" \
215 ""
216
217#define CONFIG_BOOTCOMMAND "run net_nfs"
218
219/*
220 * IPB Bus clocking configuration.
221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200225/*
226 * PCI Bus clocking configuration
227 *
228 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229 * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200230 * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
Wolfgang Denkeece1592005-08-10 11:03:05 +0200231 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200233#endif
234
235/*
236 * I2C configuration
237 */
238#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
239#ifdef CONFIG_TQM5200_REV100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200241#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200243#endif
244
245/*
246 * I2C clock frequency
247 *
248 * Please notice, that the resulting clock frequency could differ from the
249 * configured value. This is because the I2C clock is derived from system
250 * clock over a frequency divider with only a few divider values. U-boot
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251 * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
Wolfgang Denkeece1592005-08-10 11:03:05 +0200252 * approximation allways lies below the configured value, never above.
253 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
255#define CONFIG_SYS_I2C_SLAVE 0x7F
Wolfgang Denkeece1592005-08-10 11:03:05 +0200256
257/*
258 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
259 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
260 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
261 * same configuration could be used.
262 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
264#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
265#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
266#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
Wolfgang Denkeece1592005-08-10 11:03:05 +0200267
268/*
269 * HW-Monitor configuration on Mini-FAP
270 */
271#if defined (CONFIG_MINIFAP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_I2C_HWMON_ADDR 0x2C
Wolfgang Denkeece1592005-08-10 11:03:05 +0200273#endif
274
275/* List of I2C addresses to be verified by POST */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200276#if defined (CONFIG_MINIFAP)
277#undef I2C_ADDR_LIST
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define I2C_ADDR_LIST { CONFIG_SYS_I2C_EEPROM_ADDR, \
279 CONFIG_SYS_I2C_HWMON_ADDR, \
280 CONFIG_SYS_I2C_SLAVE }
Wolfgang Denkeece1592005-08-10 11:03:05 +0200281#endif
282
283/*
284 * Flash configuration
285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_FLASH_BASE TEXT_BASE /* 0xFC000000 */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200287
288/* use CFI flash driver if no module variant is spezified */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200290#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
292#define CONFIG_SYS_FLASH_EMPTY_INFO
293#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
294#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
295#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#if !defined(CONFIG_SYS_LOWBOOT)
298#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
299#else /* CONFIG_SYS_LOWBOOT */
300#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
301#endif /* CONFIG_SYS_LOWBOOT */
302#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
Wolfgang Denkeece1592005-08-10 11:03:05 +0200303 (= chip selects) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
305#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200306
307
308/*
309 * Environment settings
310 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200311#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200312#define CONFIG_ENV_SIZE 0x10000
313#define CONFIG_ENV_SECT_SIZE 0x20000
314#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
315#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200316
317/*
318 * Memory map
319 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_MBAR 0xF0000000
321#define CONFIG_SYS_SDRAM_BASE 0x00000000
322#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
Wolfgang Denkeece1592005-08-10 11:03:05 +0200323
324/* Use ON-Chip SRAM until RAM will be available */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
Wolfgang Denkeece1592005-08-10 11:03:05 +0200326#ifdef CONFIG_POST
327/* preserve space for the post_word at end of on-chip SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200329#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200330#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200331#endif
332
333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
335#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
336#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denkeece1592005-08-10 11:03:05 +0200337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
339#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
340# define CONFIG_SYS_RAMBOOT 1
Wolfgang Denkeece1592005-08-10 11:03:05 +0200341#endif
342
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
344#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
345#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200346
347/*
348 * Ethernet configuration
349 */
350#define CONFIG_MPC5xxx_FEC 1
351/*
352 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
353 */
354/* #define CONFIG_FEC_10MBIT 1 */
355#define CONFIG_PHY_ADDR 0x00
356
357/*
358 * GPIO configuration
359 *
360 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
361 * Bit 0 (mask: 0x80000000): 1
362 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
363 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
364 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
365 * Use for REV200 STK52XX boards. Do not use with REV100 modules
366 * (because, there I2C1 is used as I2C bus)
367 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
368 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
369 * 000 -> All PSC2 pins are GIOPs
370 * 001 -> CAN1/2 on PSC2 pins
371 * Use for REV100 STK52xx boards
372 * use PSC6:
373 * on STK52xx:
374 * use as UART. Pins PSC6_0 to PSC6_3 are used.
375 * Bits 9:11 (mask: 0x00700000):
376 * 101 -> PSC6 : Extended POST test is not available
377 * on MINI-FAP and TQM5200_IB:
378 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
379 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
380 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
381 * tests.
382 */
383#if defined (CONFIG_MINIFAP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200384# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004
Wolfgang Denkeece1592005-08-10 11:03:05 +0200385#elif defined (CONFIG_STK52XX)
386# if defined (CONFIG_STK52XX_REV100)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200387# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014
Wolfgang Denkeece1592005-08-10 11:03:05 +0200388# else /* STK52xx REV200 and above */
389# if defined (CONFIG_TQM5200_REV100)
390# error TQM5200 REV100 not supported on STK52XX REV200 or above
391# else/* TQM5200 REV200 and above */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500004
Wolfgang Denkeece1592005-08-10 11:03:05 +0200393# endif
394# endif
395#else /* TMQ5200 Inbetriebnahme-Board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004
Wolfgang Denkeece1592005-08-10 11:03:05 +0200397#endif
398
399/*
400 * RTC configuration
401 */
402#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
403
404/*
405 * Miscellaneous configurable options
406 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_LONGHELP /* undef to save memory */
408#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500409#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200410#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200411#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200413#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
415#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
416#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200417
418/* Enable an alternate, more extensive memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_ALT_MEMTEST
Wolfgang Denkeece1592005-08-10 11:03:05 +0200420
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
422#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200423
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200425
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200427
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500429#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200430# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500431#endif
432
Wolfgang Denkeece1592005-08-10 11:03:05 +0200433/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500434 * Enable loopw command.
Wolfgang Denkeece1592005-08-10 11:03:05 +0200435 */
436#define CONFIG_LOOPW
437
438/*
439 * Various low-level settings
440 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
442#define CONFIG_SYS_HID0_FINAL HID0_ICE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200443
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
445#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
446#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
447#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200448#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200450#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
452#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
Wolfgang Denkeece1592005-08-10 11:03:05 +0200453
Wolfgang Denkeece1592005-08-10 11:03:05 +0200454#define CONFIG_LAST_STAGE_INIT
Wolfgang Denkeece1592005-08-10 11:03:05 +0200455
456/*
457 * SRAM - Do not map below 2 GB in address space, because this area is used
458 * for SDRAM autosizing.
459 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_CS2_START 0xE5000000
461#define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
462#define CONFIG_SYS_CS2_CFG 0x0004D930
Wolfgang Denkeece1592005-08-10 11:03:05 +0200463
464/*
465 * Grafic controller - Do not map below 2 GB in address space, because this
466 * area is used for SDRAM autosizing.
467 */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200468#define SM501_FB_BASE 0xE0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#define CONFIG_SYS_CS1_START (SM501_FB_BASE)
470#define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
471#define CONFIG_SYS_CS1_CFG 0x8F48FF70
472#define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
Wolfgang Denkeece1592005-08-10 11:03:05 +0200473
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_CS_BURST 0x00000000
475#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200476
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Wolfgang Denkeece1592005-08-10 11:03:05 +0200478
479/*-----------------------------------------------------------------------
480 * USB stuff
481 *-----------------------------------------------------------------------
482 */
483#define CONFIG_USB_CLOCK 0x0001BBBB
484#define CONFIG_USB_CONFIG 0x00001000
485
486/*-----------------------------------------------------------------------
487 * IDE/ATA stuff Supports IDE harddisk
488 *-----------------------------------------------------------------------
489 */
490
491#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
492
493#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
494#undef CONFIG_IDE_LED /* LED for ide not supported */
495
496#define CONFIG_IDE_RESET /* reset for ide supported */
497#define CONFIG_IDE_PREINIT
498
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
500#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
Wolfgang Denkeece1592005-08-10 11:03:05 +0200501
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200502#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Wolfgang Denkeece1592005-08-10 11:03:05 +0200503
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
Wolfgang Denkeece1592005-08-10 11:03:05 +0200505
506/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200508
509/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200510#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200511
512/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
Wolfgang Denkeece1592005-08-10 11:03:05 +0200514
515/* Interval between registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200516#define CONFIG_SYS_ATA_STRIDE 4
Wolfgang Denkeece1592005-08-10 11:03:05 +0200517
518#endif /* __CONFIG_H */