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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocher67fa8c22010-02-22 16:43:02 +05302/*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Prafulla Wadaskar <prafulla@marvell.com>
6 *
7 * (C) Copyright 2009
8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 *
Holger Brunck8170aef2012-07-05 05:37:46 +000010 * (C) Copyright 2011-2012
11 * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
12 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
Heiko Schocher67fa8c22010-02-22 16:43:02 +053013 */
14
15/*
16 * for linking errors see
17 * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
18 */
19
Holger Brunck83b40c32011-06-16 18:11:15 +053020#ifndef _CONFIG_KM_KIRKWOOD_H
21#define _CONFIG_KM_KIRKWOOD_H
Heiko Schocher67fa8c22010-02-22 16:43:02 +053022
Holger Brunck48ced622012-07-05 05:05:06 +000023/* KM_KIRKWOOD */
Holger Brunck8170aef2012-07-05 05:37:46 +000024#if defined(CONFIG_KM_KIRKWOOD)
Mario Six5bc05432018-03-28 14:38:20 +020025#define CONFIG_HOSTNAME "km_kirkwood"
Holger Brunck48ced622012-07-05 05:05:06 +000026#define CONFIG_KM_DISABLE_PCIE
Holger Brunck48ced622012-07-05 05:05:06 +000027
28/* KM_KIRKWOOD_PCI */
Holger Brunck8170aef2012-07-05 05:37:46 +000029#elif defined(CONFIG_KM_KIRKWOOD_PCI)
Mario Six5bc05432018-03-28 14:38:20 +020030#define CONFIG_HOSTNAME "km_kirkwood_pci"
Holger Brunck58c90c82014-08-15 10:51:48 +020031#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
32#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Holger Brunck48ced622012-07-05 05:05:06 +000033
Karlheinz Jerg5e4eeab2013-09-18 09:32:48 +020034/* KM_KIRKWOOD_128M16 */
35#elif defined(CONFIG_KM_KIRKWOOD_128M16)
Mario Six5bc05432018-03-28 14:38:20 +020036#define CONFIG_HOSTNAME "km_kirkwood_128m16"
Karlheinz Jerg5e4eeab2013-09-18 09:32:48 +020037#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamada4ab3fc52014-03-11 11:05:17 +090038#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
Karlheinz Jerg5e4eeab2013-09-18 09:32:48 +020039#define CONFIG_KM_DISABLE_PCIE
Karlheinz Jerg5e4eeab2013-09-18 09:32:48 +020040
Gerlando Falauto9c134e12014-02-13 16:43:00 +010041/* KM_NUSA / KM_SUGP1 */
42#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1)
Gerlando Falauto9c134e12014-02-13 16:43:00 +010043
44# if defined(CONFIG_KM_NUSA)
Mario Six5bc05432018-03-28 14:38:20 +020045#define CONFIG_HOSTNAME "kmnusa"
Gerlando Falauto9c134e12014-02-13 16:43:00 +010046# elif defined(CONFIG_KM_SUGP1)
Mario Six5bc05432018-03-28 14:38:20 +020047#define CONFIG_HOSTNAME "kmsugp1"
Gerlando Falauto9c134e12014-02-13 16:43:00 +010048#define KM_PCIE_RESET_MPP7
49#endif
50
Holger Brunck8170aef2012-07-05 05:37:46 +000051#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamada4ab3fc52014-03-11 11:05:17 +090052#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
Holger Brunck8170aef2012-07-05 05:37:46 +000053
Holger Brunckf9454392012-07-05 05:05:03 +000054/* KMCOGE5UN */
Holger Brunckd9354532012-07-05 05:05:02 +000055#elif defined(CONFIG_KM_COGE5UN)
Holger Brunckd9354532012-07-05 05:05:02 +000056#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamada4ab3fc52014-03-11 11:05:17 +090057#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
Mario Six5bc05432018-03-28 14:38:20 +020058#define CONFIG_HOSTNAME "kmcoge5un"
Holger Brunckd9354532012-07-05 05:05:02 +000059#define CONFIG_KM_DISABLE_PCIE
Holger Brunck6ef64862012-07-05 05:05:04 +000060
Holger Brunck90639fe2013-01-15 22:51:22 +000061/* KM_SUV31 */
62#elif defined(CONFIG_KM_SUV31)
Mario Six5bc05432018-03-28 14:38:20 +020063#define CONFIG_HOSTNAME "kmsuv31"
Holger Brunck2a4ebef2014-01-27 16:58:24 +010064#undef CONFIG_SYS_KWD_CONFIG
Masahiro Yamada4ab3fc52014-03-11 11:05:17 +090065#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
Holger Brunck58c90c82014-08-15 10:51:48 +020066#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
67#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Holger Brunck0e1c0f32020-01-13 15:34:01 +010068
69/* KM_SUSE2 */
70#elif defined(CONFIG_KM_SUSE2)
71#define CONFIG_HOSTNAME "kmsuse2"
72#undef CONFIG_SYS_KWD_CONFIG
73#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
74#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
75#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Holger Brunck8170aef2012-07-05 05:37:46 +000076#else
77#error ("Board unsupported")
78#endif
79
Heiko Schocher67fa8c22010-02-22 16:43:02 +053080/* include common defines/options for all arm based Keymile boards */
Valentin Longchamp264eaa02011-05-04 01:47:33 +000081#include "km/km_arm.h"
Heiko Schocher67fa8c22010-02-22 16:43:02 +053082
Holger Brunck8170aef2012-07-05 05:37:46 +000083#if defined(CONFIG_KM_PIGGY4_88E6352)
84/*
85 * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
86 * an Marvell 88E6352 simple switch.
87 * In this case we have to change the default settings for the etherent mac.
88 * There is NO ethernet phy. The ARM and Switch are conencted directly over
89 * RGMII in MAC-MAC mode
90 * In this case 1GBit full duplex and autoneg off
91 */
92#define PORT_SERIAL_CONTROL_VALUE ( \
93 MVGBE_FORCE_LINK_PASS | \
94 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
95 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
96 MVGBE_ADV_NO_FLOW_CTRL | \
97 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
98 MVGBE_FORCE_BP_MODE_NO_JAM | \
99 (1 << 9) /* Reserved bit has to be 1 */ | \
100 MVGBE_DO_NOT_FORCE_LINK_FAIL | \
101 MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
102 MVGBE_DTE_ADV_0 | \
103 MVGBE_MIIPHY_MAC_MODE | \
104 MVGBE_AUTO_NEG_NO_CHANGE | \
105 MVGBE_MAX_RX_PACKET_1552BYTE | \
106 MVGBE_CLR_EXT_LOOPBACK | \
107 MVGBE_SET_FULL_DUPLEX_MODE | \
108 MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
109 MVGBE_SET_GMII_SPEED_TO_1000 |\
110 MVGBE_SET_MII_SPEED_TO_100)
111
112#endif
Heiko Schocher731b9682011-03-08 10:53:51 +0100113
Holger Brunckf9454392012-07-05 05:05:03 +0000114#ifdef CONFIG_KM_PIGGY4_88E6061
115/*
Holger Bruncke7fdb342019-11-25 17:24:15 +0100116 * Some keymile boards like mgcoge5un have their PIGGY4 connected via
Holger Brunckf9454392012-07-05 05:05:03 +0000117 * an Marvell 88E6061 simple switch.
118 * In this case we have to change the default settings for the
119 * ethernet phy connected to the kirkwood.
120 * In this case 100MB full duplex and autoneg off
121 */
122#define PORT_SERIAL_CONTROL_VALUE ( \
123 MVGBE_FORCE_LINK_PASS | \
124 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
125 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
126 MVGBE_ADV_NO_FLOW_CTRL | \
127 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
128 MVGBE_FORCE_BP_MODE_NO_JAM | \
129 (1 << 9) /* Reserved bit has to be 1 */ | \
130 MVGBE_DO_NOT_FORCE_LINK_FAIL | \
131 MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
132 MVGBE_DTE_ADV_0 | \
133 MVGBE_MIIPHY_MAC_MODE | \
134 MVGBE_AUTO_NEG_NO_CHANGE | \
135 MVGBE_MAX_RX_PACKET_1552BYTE | \
136 MVGBE_CLR_EXT_LOOPBACK | \
137 MVGBE_SET_FULL_DUPLEX_MODE | \
138 MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
139 MVGBE_SET_GMII_SPEED_TO_10_100 |\
140 MVGBE_SET_MII_SPEED_TO_100)
141#endif
142
Pascal Linder9db6bff2019-07-09 09:28:23 +0200143#ifdef CONFIG_KM_DISABLE_PCIE
Holger Brunckf9454392012-07-05 05:05:03 +0000144#undef CONFIG_KIRKWOOD_PCIE_INIT
145#endif
Valentin Longchampb37f7722012-07-05 05:05:05 +0000146
Holger Brunck83b40c32011-06-16 18:11:15 +0530147#endif /* _CONFIG_KM_KIRKWOOD */