blob: d336e55c5d4493c8468080e0d22d01e1430f9353 [file] [log] [blame]
Dirk Eibach6e9e6c32012-04-26 03:54:22 +00001/*
2 * (C) Copyright 2011
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
26#include <asm/processor.h>
27#include <asm/io.h>
28#include <asm/ppc4xx-gpio.h>
29#include <dtt.h>
30
31#include "405ep.h"
32#include <gdsys_fpga.h>
33
34#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
35#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
36#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
37
38enum {
39 UNITTYPE_CCX16 = 1,
40 UNITTYPE_CCIP216 = 2,
41};
42
43enum {
44 HWVER_300 = 3,
45};
46
47int misc_init_r(void)
48{
49 /* startup fans */
50 dtt_init();
51
52 return 0;
53}
54
55int checkboard(void)
56{
57 char *s = getenv("serial#");
58
59 puts("Board: CATCenter Neo");
60
61 if (s != NULL) {
62 puts(", serial# ");
63 puts(s);
64 }
65
66 puts("\n");
67
68 return 0;
69}
70
71static void print_fpga_info(void)
72{
Dirk Eibach0e60aa82012-04-27 10:33:46 +020073 struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000074 u16 versions = in_le16(&fpga->versions);
75 u16 fpga_version = in_le16(&fpga->fpga_version);
76 u16 fpga_features = in_le16(&fpga->fpga_features);
77 int fpga_state = get_fpga_state(0);
78 unsigned unit_type;
79 unsigned hardware_version;
80 unsigned feature_channels;
81
82 puts("FPGA: ");
83 if (fpga_state & FPGA_STATE_DONE_FAILED) {
84 printf(" done timed out\n");
85 return;
86 }
87
88 if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
89 printf(" refelectione test failed\n");
90 return;
91 }
92
93 unit_type = (versions & 0xf000) >> 12;
94 hardware_version = versions & 0x000f;
95 feature_channels = fpga_features & 0x007f;
96
97 switch (unit_type) {
98 case UNITTYPE_CCX16:
99 printf("CCX-Switch");
100 break;
101
102 default:
103 printf("UnitType %d(not supported)", unit_type);
104 break;
105 }
106
107 switch (hardware_version) {
108 case HWVER_300:
109 printf(" HW-Ver 3.00-3.12\n");
110 break;
111
112 default:
113 printf(" HW-Ver %d(not supported)\n",
114 hardware_version);
115 break;
116 }
117
118 printf(" FPGA V %d.%02d, features:",
119 fpga_version / 100, fpga_version % 100);
120
121 printf(" %d channel(s)\n", feature_channels);
122}
123
124int last_stage_init(void)
125{
126 print_fpga_info();
127
128 return 0;
129}
130
131void gd405ep_init(void)
132{
133}
134
135void gd405ep_set_fpga_reset(unsigned state)
136{
137 if (state) {
138 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
139 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
140 } else {
141 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
142 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
143 }
144}
145
146void gd405ep_setup_hw(void)
147{
148 /*
149 * set "startup-finished"-gpios
150 */
151 gpio_write_bit(21, 0);
152 gpio_write_bit(22, 1);
153}
154
155int gd405ep_get_fpga_done(unsigned fpga)
156{
157 /*
158 * Neo hardware has no FPGA-DONE GPIO
159 */
160 return 1;
161}