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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +09002
3#include <common.h>
4#include <asm/processor.h>
Nobuhiro Iwamatsu754613f2010-06-16 16:55:26 +09005#include <asm/system.h>
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +09006#include <asm/io.h>
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +09007
8#define WDT_BASE WTCNT
9
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +090010#define WDT_WD (1 << 6)
11#define WDT_RST_P (0)
12#define WDT_RST_M (1 << 5)
13#define WDT_ENABLE (1 << 7)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +090014
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +090015#if defined(CONFIG_WATCHDOG)
16static unsigned char csr_read(void)
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +090017{
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +090018 return inb(WDT_BASE + 0x04);
19}
20
21static void cnt_write(unsigned char value)
22{
23 outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
24}
25
26static void csr_write(unsigned char value)
27{
28 outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
29}
30
31void watchdog_reset(void)
32{
33 outl(0x55000000, WDT_BASE + 0x08);
34}
35
36int watchdog_init(void)
37{
38 /* Set overflow time*/
39 cnt_write(0);
40 /* Power on reset */
41 csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
42
43 return 0;
44}
45
46int watchdog_disable(void)
47{
48 csr_write(csr_read() & ~WDT_ENABLE);
49 return 0;
50}
51#endif
52
53void reset_cpu(unsigned long ignored)
54{
Nobuhiro Iwamatsu754613f2010-06-16 16:55:26 +090055 /* Address error with SR.BL=1 first. */
56 trigger_address_error();
57
Nobuhiro Iwamatsu4a065ab2008-09-18 19:04:26 +090058 while (1)
59 ;
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +090060}