blob: d89e71c16a04900a9adbc7ae092e080dd3d280f1 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00002/*
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
wdenkc6097192002-11-03 00:24:07 +00009 */
10
11/*
12 * PCI routines
13 */
14
15#include <common.h>
Simon Glass0098e172014-04-10 20:01:30 -060016#include <bootretry.h>
Simon Glass18d66532014-04-10 20:01:25 -060017#include <cli.h>
wdenkc6097192002-11-03 00:24:07 +000018#include <command.h>
Simon Glass24b852a2015-11-08 23:47:45 -070019#include <console.h>
Simon Glasscab24b32015-11-26 19:51:29 -070020#include <dm.h>
Simon Glass691d7192020-05-10 11:40:02 -060021#include <init.h>
wdenkc6097192002-11-03 00:24:07 +000022#include <asm/processor.h>
23#include <asm/io.h>
wdenkc6097192002-11-03 00:24:07 +000024#include <pci.h>
25
Simon Glass07a58872015-11-26 19:51:20 -070026struct pci_reg_info {
27 const char *name;
28 enum pci_size_t size;
29 u8 offset;
30};
31
Simon Glass72ef5b62015-11-26 19:51:26 -070032static int pci_byte_size(enum pci_size_t size)
Simon Glass07a58872015-11-26 19:51:20 -070033{
34 switch (size) {
35 case PCI_SIZE_8:
Simon Glass72ef5b62015-11-26 19:51:26 -070036 return 1;
Simon Glass07a58872015-11-26 19:51:20 -070037 case PCI_SIZE_16:
Simon Glass72ef5b62015-11-26 19:51:26 -070038 return 2;
Simon Glass07a58872015-11-26 19:51:20 -070039 case PCI_SIZE_32:
40 default:
Simon Glass72ef5b62015-11-26 19:51:26 -070041 return 4;
Simon Glass07a58872015-11-26 19:51:20 -070042 }
43}
44
Simon Glass72ef5b62015-11-26 19:51:26 -070045static int pci_field_width(enum pci_size_t size)
46{
47 return pci_byte_size(size) * 2;
48}
49
Simon Glasscab24b32015-11-26 19:51:29 -070050static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
51{
52 for (; regs->name; regs++) {
53 unsigned long val;
54
55 dm_pci_read_config(dev, regs->offset, &val, regs->size);
56 printf(" %s =%*s%#.*lx\n", regs->name,
57 (int)(28 - strlen(regs->name)), "",
58 pci_field_width(regs->size), val);
59 }
60}
Simon Glass07a58872015-11-26 19:51:20 -070061
Vladimir Olteanf5164f62021-09-17 15:11:22 +030062static int pci_bar_show(struct udevice *dev)
Yehuda Yitschake5f96a82016-12-01 17:14:18 +020063{
64 u8 header_type;
65 int bar_cnt, bar_id, mem_type;
66 bool is_64, is_io;
67 u32 base_low, base_high;
68 u32 size_low, size_high;
69 u64 base, size;
70 u32 reg_addr;
71 int prefetchable;
72
73 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
Pali Roháre6335d32021-10-07 14:51:00 +020074 header_type &= 0x7f;
Yehuda Yitschake5f96a82016-12-01 17:14:18 +020075
76 if (header_type == PCI_HEADER_TYPE_CARDBUS) {
77 printf("CardBus doesn't support BARs\n");
78 return -ENOSYS;
Pali Roháre6335d32021-10-07 14:51:00 +020079 } else if (header_type != PCI_HEADER_TYPE_NORMAL &&
80 header_type != PCI_HEADER_TYPE_BRIDGE) {
81 printf("unknown header type\n");
82 return -ENOSYS;
Yehuda Yitschake5f96a82016-12-01 17:14:18 +020083 }
84
85 bar_cnt = (header_type == PCI_HEADER_TYPE_NORMAL) ? 6 : 2;
86
87 printf("ID Base Size Width Type\n");
88 printf("----------------------------------------------------------\n");
89
90 bar_id = 0;
91 reg_addr = PCI_BASE_ADDRESS_0;
92 while (bar_cnt) {
93 dm_pci_read_config32(dev, reg_addr, &base_low);
94 dm_pci_write_config32(dev, reg_addr, 0xffffffff);
95 dm_pci_read_config32(dev, reg_addr, &size_low);
96 dm_pci_write_config32(dev, reg_addr, base_low);
97 reg_addr += 4;
98
99 base = base_low & ~0xf;
100 size = size_low & ~0xf;
101 base_high = 0x0;
102 size_high = 0xffffffff;
103 is_64 = 0;
104 prefetchable = base_low & PCI_BASE_ADDRESS_MEM_PREFETCH;
105 is_io = base_low & PCI_BASE_ADDRESS_SPACE_IO;
106 mem_type = base_low & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
107
108 if (mem_type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
109 dm_pci_read_config32(dev, reg_addr, &base_high);
110 dm_pci_write_config32(dev, reg_addr, 0xffffffff);
111 dm_pci_read_config32(dev, reg_addr, &size_high);
112 dm_pci_write_config32(dev, reg_addr, base_high);
113 bar_cnt--;
114 reg_addr += 4;
115 is_64 = 1;
116 }
117
118 base = base | ((u64)base_high << 32);
119 size = size | ((u64)size_high << 32);
120
121 if ((!is_64 && size_low) || (is_64 && size)) {
122 size = ~size + 1;
Kunihiko Hayashi4ebeb4c2019-08-23 10:56:55 +0900123 printf(" %d %#018llx %#018llx %d %s %s\n",
Simon Glass84d7f912017-05-27 07:38:12 -0600124 bar_id, (unsigned long long)base,
125 (unsigned long long)size, is_64 ? 64 : 32,
Yehuda Yitschake5f96a82016-12-01 17:14:18 +0200126 is_io ? "I/O" : "MEM",
127 prefetchable ? "Prefetchable" : "");
128 }
129
130 bar_id++;
131 bar_cnt--;
132 }
133
134 return 0;
135}
Yehuda Yitschake5f96a82016-12-01 17:14:18 +0200136
Simon Glass07a58872015-11-26 19:51:20 -0700137static struct pci_reg_info regs_start[] = {
138 { "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
139 { "device ID", PCI_SIZE_16, PCI_DEVICE_ID },
140 { "command register ID", PCI_SIZE_16, PCI_COMMAND },
141 { "status register", PCI_SIZE_16, PCI_STATUS },
142 { "revision ID", PCI_SIZE_8, PCI_REVISION_ID },
143 {},
144};
145
146static struct pci_reg_info regs_rest[] = {
147 { "sub class code", PCI_SIZE_8, PCI_CLASS_SUB_CODE },
148 { "programming interface", PCI_SIZE_8, PCI_CLASS_PROG },
149 { "cache line", PCI_SIZE_8, PCI_CACHE_LINE_SIZE },
150 { "latency time", PCI_SIZE_8, PCI_LATENCY_TIMER },
151 { "header type", PCI_SIZE_8, PCI_HEADER_TYPE },
152 { "BIST", PCI_SIZE_8, PCI_BIST },
153 { "base address 0", PCI_SIZE_32, PCI_BASE_ADDRESS_0 },
154 {},
155};
156
157static struct pci_reg_info regs_normal[] = {
158 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
159 { "base address 2", PCI_SIZE_32, PCI_BASE_ADDRESS_2 },
160 { "base address 3", PCI_SIZE_32, PCI_BASE_ADDRESS_3 },
161 { "base address 4", PCI_SIZE_32, PCI_BASE_ADDRESS_4 },
162 { "base address 5", PCI_SIZE_32, PCI_BASE_ADDRESS_5 },
163 { "cardBus CIS pointer", PCI_SIZE_32, PCI_CARDBUS_CIS },
164 { "sub system vendor ID", PCI_SIZE_16, PCI_SUBSYSTEM_VENDOR_ID },
165 { "sub system ID", PCI_SIZE_16, PCI_SUBSYSTEM_ID },
166 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS },
167 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
168 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
169 { "min Grant", PCI_SIZE_8, PCI_MIN_GNT },
170 { "max Latency", PCI_SIZE_8, PCI_MAX_LAT },
171 {},
172};
173
174static struct pci_reg_info regs_bridge[] = {
175 { "base address 1", PCI_SIZE_32, PCI_BASE_ADDRESS_1 },
176 { "primary bus number", PCI_SIZE_8, PCI_PRIMARY_BUS },
177 { "secondary bus number", PCI_SIZE_8, PCI_SECONDARY_BUS },
178 { "subordinate bus number", PCI_SIZE_8, PCI_SUBORDINATE_BUS },
179 { "secondary latency timer", PCI_SIZE_8, PCI_SEC_LATENCY_TIMER },
180 { "IO base", PCI_SIZE_8, PCI_IO_BASE },
181 { "IO limit", PCI_SIZE_8, PCI_IO_LIMIT },
182 { "secondary status", PCI_SIZE_16, PCI_SEC_STATUS },
183 { "memory base", PCI_SIZE_16, PCI_MEMORY_BASE },
184 { "memory limit", PCI_SIZE_16, PCI_MEMORY_LIMIT },
185 { "prefetch memory base", PCI_SIZE_16, PCI_PREF_MEMORY_BASE },
186 { "prefetch memory limit", PCI_SIZE_16, PCI_PREF_MEMORY_LIMIT },
187 { "prefetch memory base upper", PCI_SIZE_32, PCI_PREF_BASE_UPPER32 },
188 { "prefetch memory limit upper", PCI_SIZE_32, PCI_PREF_LIMIT_UPPER32 },
189 { "IO base upper 16 bits", PCI_SIZE_16, PCI_IO_BASE_UPPER16 },
190 { "IO limit upper 16 bits", PCI_SIZE_16, PCI_IO_LIMIT_UPPER16 },
191 { "expansion ROM base address", PCI_SIZE_32, PCI_ROM_ADDRESS1 },
192 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
193 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
194 { "bridge control", PCI_SIZE_16, PCI_BRIDGE_CONTROL },
195 {},
196};
197
198static struct pci_reg_info regs_cardbus[] = {
199 { "capabilities", PCI_SIZE_8, PCI_CB_CAPABILITY_LIST },
200 { "secondary status", PCI_SIZE_16, PCI_CB_SEC_STATUS },
201 { "primary bus number", PCI_SIZE_8, PCI_CB_PRIMARY_BUS },
202 { "CardBus number", PCI_SIZE_8, PCI_CB_CARD_BUS },
203 { "subordinate bus number", PCI_SIZE_8, PCI_CB_SUBORDINATE_BUS },
204 { "CardBus latency timer", PCI_SIZE_8, PCI_CB_LATENCY_TIMER },
205 { "CardBus memory base 0", PCI_SIZE_32, PCI_CB_MEMORY_BASE_0 },
206 { "CardBus memory limit 0", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_0 },
207 { "CardBus memory base 1", PCI_SIZE_32, PCI_CB_MEMORY_BASE_1 },
208 { "CardBus memory limit 1", PCI_SIZE_32, PCI_CB_MEMORY_LIMIT_1 },
209 { "CardBus IO base 0", PCI_SIZE_16, PCI_CB_IO_BASE_0 },
210 { "CardBus IO base high 0", PCI_SIZE_16, PCI_CB_IO_BASE_0_HI },
211 { "CardBus IO limit 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0 },
212 { "CardBus IO limit high 0", PCI_SIZE_16, PCI_CB_IO_LIMIT_0_HI },
213 { "CardBus IO base 1", PCI_SIZE_16, PCI_CB_IO_BASE_1 },
214 { "CardBus IO base high 1", PCI_SIZE_16, PCI_CB_IO_BASE_1_HI },
215 { "CardBus IO limit 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1 },
216 { "CardBus IO limit high 1", PCI_SIZE_16, PCI_CB_IO_LIMIT_1_HI },
217 { "interrupt line", PCI_SIZE_8, PCI_INTERRUPT_LINE },
218 { "interrupt pin", PCI_SIZE_8, PCI_INTERRUPT_PIN },
219 { "bridge control", PCI_SIZE_16, PCI_CB_BRIDGE_CONTROL },
220 { "subvendor ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_VENDOR_ID },
221 { "subdevice ID", PCI_SIZE_16, PCI_CB_SUBSYSTEM_ID },
222 { "PC Card 16bit base address", PCI_SIZE_32, PCI_CB_LEGACY_MODE_BASE },
223 {},
224};
225
Simon Glassc2be0702015-11-26 19:51:25 -0700226/**
227 * pci_header_show() - Show the header of the specified PCI device.
wdenkc6097192002-11-03 00:24:07 +0000228 *
Simon Glassc2be0702015-11-26 19:51:25 -0700229 * @dev: Bus+Device+Function number
wdenkc6097192002-11-03 00:24:07 +0000230 */
Vladimir Olteana95f8ee2021-09-17 15:11:23 +0300231static void pci_header_show(struct udevice *dev)
wdenkc6097192002-11-03 00:24:07 +0000232{
Simon Glasscab24b32015-11-26 19:51:29 -0700233 unsigned long class, header_type;
234
235 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
236 dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
Simon Glass07a58872015-11-26 19:51:20 -0700237 pci_show_regs(dev, regs_start);
Simon Glasscab24b32015-11-26 19:51:29 -0700238 printf(" class code = 0x%.2x (%s)\n", (int)class,
Simon Glass07a58872015-11-26 19:51:20 -0700239 pci_class_str(class));
240 pci_show_regs(dev, regs_rest);
wdenkc6097192002-11-03 00:24:07 +0000241
Pali Rohár43dad072021-10-07 14:51:01 +0200242 switch (header_type & 0x7f) {
wdenk7c7a23b2002-12-07 00:20:59 +0000243 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
Simon Glass07a58872015-11-26 19:51:20 -0700244 pci_show_regs(dev, regs_normal);
wdenk7c7a23b2002-12-07 00:20:59 +0000245 break;
wdenk7c7a23b2002-12-07 00:20:59 +0000246 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
Simon Glass07a58872015-11-26 19:51:20 -0700247 pci_show_regs(dev, regs_bridge);
wdenk7c7a23b2002-12-07 00:20:59 +0000248 break;
wdenk7c7a23b2002-12-07 00:20:59 +0000249 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
Simon Glass07a58872015-11-26 19:51:20 -0700250 pci_show_regs(dev, regs_cardbus);
wdenk7c7a23b2002-12-07 00:20:59 +0000251 break;
wdenk8bde7f72003-06-27 21:31:46 +0000252
wdenk7c7a23b2002-12-07 00:20:59 +0000253 default:
254 printf("unknown header\n");
wdenk8bde7f72003-06-27 21:31:46 +0000255 break;
wdenkc6097192002-11-03 00:24:07 +0000256 }
wdenkc6097192002-11-03 00:24:07 +0000257}
258
Pali Rohár1a4942f2022-01-17 16:38:40 +0100259static void pciinfo_header(bool short_listing)
Simon Glassc4f32bb2015-11-26 19:51:28 -0700260{
Simon Glassc4f32bb2015-11-26 19:51:28 -0700261 if (short_listing) {
262 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
263 printf("_____________________________________________________________\n");
264 }
265}
266
Simon Glasscab24b32015-11-26 19:51:29 -0700267/**
268 * pci_header_show_brief() - Show the short-form PCI device header
269 *
270 * Reads and prints the header of the specified PCI device in short form.
271 *
272 * @dev: PCI device to show
273 */
274static void pci_header_show_brief(struct udevice *dev)
275{
276 ulong vendor, device;
277 ulong class, subclass;
278
279 dm_pci_read_config(dev, PCI_VENDOR_ID, &vendor, PCI_SIZE_16);
280 dm_pci_read_config(dev, PCI_DEVICE_ID, &device, PCI_SIZE_16);
281 dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
282 dm_pci_read_config(dev, PCI_CLASS_SUB_CODE, &subclass, PCI_SIZE_8);
283
284 printf("0x%.4lx 0x%.4lx %-23s 0x%.2lx\n",
285 vendor, device,
286 pci_class_str(class), subclass);
287}
288
Pali Rohár1a4942f2022-01-17 16:38:40 +0100289static void pciinfo(struct udevice *bus, bool short_listing, bool multi)
Simon Glasscab24b32015-11-26 19:51:29 -0700290{
291 struct udevice *dev;
292
Pali Rohár1a4942f2022-01-17 16:38:40 +0100293 if (!multi)
294 printf("Scanning PCI devices on bus %d\n", dev_seq(bus));
295
296 if (!multi || dev_seq(bus) == 0)
297 pciinfo_header(short_listing);
Simon Glasscab24b32015-11-26 19:51:29 -0700298
299 for (device_find_first_child(bus, &dev);
300 dev;
301 device_find_next_child(&dev)) {
Simon Glass8a8d24b2020-12-03 16:55:23 -0700302 struct pci_child_plat *pplat;
Simon Glasscab24b32015-11-26 19:51:29 -0700303
Simon Glasscaa4daa2020-12-03 16:55:18 -0700304 pplat = dev_get_parent_plat(dev);
Simon Glasscab24b32015-11-26 19:51:29 -0700305 if (short_listing) {
Simon Glass8b85dfc2020-12-16 21:20:07 -0700306 printf("%02x.%02x.%02x ", dev_seq(bus),
Simon Glasscab24b32015-11-26 19:51:29 -0700307 PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
308 pci_header_show_brief(dev);
309 } else {
Simon Glass8b85dfc2020-12-16 21:20:07 -0700310 printf("\nFound PCI device %02x.%02x.%02x:\n",
311 dev_seq(bus),
Simon Glasscab24b32015-11-26 19:51:29 -0700312 PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn));
313 pci_header_show(dev);
314 }
315 }
316}
317
Simon Glassc2be0702015-11-26 19:51:25 -0700318/**
319 * get_pci_dev() - Convert the "bus.device.function" identifier into a number
320 *
321 * @name: Device string in the form "bus.device.function" where each is in hex
Heinrich Schuchardt185f8122022-01-19 18:05:50 +0100322 * Return: encoded pci_dev_t or -1 if the string was invalid
wdenkc6097192002-11-03 00:24:07 +0000323 */
Simon Glassc2be0702015-11-26 19:51:25 -0700324static pci_dev_t get_pci_dev(char *name)
wdenkc6097192002-11-03 00:24:07 +0000325{
326 char cnum[12];
327 int len, i, iold, n;
328 int bdfs[3] = {0,0,0};
329
330 len = strlen(name);
331 if (len > 8)
332 return -1;
333 for (i = 0, iold = 0, n = 0; i < len; i++) {
334 if (name[i] == '.') {
335 memcpy(cnum, &name[iold], i - iold);
336 cnum[i - iold] = '\0';
Simon Glass7e5f4602021-07-24 09:03:29 -0600337 bdfs[n++] = hextoul(cnum, NULL);
wdenkc6097192002-11-03 00:24:07 +0000338 iold = i + 1;
339 }
340 }
341 strcpy(cnum, &name[iold]);
342 if (n == 0)
343 n = 1;
Simon Glass7e5f4602021-07-24 09:03:29 -0600344 bdfs[n] = hextoul(cnum, NULL);
Simon Glassc2be0702015-11-26 19:51:25 -0700345
wdenkc6097192002-11-03 00:24:07 +0000346 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
347}
348
Simon Glasscab24b32015-11-26 19:51:29 -0700349static int pci_cfg_display(struct udevice *dev, ulong addr,
350 enum pci_size_t size, ulong length)
wdenkc6097192002-11-03 00:24:07 +0000351{
352#define DISP_LINE_LEN 16
353 ulong i, nbytes, linebytes;
Simon Glass72ef5b62015-11-26 19:51:26 -0700354 int byte_size;
wdenkc6097192002-11-03 00:24:07 +0000355 int rc = 0;
356
Simon Glass72ef5b62015-11-26 19:51:26 -0700357 byte_size = pci_byte_size(size);
wdenkc6097192002-11-03 00:24:07 +0000358 if (length == 0)
Simon Glass72ef5b62015-11-26 19:51:26 -0700359 length = 0x40 / byte_size; /* Standard PCI config space */
wdenkc6097192002-11-03 00:24:07 +0000360
Pali Rohárd9f554b2022-07-03 12:48:06 +0200361 if (addr >= 4096)
362 return 1;
363
wdenkc6097192002-11-03 00:24:07 +0000364 /* Print the lines.
365 * once, and all accesses are with the specified bus width.
366 */
Simon Glass72ef5b62015-11-26 19:51:26 -0700367 nbytes = length * byte_size;
wdenkc6097192002-11-03 00:24:07 +0000368 do {
wdenkc6097192002-11-03 00:24:07 +0000369 printf("%08lx:", addr);
Simon Glass72ef5b62015-11-26 19:51:26 -0700370 linebytes = (nbytes > DISP_LINE_LEN) ? DISP_LINE_LEN : nbytes;
371 for (i = 0; i < linebytes; i += byte_size) {
372 unsigned long val;
373
Simon Glasscab24b32015-11-26 19:51:29 -0700374 dm_pci_read_config(dev, addr, &val, size);
Simon Glass72ef5b62015-11-26 19:51:26 -0700375 printf(" %0*lx", pci_field_width(size), val);
376 addr += byte_size;
wdenkc6097192002-11-03 00:24:07 +0000377 }
378 printf("\n");
379 nbytes -= linebytes;
380 if (ctrlc()) {
381 rc = 1;
382 break;
383 }
Pali Rohárd9f554b2022-07-03 12:48:06 +0200384 } while (nbytes > 0 && addr < 4096);
385
386 if (rc == 0 && nbytes > 0)
387 return 1;
wdenkc6097192002-11-03 00:24:07 +0000388
389 return (rc);
390}
391
Simon Glasscab24b32015-11-26 19:51:29 -0700392static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
Simon Glass72ef5b62015-11-26 19:51:26 -0700393 ulong value, int incrflag)
wdenkc6097192002-11-03 00:24:07 +0000394{
395 ulong i;
396 int nbytes;
Simon Glass72ef5b62015-11-26 19:51:26 -0700397 ulong val;
wdenkc6097192002-11-03 00:24:07 +0000398
Pali Rohárd9f554b2022-07-03 12:48:06 +0200399 if (addr >= 4096)
400 return 1;
401
wdenkc6097192002-11-03 00:24:07 +0000402 /* Print the address, followed by value. Then accept input for
403 * the next value. A non-converted value exits.
404 */
405 do {
406 printf("%08lx:", addr);
Simon Glasscab24b32015-11-26 19:51:29 -0700407 dm_pci_read_config(dev, addr, &val, size);
Simon Glass72ef5b62015-11-26 19:51:26 -0700408 printf(" %0*lx", pci_field_width(size), val);
wdenkc6097192002-11-03 00:24:07 +0000409
Simon Glasse1bf8242014-04-10 20:01:27 -0600410 nbytes = cli_readline(" ? ");
wdenkc6097192002-11-03 00:24:07 +0000411 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
412 /* <CR> pressed as only input, don't modify current
413 * location and move to next. "-" pressed will go back.
414 */
415 if (incrflag)
416 addr += nbytes ? -size : size;
417 nbytes = 1;
Simon Glassb26440f2014-04-10 20:01:31 -0600418 /* good enough to not time out */
419 bootretry_reset_cmd_timeout();
wdenkc6097192002-11-03 00:24:07 +0000420 }
421#ifdef CONFIG_BOOT_RETRY_TIME
422 else if (nbytes == -2) {
423 break; /* timed out, exit the command */
424 }
425#endif
426 else {
427 char *endp;
Simon Glass7e5f4602021-07-24 09:03:29 -0600428 i = hextoul(console_buffer, &endp);
wdenkc6097192002-11-03 00:24:07 +0000429 nbytes = endp - console_buffer;
430 if (nbytes) {
wdenkc6097192002-11-03 00:24:07 +0000431 /* good enough to not time out
432 */
Simon Glassb26440f2014-04-10 20:01:31 -0600433 bootretry_reset_cmd_timeout();
Simon Glasscab24b32015-11-26 19:51:29 -0700434 dm_pci_write_config(dev, addr, i, size);
wdenkc6097192002-11-03 00:24:07 +0000435 if (incrflag)
436 addr += size;
437 }
438 }
Pali Rohárd9f554b2022-07-03 12:48:06 +0200439 } while (nbytes && addr < 4096);
440
441 if (nbytes)
442 return 1;
wdenkc6097192002-11-03 00:24:07 +0000443
444 return 0;
445}
446
Simon Glassb997a732017-04-08 13:10:06 -0600447static const struct pci_flag_info {
448 uint flag;
449 const char *name;
450} pci_flag_info[] = {
451 { PCI_REGION_IO, "io" },
452 { PCI_REGION_PREFETCH, "prefetch" },
453 { PCI_REGION_SYS_MEMORY, "sysmem" },
454 { PCI_REGION_RO, "readonly" },
Simon Glassb997a732017-04-08 13:10:06 -0600455};
456
457static void pci_show_regions(struct udevice *bus)
458{
Pali Rohár39320932022-01-17 16:38:38 +0100459 struct pci_controller *hose = dev_get_uclass_priv(pci_get_controller(bus));
Simon Glassb997a732017-04-08 13:10:06 -0600460 const struct pci_region *reg;
461 int i, j;
462
463 if (!hose) {
464 printf("Bus '%s' is not a PCI controller\n", bus->name);
465 return;
466 }
467
Pali Rohár39320932022-01-17 16:38:38 +0100468 printf("Buses %02x-%02x\n", hose->first_busno, hose->last_busno);
Kunihiko Hayashi4ebeb4c2019-08-23 10:56:55 +0900469 printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size",
Simon Glassb997a732017-04-08 13:10:06 -0600470 "Flags");
471 for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
Kunihiko Hayashi4ebeb4c2019-08-23 10:56:55 +0900472 printf("%d %#018llx %#018llx %#018llx ", i,
Simon Glassb997a732017-04-08 13:10:06 -0600473 (unsigned long long)reg->bus_start,
474 (unsigned long long)reg->phys_start,
475 (unsigned long long)reg->size);
476 if (!(reg->flags & PCI_REGION_TYPE))
477 printf("mem ");
478 for (j = 0; j < ARRAY_SIZE(pci_flag_info); j++) {
479 if (reg->flags & pci_flag_info[j].flag)
480 printf("%s ", pci_flag_info[j].name);
481 }
482 printf("\n");
483 }
484}
Simon Glassb997a732017-04-08 13:10:06 -0600485
wdenkc6097192002-11-03 00:24:07 +0000486/* PCI Configuration Space access commands
487 *
488 * Syntax:
489 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
490 * pci next[.b, .w, .l] bus.device.function [addr]
491 * pci modify[.b, .w, .l] bus.device.function [addr]
492 * pci write[.b, .w, .l] bus.device.function addr value
493 */
Simon Glass09140112020-05-10 11:40:03 -0600494static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
wdenkc6097192002-11-03 00:24:07 +0000495{
Simon Glass72ef5b62015-11-26 19:51:26 -0700496 ulong addr = 0, value = 0, cmd_size = 0;
497 enum pci_size_t size = PCI_SIZE_32;
Simon Glasscab24b32015-11-26 19:51:29 -0700498 struct udevice *dev, *bus;
Pali Rohár1a4942f2022-01-17 16:38:40 +0100499 int busnum = -1;
wdenkc6097192002-11-03 00:24:07 +0000500 pci_dev_t bdf = 0;
501 char cmd = 's';
Simon Glassbfa41912015-11-26 19:51:18 -0700502 int ret = 0;
Pali Rohár1a4942f2022-01-17 16:38:40 +0100503 char *endp;
wdenkc6097192002-11-03 00:24:07 +0000504
505 if (argc > 1)
506 cmd = argv[1][0];
507
508 switch (cmd) {
509 case 'd': /* display */
510 case 'n': /* next */
511 case 'm': /* modify */
512 case 'w': /* write */
513 /* Check for a size specification. */
Simon Glass72ef5b62015-11-26 19:51:26 -0700514 cmd_size = cmd_get_data_size(argv[1], 4);
515 size = (cmd_size == 4) ? PCI_SIZE_32 : cmd_size - 1;
wdenkc6097192002-11-03 00:24:07 +0000516 if (argc > 3)
Simon Glass7e5f4602021-07-24 09:03:29 -0600517 addr = hextoul(argv[3], NULL);
wdenkc6097192002-11-03 00:24:07 +0000518 if (argc > 4)
Simon Glass7e5f4602021-07-24 09:03:29 -0600519 value = hextoul(argv[4], NULL);
Heinrich Schuchardt62d92d82023-04-01 09:43:33 +0200520 fallthrough;
wdenkc6097192002-11-03 00:24:07 +0000521 case 'h': /* header */
Yehuda Yitschake5f96a82016-12-01 17:14:18 +0200522 case 'b': /* bars */
wdenkc6097192002-11-03 00:24:07 +0000523 if (argc < 3)
524 goto usage;
525 if ((bdf = get_pci_dev(argv[2])) == -1)
526 return 1;
527 break;
John Schmoller96d61602010-10-22 00:20:23 -0500528 case 'e':
Stephen Warrene578b922016-01-26 11:10:11 -0700529 pci_init();
530 return 0;
Simon Glassb997a732017-04-08 13:10:06 -0600531 case 'r': /* no break */
wdenkc6097192002-11-03 00:24:07 +0000532 default: /* scan bus */
533 value = 1; /* short listing */
wdenkc6097192002-11-03 00:24:07 +0000534 if (argc > 1) {
Simon Glassb997a732017-04-08 13:10:06 -0600535 if (cmd != 'r' && argv[argc-1][0] == 'l') {
wdenkc6097192002-11-03 00:24:07 +0000536 value = 0;
537 argc--;
538 }
Pali Rohár39320932022-01-17 16:38:38 +0100539 if (argc > 2 || (argc > 1 && cmd != 'r' && argv[1][0] != 's')) {
Pali Rohár1a4942f2022-01-17 16:38:40 +0100540 if (argv[argc - 1][0] != '*') {
541 busnum = hextoul(argv[argc - 1], &endp);
542 if (*endp)
543 goto usage;
544 }
Pali Rohár6850a5a2022-01-17 16:38:39 +0100545 argc--;
Pali Rohár39320932022-01-17 16:38:38 +0100546 }
Pali Rohár6850a5a2022-01-17 16:38:39 +0100547 if (cmd == 'r' && argc > 2)
548 goto usage;
549 else if (cmd != 'r' && (argc > 2 || (argc == 2 && argv[1][0] != 's')))
550 goto usage;
wdenkc6097192002-11-03 00:24:07 +0000551 }
Pali Rohár1a4942f2022-01-17 16:38:40 +0100552 if (busnum == -1) {
553 if (cmd != 'r') {
554 for (busnum = 0;
555 uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
556 busnum++)
557 pciinfo(bus, value, true);
558 } else {
559 for (busnum = 0;
560 uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
561 busnum++) {
562 /* Regions are controller specific so skip non-root buses */
563 if (device_is_on_pci_bus(bus))
564 continue;
565 pci_show_regions(bus);
566 }
567 }
568 return 0;
569 }
Simon Glasscab24b32015-11-26 19:51:29 -0700570 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
571 if (ret) {
572 printf("No such bus\n");
573 return CMD_RET_FAILURE;
574 }
Simon Glassb997a732017-04-08 13:10:06 -0600575 if (cmd == 'r')
576 pci_show_regions(bus);
577 else
Pali Rohár1a4942f2022-01-17 16:38:40 +0100578 pciinfo(bus, value, false);
wdenkc6097192002-11-03 00:24:07 +0000579 return 0;
580 }
581
Simon Glassf3f1fae2015-11-29 13:17:48 -0700582 ret = dm_pci_bus_find_bdf(bdf, &dev);
Simon Glasscab24b32015-11-26 19:51:29 -0700583 if (ret) {
584 printf("No such device\n");
585 return CMD_RET_FAILURE;
586 }
Simon Glass32ec5b32015-11-26 19:51:27 -0700587
wdenkc6097192002-11-03 00:24:07 +0000588 switch (argv[1][0]) {
589 case 'h': /* header */
Simon Glass32ec5b32015-11-26 19:51:27 -0700590 pci_header_show(dev);
Simon Glassbfa41912015-11-26 19:51:18 -0700591 break;
wdenkc6097192002-11-03 00:24:07 +0000592 case 'd': /* display */
Simon Glass32ec5b32015-11-26 19:51:27 -0700593 return pci_cfg_display(dev, addr, size, value);
wdenkc6097192002-11-03 00:24:07 +0000594 case 'n': /* next */
595 if (argc < 4)
596 goto usage;
Simon Glass32ec5b32015-11-26 19:51:27 -0700597 ret = pci_cfg_modify(dev, addr, size, value, 0);
Simon Glassbfa41912015-11-26 19:51:18 -0700598 break;
wdenkc6097192002-11-03 00:24:07 +0000599 case 'm': /* modify */
600 if (argc < 4)
601 goto usage;
Simon Glass32ec5b32015-11-26 19:51:27 -0700602 ret = pci_cfg_modify(dev, addr, size, value, 1);
Simon Glassbfa41912015-11-26 19:51:18 -0700603 break;
wdenkc6097192002-11-03 00:24:07 +0000604 case 'w': /* write */
605 if (argc < 5)
606 goto usage;
Simon Glasscab24b32015-11-26 19:51:29 -0700607 ret = dm_pci_write_config(dev, addr, value, size);
Simon Glassbfa41912015-11-26 19:51:18 -0700608 break;
Yehuda Yitschake5f96a82016-12-01 17:14:18 +0200609 case 'b': /* bars */
610 return pci_bar_show(dev);
Simon Glassbfa41912015-11-26 19:51:18 -0700611 default:
612 ret = CMD_RET_USAGE;
613 break;
wdenkc6097192002-11-03 00:24:07 +0000614 }
615
Simon Glassbfa41912015-11-26 19:51:18 -0700616 return ret;
wdenkc6097192002-11-03 00:24:07 +0000617 usage:
Simon Glass4c12eeb2011-12-10 08:44:01 +0000618 return CMD_RET_USAGE;
wdenkc6097192002-11-03 00:24:07 +0000619}
620
wdenk8bde7f72003-06-27 21:31:46 +0000621/***************************************************/
622
Tom Rini36162182023-10-07 15:13:08 -0400623U_BOOT_LONGHELP(pci,
Pali Rohár1a4942f2022-01-17 16:38:40 +0100624 "[bus|*] [long]\n"
wdenk8bde7f72003-06-27 21:31:46 +0000625 " - short or long list of PCI devices on bus 'bus'\n"
John Schmoller96d61602010-10-22 00:20:23 -0500626 "pci enum\n"
Stephen Warrene578b922016-01-26 11:10:11 -0700627 " - Enumerate PCI buses\n"
wdenk8bde7f72003-06-27 21:31:46 +0000628 "pci header b.d.f\n"
629 " - show header of PCI device 'bus.device.function'\n"
Yehuda Yitschake5f96a82016-12-01 17:14:18 +0200630 "pci bar b.d.f\n"
631 " - show BARs base and size for device b.d.f'\n"
Pali Rohár1a4942f2022-01-17 16:38:40 +0100632 "pci regions [bus|*]\n"
Simon Glassb997a732017-04-08 13:10:06 -0600633 " - show PCI regions\n"
wdenk8bde7f72003-06-27 21:31:46 +0000634 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
635 " - display PCI configuration space (CFG)\n"
636 "pci next[.b, .w, .l] b.d.f address\n"
637 " - modify, read and keep CFG address\n"
638 "pci modify[.b, .w, .l] b.d.f address\n"
639 " - modify, auto increment CFG address\n"
640 "pci write[.b, .w, .l] b.d.f address value\n"
Tom Rini36162182023-10-07 15:13:08 -0400641 " - write to CFG address");
Kim Phillips088f1b12012-10-29 13:34:31 +0000642
643U_BOOT_CMD(
644 pci, 5, 1, do_pci,
645 "list and access PCI Configuration Space", pci_help_text
wdenk8bde7f72003-06-27 21:31:46 +0000646);