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Heiko Schocherf5e0d032006-06-19 11:02:41 +02001/*
2 * ppmc7xx.h
3 * ---------
Wolfgang Denkb87dfd22006-07-19 13:50:38 +02004 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +02005 * Wind River PPMC 7xx/74xx board configuration file.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +02006 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +02007 * By Richard Danter (richard.danter@windriver.com)
8 * Copyright (C) 2005 Wind River Systems
9 */
10
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#define CONFIG_PPMC7XX
16
17
18/*===================================================================
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020019 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +020020 * User configurable settings - Modify to your preference
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020021 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +020022 *===================================================================
23 */
24
25/*
26 * Debug
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020027 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020028 * DEBUG - Define this is you want extra debug info
29 * GTREGREAD - Required to build with debug
30 * do_bdinfo - Required to build with debug
Heiko Schocherf5e0d032006-06-19 11:02:41 +020031 */
32
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020033#ifdef DEBUG
34#define GTREGREAD(x) 0xFFFFFFFF
Heiko Schocherf5e0d032006-06-19 11:02:41 +020035#define do_bdinfo(a,b,c,d)
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020036#endif
Heiko Schocherf5e0d032006-06-19 11:02:41 +020037
38/*
39 * CPU type
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020040 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020041 * CONFIG_7xx - We have a 750 or 755 CPU
42 * CONFIG_74xx - We have a 7400 CPU
43 * CONFIG_ALTIVEC - We have altivec enabled CPU (only 7400)
44 * CONFIG_BUS_CLK - System bus clock in Hz
Heiko Schocherf5e0d032006-06-19 11:02:41 +020045 */
46
47#define CONFIG_7xx
48#undef CONFIG_74xx
49#undef CONFIG_ALTIVEC
Wolfgang Denkcdd917a2007-08-02 00:48:45 +020050#define CONFIG_BUS_CLK 66000000
Heiko Schocherf5e0d032006-06-19 11:02:41 +020051
52
53/*
54 * Monitor configuration
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020055 *
Jon Loeliger26a34562007-07-04 22:33:17 -050056 * List of command sets to include in shell
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020057 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +020058 * The following command sets have been tested and known to work:
Wolfgang Denkb87dfd22006-07-19 13:50:38 +020059 *
Jon Loeliger26a34562007-07-04 22:33:17 -050060 * CMD_CACHE - Cache control commands
61 * CMD_MEMORY - Memory display, change and test commands
62 * CMD_FLASH - Erase and program flash
63 * CMD_ENV - Environment commands
64 * CMD_RUN - Run commands stored in env vars
65 * CMD_ELF - Load ELF files
66 * CMD_NET - Networking/file download commands
67 * CMD_PIN - ICMP Echo Request command
68 * CMD_PCI - PCI Bus scanning command
Heiko Schocherf5e0d032006-06-19 11:02:41 +020069 */
70
Jon Loeliger26a34562007-07-04 22:33:17 -050071/*
Jon Loeliger079a1362007-07-10 10:12:10 -050072 * BOOTP options
73 */
74#define CONFIG_BOOTP_BOOTFILESIZE
75#define CONFIG_BOOTP_BOOTPATH
76#define CONFIG_BOOTP_GATEWAY
77#define CONFIG_BOOTP_HOSTNAME
78
79
80/*
Jon Loeliger26a34562007-07-04 22:33:17 -050081 * Command line configuration.
82 */
83#include <config_cmd_default.h>
84
85#define CONFIG_CMD_FLASH
86#define CONFIG_CMD_ENV
87#define CONFIG_CMD_RUN
88#define CONFIG_CMD_ELF
89#define CONFIG_CMD_NET
90#define CONFIG_CMD_PING
91#define CONFIG_CMD_PCI
92
93#undef CONFIG_CMD_KGDB
Heiko Schocherf5e0d032006-06-19 11:02:41 +020094
95
96/*
97 * Serial configuration
98 *
99 * CONFIG_CONS_INDEX - Serial console port number (COM1)
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200100 * CONFIG_BAUDRATE - Serial speed
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200101 */
102
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200103#define CONFIG_CONS_INDEX 1
104#define CONFIG_BAUDRATE 9600
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200105
106
107/*
108 * PCI config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200109 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200110 * CONFIG_PCI - Enable PCI bus
111 * CONFIG_PCI_PNP - Enable Plug & Play support
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200112 * CONFIG_PCI_SCAN_SHOW - Enable display of devices at startup
113 */
114
115#define CONFIG_PCI
116#define CONFIG_PCI_PNP
117#undef CONFIG_PCI_SCAN_SHOW
118
119
120/*
121 * Network config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200122 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200123 * CONFIG_NET_MULTI - Support for multiple network interfaces
124 * CONFIG_EEPRO100 - Intel 8255x Ethernet Controller
125 * CONFIG_EEPRO100_SROM_WRITE - Enable writing to network card ROM
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200126 */
127
128#define CONFIG_NET_MULTI
129#define CONFIG_EEPRO100
130#define CONFIG_EEPRO100_SROM_WRITE
131
132
133/*
134 * Enable extra init functions
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200135 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200136 * CONFIG_MISC_INIT_F - Call pre-relocation init functions
137 * CONFIG_MISC_INIT_R - Call post relocation init functions
138 */
139
140#undef CONFIG_MISC_INIT_F
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200141#define CONFIG_MISC_INIT_R
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200142
143
144/*
145 * Boot config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200146 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200147 * CONFIG_BOOTCOMMAND - Command(s) to execute to auto-boot
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200148 * CONFIG_BOOTDELAY - How long to wait before auto-boot (in sec)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200149 */
150
151#define CONFIG_BOOTCOMMAND \
152 "bootp;" \
153 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
154 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
155 "bootm"
156#define CONFIG_BOOTDELAY 5
157
158
159/*===================================================================
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200160 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200161 * Board configuration settings - You should not need to modify these
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200162 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200163 *===================================================================
164 */
165
166
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200167/*
168 * Memory map
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200169 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200170 * This board runs in a standard CHRP (Map-B) configuration.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200171 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200172 * Type Start End Size Width Chip Sel
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200173 * ----------- ----------- ----------- ------- ------- --------
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200174 * SDRAM 0x00000000 0x04000000 64MB 64b SDRAMCS0
175 * User LED's 0x78000000 RCS3
176 * UART 0x7C000000 RCS2
177 * Mailbox 0xFF000000 RCS1
178 * Flash 0xFFC00000 0xFFFFFFFF 4MB 64b RCS0
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200179 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200180 * Flash sectors are laid out as follows.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200181 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200182 * Sector Start End Size Comments
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200183 * ------- ----------- ----------- ------- -----------
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200184 * 0 0xFFC00000 0xFFC3FFFF 256KB
185 * 1 0xFFC40000 0xFFC7FFFF 256KB
186 * 2 0xFFC80000 0xFFCBFFFF 256KB
187 * 3 0xFFCC0000 0xFFCFFFFF 256KB
188 * 4 0xFFD00000 0xFFD3FFFF 256KB
189 * 5 0xFFD40000 0xFFD7FFFF 256KB
190 * 6 0xFFD80000 0xFFDBFFFF 256KB
191 * 7 0xFFDC0000 0xFFDFFFFF 256KB
192 * 8 0xFFE00000 0xFFE3FFFF 256KB
193 * 9 0xFFE40000 0xFFE7FFFF 256KB
194 * 10 0xFFE80000 0xFFEBFFFF 256KB
195 * 11 0xFFEC0000 0xFFEFFFFF 256KB
196 * 12 0xFFF00000 0xFFF3FFFF 256KB U-Boot code here
197 * 13 0xFFF40000 0xFFF7FFFF 256KB
198 * 14 0xFFF80000 0xFFFBFFFF 256KB
199 * 15 0xFFFC0000 0xFFFDFFFF 128KB
200 * 16 0xFFFE0000 0xFFFE7FFF 32KB U-Boot env vars here
201 * 17 0xFFFE8000 0xFFFEFFFF 32KB U-Boot backup copy of env vars here
202 * 18 0xFFFF0000 0xFFFFFFFF 64KB
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200203 */
204
205
206/*
207 * SDRAM config - see memory map details above.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200208 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200209 * CFG_SDRAM_BASE - Start address of SDRAM, this _must_ be zero!
210 * CFG_SDRAM_SIZE - Total size of contiguous SDRAM bank(s)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200211 */
212
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200213#define CFG_SDRAM_BASE 0x00000000
214#define CFG_SDRAM_SIZE 0x04000000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200215
216
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200217/*
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200218 * Flash config - see memory map details above.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200219 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200220 * CFG_FLASH_BASE - Start address of flash memory
221 * CFG_FLASH_SIZE - Total size of contiguous flash mem
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200222 * CFG_FLASH_ERASE_TOUT - Erase timeout in ms
223 * CFG_FLASH_WRITE_TOUT - Write timeout in ms
224 * CFG_MAX_FLASH_BANKS - Number of banks of flash on board
225 * CFG_MAX_FLASH_SECT - Number of sectors in a bank
226 */
227
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200228#define CFG_FLASH_BASE 0xFFC00000
229#define CFG_FLASH_SIZE 0x00400000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200230#define CFG_FLASH_ERASE_TOUT 250000
231#define CFG_FLASH_WRITE_TOUT 5000
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200232#define CFG_MAX_FLASH_BANKS 1
233#define CFG_MAX_FLASH_SECT 19
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200234
235
236/*
237 * Monitor config - see memory map details above
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200238 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200239 * CFG_MONITOR_BASE - Base address of monitor code
240 * CFG_MALLOC_LEN - Size of malloc pool (128KB)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200241 */
242
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200243#define CFG_MONITOR_BASE TEXT_BASE
244#define CFG_MALLOC_LEN 0x20000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200245
246
247/*
248 * Command shell settings
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200249 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200250 * CFG_BARGSIZE - Boot Argument buffer size
251 * CFG_BOOTMAPSZ - Size of app's mapped RAM at boot (Linux=8MB)
252 * CFG_CBSIZE - Console Buffer (input) size
253 * CFG_LOAD_ADDR - Default load address
254 * CFG_LONGHELP - Provide more detailed help
255 * CFG_MAXARGS - Number of args accepted by monitor commands
256 * CFG_MEMTEST_START - Start address of test to run on RAM
257 * CFG_MEMTEST_END - End address of RAM test
258 * CFG_PBSIZE - Print Buffer (output) size
259 * CFG_PROMPT - Prompt string
260 */
261
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200262#define CFG_BARGSIZE 1024
263#define CFG_BOOTMAPSZ 0x800000
264#define CFG_CBSIZE 1024
265#define CFG_LOAD_ADDR 0x100000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200266#define CFG_LONGHELP
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200267#define CFG_MAXARGS 16
268#define CFG_MEMTEST_START 0x00040000
269#define CFG_MEMTEST_END 0x00040100
270#define CFG_PBSIZE 1024
271#define CFG_PROMPT "=> "
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200272
273
274/*
275 * Environment config - see memory map details above
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200276 *
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200277 * CONFIG_ENV_IS_IN_FLASH - The env variables are stored in flash
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200278 * CONFIG_ENV_ADDR - Address of the sector containing env vars
279 * CONFIG_ENV_SIZE - Ammount of RAM for env vars (used to save RAM, 4KB)
280 * CONFIG_ENV_SECT_SIZE - Size of sector containing env vars (32KB)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200281 */
282
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200283#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200284#define CONFIG_ENV_ADDR 0xFFFE0000
285#define CONFIG_ENV_SIZE 0x1000
286#define CONFIG_ENV_ADDR_REDUND 0xFFFE8000
287#define CONFIG_ENV_SIZE_REDUND 0x1000
288#define CONFIG_ENV_SECT_SIZE 0x8000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200289
290
291/*
292 * Initial RAM config
293 *
294 * Since the main system RAM is initialised very early, we place the INIT_RAM
295 * in the main system RAM just above the exception vectors. The contents are
296 * copied to top of RAM by the init code.
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200297 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200298 * CFG_INIT_RAM_ADDR - Address of Init RAM, above exception vect
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200299 * CFG_INIT_RAM_END - Size of Init RAM
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200300 * CFG_GBL_DATA_SIZE - Ammount of RAM to reserve for global data
301 * CFG_GBL_DATA_OFFSET - Start of global data, top of stack
302 */
303
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200304#define CFG_INIT_RAM_ADDR (CFG_SDRAM_BASE + 0x4000)
305#define CFG_INIT_RAM_END 0x4000
306#define CFG_GBL_DATA_SIZE 128
307#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200308
309
310/*
311 * Initial BAT config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200312 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200313 * BAT0 - System SDRAM
314 * BAT1 - LED's and Serial Port
315 * BAT2 - PCI Memory
316 * BAT3 - PCI I/O including Flash Memory
317 */
318
319#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
320#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
321#define CFG_DBAT0L CFG_IBAT0L
322#define CFG_DBAT0U CFG_IBAT0U
323
324#define CFG_IBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
325#define CFG_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
326#define CFG_DBAT1L (0x70000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
327#define CFG_DBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
328
329#define CFG_IBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
330#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
331#define CFG_DBAT2L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
332#define CFG_DBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
333
334#define CFG_IBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
335#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
336#define CFG_DBAT3L (0xF0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
337#define CFG_DBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
338
339
340/*
341 * Cache config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200342 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200343 * CFG_CACHELINE_SIZE - Size of a cache line (CPU specific)
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200344 * CFG_L2 - L2 cache enabled if defined
345 * L2_INIT - L2 cache init flags
346 * L2_ENABLE - L2 cache enable flags
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200347 */
348
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200349#define CFG_CACHELINE_SIZE 32
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200350#undef CFG_L2
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200351#define L2_INIT 0
352#define L2_ENABLE 0
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200353
354
355/*
356 * Clocks config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200357 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200358 * CFG_BUS_HZ - Bus clock frequency in Hz
359 * CFG_BUS_CLK - As above (?)
360 * CFG_HZ - Decrementer freq in Hz
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200361 */
362
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200363#define CFG_BUS_HZ CONFIG_BUS_CLK
364#define CFG_BUS_CLK CONFIG_BUS_CLK
365#define CFG_HZ 1000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200366
367
368/*
369 * Serial port config
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200370 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200371 * CFG_BAUDRATE_TABLE - List of valid baud rates
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200372 * CFG_NS16550 - Include the NS16550 driver
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200373 * CFG_NS16550_SERIAL - Include the serial (wrapper) driver
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200374 * CFG_NS16550_CLK - Frequency of reference clock
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200375 * CFG_NS16550_REG_SIZE - 64-bit accesses to 8-bit port
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200376 * CFG_NS16550_COM1 - Base address of 1st serial port
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200377 */
378
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200379#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200380#define CFG_NS16550
381#define CFG_NS16550_SERIAL
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200382#define CFG_NS16550_CLK 3686400
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200383#define CFG_NS16550_REG_SIZE -8
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200384#define CFG_NS16550_COM1 0x7C000000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200385
386
387/*
388 * PCI Config - Address Map B (CHRP)
389 */
390
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200391#define CFG_PCI_MEMORY_BUS 0x00000000
392#define CFG_PCI_MEMORY_PHYS 0x00000000
393#define CFG_PCI_MEMORY_SIZE 0x40000000
394#define CFG_PCI_MEM_BUS 0x80000000
395#define CFG_PCI_MEM_PHYS 0x80000000
396#define CFG_PCI_MEM_SIZE 0x7D000000
397#define CFG_ISA_MEM_BUS 0x00000000
398#define CFG_ISA_MEM_PHYS 0xFD000000
399#define CFG_ISA_MEM_SIZE 0x01000000
400#define CFG_PCI_IO_BUS 0x00800000
401#define CFG_PCI_IO_PHYS 0xFE800000
402#define CFG_PCI_IO_SIZE 0x00400000
403#define CFG_ISA_IO_BUS 0x00000000
404#define CFG_ISA_IO_PHYS 0xFE000000
405#define CFG_ISA_IO_SIZE 0x00800000
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200406#define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200407#define CFG_ISA_IO CFG_ISA_IO_PHYS
408#define CFG_60X_PCI_IO_OFFSET CFG_ISA_IO_PHYS
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200409
410
411/*
412 * Extra init functions
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200413 *
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200414 * CFG_BOARD_ASM_INIT - Call assembly init code
415 */
416
417#define CFG_BOARD_ASM_INIT
418
419
420/*
421 * Boot flags
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200422 *
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200423 * BOOTFLAG_COLD - Indicates a power-on boot
424 * BOOTFLAG_WARM - Indicates a software reset
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200425 */
Wolfgang Denkb87dfd22006-07-19 13:50:38 +0200426
Wolfgang Denkcdd917a2007-08-02 00:48:45 +0200427#define BOOTFLAG_COLD 0x01
428#define BOOTFLAG_WARM 0x02
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200429
430
431#endif /* __CONFIG_H */