blob: 5bdab611645166d036f649975780175d0ad86ea2 [file] [log] [blame]
Michal Simek44303df2015-10-30 15:39:18 +01001/*
2 * dts file for Xilinx ZynqMP
3 *
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
Michal Simek91d11532016-12-16 13:12:48 +010010
Michal Simek44303df2015-10-30 15:39:18 +010011/ {
12 compatible = "xlnx,zynqmp";
13 #address-cells = <2>;
Michal Simek85d11422016-04-07 15:07:38 +020014 #size-cells = <2>;
Michal Simek44303df2015-10-30 15:39:18 +010015
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
Michal Simek585ca872017-02-06 10:09:53 +010020 cpu0: cpu@0 {
Michal Simek44303df2015-10-30 15:39:18 +010021 compatible = "arm,cortex-a53", "arm,armv8";
22 device_type = "cpu";
23 enable-method = "psci";
Shubhrajyoti Datta941f61f2017-02-13 15:58:55 +053024 operating-points-v2 = <&cpu_opp_table>;
Michal Simek44303df2015-10-30 15:39:18 +010025 reg = <0x0>;
Stefan Krsmanovic2e15b072016-10-21 12:44:56 +020026 cpu-idle-states = <&CPU_SLEEP_0>;
Michal Simek44303df2015-10-30 15:39:18 +010027 };
28
Michal Simek585ca872017-02-06 10:09:53 +010029 cpu1: cpu@1 {
Michal Simek44303df2015-10-30 15:39:18 +010030 compatible = "arm,cortex-a53", "arm,armv8";
31 device_type = "cpu";
32 enable-method = "psci";
33 reg = <0x1>;
Shubhrajyoti Datta941f61f2017-02-13 15:58:55 +053034 operating-points-v2 = <&cpu_opp_table>;
Stefan Krsmanovic2e15b072016-10-21 12:44:56 +020035 cpu-idle-states = <&CPU_SLEEP_0>;
Michal Simek44303df2015-10-30 15:39:18 +010036 };
37
Michal Simek585ca872017-02-06 10:09:53 +010038 cpu2: cpu@2 {
Michal Simek44303df2015-10-30 15:39:18 +010039 compatible = "arm,cortex-a53", "arm,armv8";
40 device_type = "cpu";
41 enable-method = "psci";
42 reg = <0x2>;
Shubhrajyoti Datta941f61f2017-02-13 15:58:55 +053043 operating-points-v2 = <&cpu_opp_table>;
Stefan Krsmanovic2e15b072016-10-21 12:44:56 +020044 cpu-idle-states = <&CPU_SLEEP_0>;
Michal Simek44303df2015-10-30 15:39:18 +010045 };
46
Michal Simek585ca872017-02-06 10:09:53 +010047 cpu3: cpu@3 {
Michal Simek44303df2015-10-30 15:39:18 +010048 compatible = "arm,cortex-a53", "arm,armv8";
49 device_type = "cpu";
50 enable-method = "psci";
51 reg = <0x3>;
Shubhrajyoti Datta941f61f2017-02-13 15:58:55 +053052 operating-points-v2 = <&cpu_opp_table>;
Stefan Krsmanovic2e15b072016-10-21 12:44:56 +020053 cpu-idle-states = <&CPU_SLEEP_0>;
54 };
55
56 idle-states {
Jyotheeswar Reddyfec54732017-01-13 16:13:39 +053057 entry-method = "arm,psci";
Stefan Krsmanovic2e15b072016-10-21 12:44:56 +020058
59 CPU_SLEEP_0: cpu-sleep-0 {
60 compatible = "arm,idle-state";
61 arm,psci-suspend-param = <0x40000000>;
62 local-timer-stop;
63 entry-latency-us = <300>;
64 exit-latency-us = <600>;
Jolly Shah6a097b02017-06-14 15:03:52 -070065 min-residency-us = <10000>;
Stefan Krsmanovic2e15b072016-10-21 12:44:56 +020066 };
Michal Simek44303df2015-10-30 15:39:18 +010067 };
68 };
69
Shubhrajyoti Datta941f61f2017-02-13 15:58:55 +053070 cpu_opp_table: cpu_opp_table {
71 compatible = "operating-points-v2";
72 opp-shared;
73 opp00 {
74 opp-hz = /bits/ 64 <1199999988>;
75 opp-microvolt = <1000000>;
76 clock-latency-ns = <500000>;
77 };
78 opp01 {
79 opp-hz = /bits/ 64 <599999994>;
80 opp-microvolt = <1000000>;
81 clock-latency-ns = <500000>;
82 };
83 opp02 {
84 opp-hz = /bits/ 64 <399999996>;
85 opp-microvolt = <1000000>;
86 clock-latency-ns = <500000>;
87 };
88 opp03 {
89 opp-hz = /bits/ 64 <299999997>;
90 opp-microvolt = <1000000>;
91 clock-latency-ns = <500000>;
92 };
93 };
94
Michal Simek69d09dd2016-09-09 08:46:39 +020095 dcc: dcc {
96 compatible = "arm,dcc";
97 status = "disabled";
98 u-boot,dm-pre-reloc;
99 };
100
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800101 power-domains {
102 compatible = "xlnx,zynqmp-genpd";
103
104 pd_usb0: pd-usb0 {
105 #power-domain-cells = <0x0>;
106 pd-id = <0x16>;
107 };
108
109 pd_usb1: pd-usb1 {
110 #power-domain-cells = <0x0>;
111 pd-id = <0x17>;
112 };
113
114 pd_sata: pd-sata {
115 #power-domain-cells = <0x0>;
116 pd-id = <0x1c>;
117 };
118
119 pd_spi0: pd-spi0 {
120 #power-domain-cells = <0x0>;
121 pd-id = <0x23>;
122 };
123
124 pd_spi1: pd-spi1 {
125 #power-domain-cells = <0x0>;
126 pd-id = <0x24>;
127 };
128
129 pd_uart0: pd-uart0 {
130 #power-domain-cells = <0x0>;
131 pd-id = <0x21>;
132 };
133
134 pd_uart1: pd-uart1 {
135 #power-domain-cells = <0x0>;
136 pd-id = <0x22>;
137 };
138
139 pd_eth0: pd-eth0 {
140 #power-domain-cells = <0x0>;
141 pd-id = <0x1d>;
142 };
143
144 pd_eth1: pd-eth1 {
145 #power-domain-cells = <0x0>;
146 pd-id = <0x1e>;
147 };
148
149 pd_eth2: pd-eth2 {
150 #power-domain-cells = <0x0>;
151 pd-id = <0x1f>;
152 };
153
154 pd_eth3: pd-eth3 {
155 #power-domain-cells = <0x0>;
156 pd-id = <0x20>;
157 };
158
159 pd_i2c0: pd-i2c0 {
160 #power-domain-cells = <0x0>;
161 pd-id = <0x25>;
162 };
163
164 pd_i2c1: pd-i2c1 {
165 #power-domain-cells = <0x0>;
166 pd-id = <0x26>;
167 };
168
169 pd_dp: pd-dp {
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800170 #power-domain-cells = <0x0>;
171 pd-id = <0x29>;
172 };
173
174 pd_gdma: pd-gdma {
175 #power-domain-cells = <0x0>;
176 pd-id = <0x2a>;
177 };
178
179 pd_adma: pd-adma {
180 #power-domain-cells = <0x0>;
181 pd-id = <0x2b>;
182 };
183
184 pd_ttc0: pd-ttc0 {
185 #power-domain-cells = <0x0>;
186 pd-id = <0x18>;
187 };
188
189 pd_ttc1: pd-ttc1 {
190 #power-domain-cells = <0x0>;
191 pd-id = <0x19>;
192 };
193
194 pd_ttc2: pd-ttc2 {
195 #power-domain-cells = <0x0>;
196 pd-id = <0x1a>;
197 };
198
199 pd_ttc3: pd-ttc3 {
200 #power-domain-cells = <0x0>;
201 pd-id = <0x1b>;
202 };
203
204 pd_sd0: pd-sd0 {
205 #power-domain-cells = <0x0>;
206 pd-id = <0x27>;
207 };
208
209 pd_sd1: pd-sd1 {
210 #power-domain-cells = <0x0>;
211 pd-id = <0x28>;
212 };
213
214 pd_nand: pd-nand {
215 #power-domain-cells = <0x0>;
216 pd-id = <0x2c>;
217 };
218
219 pd_qspi: pd-qspi {
220 #power-domain-cells = <0x0>;
221 pd-id = <0x2d>;
222 };
223
224 pd_gpio: pd-gpio {
225 #power-domain-cells = <0x0>;
226 pd-id = <0x2e>;
227 };
228
229 pd_can0: pd-can0 {
230 #power-domain-cells = <0x0>;
231 pd-id = <0x2f>;
232 };
233
234 pd_can1: pd-can1 {
235 #power-domain-cells = <0x0>;
236 pd-id = <0x30>;
237 };
Filip Drazic2af39322016-08-29 19:32:56 +0200238
239 pd_pcie: pd-pcie {
240 #power-domain-cells = <0x0>;
241 pd-id = <0x3b>;
242 };
243
244 pd_gpu: pd-gpu {
245 #power-domain-cells = <0x0>;
Filip Drazica4d7d562016-08-29 19:32:59 +0200246 pd-id = <0x3a 0x14 0x15>;
Filip Drazic2af39322016-08-29 19:32:56 +0200247 };
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800248 };
249
Michal Simek44303df2015-10-30 15:39:18 +0100250 pmu {
251 compatible = "arm,armv8-pmuv3";
Michal Simek14cd9ea2016-04-07 15:28:33 +0200252 interrupt-parent = <&gic>;
Michal Simek44303df2015-10-30 15:39:18 +0100253 interrupts = <0 143 4>,
254 <0 144 4>,
255 <0 145 4>,
256 <0 146 4>;
257 };
258
259 psci {
260 compatible = "arm,psci-0.2";
261 method = "smc";
262 };
263
Michal Simek8a705a22017-12-01 14:43:05 +0100264 pmufw: firmware {
Michal Simek44303df2015-10-30 15:39:18 +0100265 compatible = "xlnx,zynqmp-pm";
266 method = "smc";
Soren Brinkmann19ee4022016-11-21 16:12:05 -0800267 interrupt-parent = <&gic>;
268 interrupts = <0 35 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100269 };
270
271 timer {
272 compatible = "arm,armv8-timer";
273 interrupt-parent = <&gic>;
Michal Simek6db82e02017-02-09 14:45:12 +0100274 interrupts = <1 13 0xf08>,
275 <1 14 0xf08>,
276 <1 11 0xf08>,
277 <1 10 0xf08>;
Michal Simek44303df2015-10-30 15:39:18 +0100278 };
279
Naga Sureshkumar Relliaaf232f2016-06-20 15:48:30 +0530280 edac {
281 compatible = "arm,cortex-a53-edac";
282 };
283
Nava kishore Manne7689dce2017-05-22 12:05:17 +0530284 fpga_full: fpga-full {
285 compatible = "fpga-region";
286 fpga-mgr = <&pcap>;
287 #address-cells = <2>;
288 #size-cells = <2>;
289 };
290
Nava kishore Manne0d87c4f2017-01-17 16:57:24 +0530291 nvmem_firmware {
292 compatible = "xlnx,zynqmp-nvmem-fw";
293 #address-cells = <1>;
294 #size-cells = <1>;
295
296 soc_revision: soc_revision@0 {
297 reg = <0x0 0x4>;
298 };
299 };
300
Nava kishore Manne7689dce2017-05-22 12:05:17 +0530301 pcap: pcap {
Nava kishore Manned64e43f2016-08-21 00:17:52 +0530302 compatible = "xlnx,zynqmp-pcap-fpga";
303 };
304
Anurag Kumar Vulisha98ad47b2017-02-06 21:40:34 +0530305 rst: reset-controller {
306 compatible = "xlnx,zynqmp-reset";
307 #reset-cells = <1>;
308 };
309
Michal Simekb0c55202017-07-05 14:51:42 +0200310 xlnx_dp_snd_card: dp_snd_card {
311 compatible = "xlnx,dp-snd-card";
312 status = "disabled";
313 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
314 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
315 };
316
317 xlnx_dp_snd_codec0: dp_snd_codec0 {
318 compatible = "xlnx,dp-snd-codec";
319 status = "disabled";
320 clock-names = "aud_clk";
321 };
322
323 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
324 compatible = "xlnx,dp-snd-pcm";
325 status = "disabled";
326 dmas = <&xlnx_dpdma 4>;
327 dma-names = "tx";
328 };
329
330 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
331 compatible = "xlnx,dp-snd-pcm";
332 status = "disabled";
333 dmas = <&xlnx_dpdma 5>;
334 dma-names = "tx";
335 };
336
337 xilinx_drm: xilinx_drm {
338 compatible = "xlnx,drm";
339 status = "disabled";
340 xlnx,encoder-slave = <&xlnx_dp>;
341 xlnx,connector-type = "DisplayPort";
342 xlnx,dp-sub = <&xlnx_dp_sub>;
343 planes {
344 xlnx,pixel-format = "rgb565";
345 plane0 {
346 dmas = <&xlnx_dpdma 3>;
347 dma-names = "dma0";
348 };
349 plane1 {
350 dmas = <&xlnx_dpdma 0>,
351 <&xlnx_dpdma 1>,
352 <&xlnx_dpdma 2>;
353 dma-names = "dma0", "dma1", "dma2";
354 };
355 };
356 };
357
Michal Simekc926e6f2016-11-11 13:21:04 +0100358 amba_apu: amba_apu@0 {
Michal Simek44303df2015-10-30 15:39:18 +0100359 compatible = "simple-bus";
360 #address-cells = <2>;
361 #size-cells = <1>;
Michal Simek85d11422016-04-07 15:07:38 +0200362 ranges = <0 0 0 0 0xffffffff>;
Michal Simek44303df2015-10-30 15:39:18 +0100363
364 gic: interrupt-controller@f9010000 {
365 compatible = "arm,gic-400", "arm,cortex-a15-gic";
366 #interrupt-cells = <3>;
367 reg = <0x0 0xf9010000 0x10000>,
Alexander Graf0a8c4f62016-05-12 13:44:01 +0200368 <0x0 0xf9020000 0x20000>,
Michal Simek44303df2015-10-30 15:39:18 +0100369 <0x0 0xf9040000 0x20000>,
Alexander Graf0a8c4f62016-05-12 13:44:01 +0200370 <0x0 0xf9060000 0x20000>;
Michal Simek44303df2015-10-30 15:39:18 +0100371 interrupt-controller;
372 interrupt-parent = <&gic>;
373 interrupts = <1 9 0xf04>;
374 };
375 };
376
Michal Simekb976fd62016-02-11 07:19:06 +0100377 amba: amba {
Michal Simek44303df2015-10-30 15:39:18 +0100378 compatible = "simple-bus";
Michal Simekc9811e12016-02-22 09:57:27 +0100379 u-boot,dm-pre-reloc;
Michal Simek44303df2015-10-30 15:39:18 +0100380 #address-cells = <2>;
Michal Simekb976fd62016-02-11 07:19:06 +0100381 #size-cells = <2>;
382 ranges;
Michal Simek44303df2015-10-30 15:39:18 +0100383
384 can0: can@ff060000 {
385 compatible = "xlnx,zynq-can-1.0";
386 status = "disabled";
387 clock-names = "can_clk", "pclk";
Michal Simekb976fd62016-02-11 07:19:06 +0100388 reg = <0x0 0xff060000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100389 interrupts = <0 23 4>;
390 interrupt-parent = <&gic>;
391 tx-fifo-depth = <0x40>;
392 rx-fifo-depth = <0x40>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800393 power-domains = <&pd_can0>;
Michal Simek44303df2015-10-30 15:39:18 +0100394 };
395
396 can1: can@ff070000 {
397 compatible = "xlnx,zynq-can-1.0";
398 status = "disabled";
399 clock-names = "can_clk", "pclk";
Michal Simekb976fd62016-02-11 07:19:06 +0100400 reg = <0x0 0xff070000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100401 interrupts = <0 24 4>;
402 interrupt-parent = <&gic>;
403 tx-fifo-depth = <0x40>;
404 rx-fifo-depth = <0x40>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800405 power-domains = <&pd_can1>;
Michal Simek44303df2015-10-30 15:39:18 +0100406 };
407
Michal Simekff50d212015-11-26 11:21:25 +0100408 cci: cci@fd6e0000 {
409 compatible = "arm,cci-400";
Michal Simekb976fd62016-02-11 07:19:06 +0100410 reg = <0x0 0xfd6e0000 0x0 0x9000>;
Michal Simekff50d212015-11-26 11:21:25 +0100411 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
412 #address-cells = <1>;
413 #size-cells = <1>;
414
415 pmu@9000 {
416 compatible = "arm,cci-400-pmu,r1";
417 reg = <0x9000 0x5000>;
418 interrupt-parent = <&gic>;
419 interrupts = <0 123 4>,
420 <0 123 4>,
421 <0 123 4>,
422 <0 123 4>,
423 <0 123 4>;
424 };
425 };
426
Michal Simek44303df2015-10-30 15:39:18 +0100427 /* GDMA */
428 fpd_dma_chan1: dma@fd500000 {
429 status = "disabled";
430 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100431 reg = <0x0 0xfd500000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100432 interrupt-parent = <&gic>;
433 interrupts = <0 124 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530434 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100435 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200436 #stream-id-cells = <1>;
437 iommus = <&smmu 0x14e8>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800438 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100439 };
440
441 fpd_dma_chan2: dma@fd510000 {
442 status = "disabled";
443 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100444 reg = <0x0 0xfd510000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100445 interrupt-parent = <&gic>;
446 interrupts = <0 125 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530447 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100448 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200449 #stream-id-cells = <1>;
450 iommus = <&smmu 0x14e9>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800451 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100452 };
453
454 fpd_dma_chan3: dma@fd520000 {
455 status = "disabled";
456 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100457 reg = <0x0 0xfd520000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100458 interrupt-parent = <&gic>;
459 interrupts = <0 126 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530460 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100461 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200462 #stream-id-cells = <1>;
463 iommus = <&smmu 0x14ea>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800464 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100465 };
466
467 fpd_dma_chan4: dma@fd530000 {
468 status = "disabled";
469 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100470 reg = <0x0 0xfd530000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100471 interrupt-parent = <&gic>;
472 interrupts = <0 127 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530473 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100474 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200475 #stream-id-cells = <1>;
476 iommus = <&smmu 0x14eb>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800477 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100478 };
479
480 fpd_dma_chan5: dma@fd540000 {
481 status = "disabled";
482 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100483 reg = <0x0 0xfd540000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100484 interrupt-parent = <&gic>;
485 interrupts = <0 128 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530486 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100487 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200488 #stream-id-cells = <1>;
489 iommus = <&smmu 0x14ec>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800490 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100491 };
492
493 fpd_dma_chan6: dma@fd550000 {
494 status = "disabled";
495 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100496 reg = <0x0 0xfd550000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100497 interrupt-parent = <&gic>;
498 interrupts = <0 129 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530499 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100500 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200501 #stream-id-cells = <1>;
502 iommus = <&smmu 0x14ed>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800503 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100504 };
505
506 fpd_dma_chan7: dma@fd560000 {
507 status = "disabled";
508 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100509 reg = <0x0 0xfd560000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100510 interrupt-parent = <&gic>;
511 interrupts = <0 130 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530512 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100513 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200514 #stream-id-cells = <1>;
515 iommus = <&smmu 0x14ee>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800516 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100517 };
518
519 fpd_dma_chan8: dma@fd570000 {
520 status = "disabled";
521 compatible = "xlnx,zynqmp-dma-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100522 reg = <0x0 0xfd570000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100523 interrupt-parent = <&gic>;
524 interrupts = <0 131 4>;
VNSL Durgab34d11d2016-03-24 22:45:12 +0530525 clock-names = "clk_main", "clk_apb";
Michal Simek44303df2015-10-30 15:39:18 +0100526 xlnx,bus-width = <128>;
Michal Simekba6ad312016-04-06 10:43:23 +0200527 #stream-id-cells = <1>;
528 iommus = <&smmu 0x14ef>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800529 power-domains = <&pd_gdma>;
Michal Simek44303df2015-10-30 15:39:18 +0100530 };
531
532 gpu: gpu@fd4b0000 {
533 status = "disabled";
534 compatible = "arm,mali-400", "arm,mali-utgard";
Hyun Kwon834ec8e2017-08-21 18:54:29 -0700535 reg = <0x0 0xfd4b0000 0x0 0x10000>;
Michal Simek44303df2015-10-30 15:39:18 +0100536 interrupt-parent = <&gic>;
537 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
538 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
Madhurkiran Harikrishnan59206dd2017-02-17 04:14:45 -0800539 clock-names = "gpu", "gpu_pp0", "gpu_pp1";
Filip Drazic2af39322016-08-29 19:32:56 +0200540 power-domains = <&pd_gpu>;
Michal Simek44303df2015-10-30 15:39:18 +0100541 };
542
Kedareswara rao Appana6af57732016-09-09 12:36:01 +0530543 /* LPDDMA default allows only secured access. inorder to enable
544 * These dma channels, Users should ensure that these dma
545 * Channels are allowed for non secure access.
546 */
Michal Simek44303df2015-10-30 15:39:18 +0100547 lpd_dma_chan1: dma@ffa80000 {
548 status = "disabled";
549 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530550 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100551 reg = <0x0 0xffa80000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100552 interrupt-parent = <&gic>;
553 interrupts = <0 77 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100554 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200555 #stream-id-cells = <1>;
556 iommus = <&smmu 0x868>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800557 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100558 };
559
560 lpd_dma_chan2: dma@ffa90000 {
561 status = "disabled";
562 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530563 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100564 reg = <0x0 0xffa90000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100565 interrupt-parent = <&gic>;
566 interrupts = <0 78 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100567 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200568 #stream-id-cells = <1>;
569 iommus = <&smmu 0x869>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800570 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100571 };
572
573 lpd_dma_chan3: dma@ffaa0000 {
574 status = "disabled";
575 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530576 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100577 reg = <0x0 0xffaa0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100578 interrupt-parent = <&gic>;
579 interrupts = <0 79 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100580 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200581 #stream-id-cells = <1>;
582 iommus = <&smmu 0x86a>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800583 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100584 };
585
586 lpd_dma_chan4: dma@ffab0000 {
587 status = "disabled";
588 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530589 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100590 reg = <0x0 0xffab0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100591 interrupt-parent = <&gic>;
592 interrupts = <0 80 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100593 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200594 #stream-id-cells = <1>;
595 iommus = <&smmu 0x86b>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800596 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100597 };
598
599 lpd_dma_chan5: dma@ffac0000 {
600 status = "disabled";
601 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530602 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100603 reg = <0x0 0xffac0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100604 interrupt-parent = <&gic>;
605 interrupts = <0 81 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100606 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200607 #stream-id-cells = <1>;
608 iommus = <&smmu 0x86c>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800609 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100610 };
611
612 lpd_dma_chan6: dma@ffad0000 {
613 status = "disabled";
614 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530615 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100616 reg = <0x0 0xffad0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100617 interrupt-parent = <&gic>;
618 interrupts = <0 82 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100619 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200620 #stream-id-cells = <1>;
621 iommus = <&smmu 0x86d>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800622 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100623 };
624
625 lpd_dma_chan7: dma@ffae0000 {
626 status = "disabled";
627 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530628 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100629 reg = <0x0 0xffae0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100630 interrupt-parent = <&gic>;
631 interrupts = <0 83 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100632 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200633 #stream-id-cells = <1>;
634 iommus = <&smmu 0x86e>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800635 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100636 };
637
638 lpd_dma_chan8: dma@ffaf0000 {
639 status = "disabled";
640 compatible = "xlnx,zynqmp-dma-1.0";
Kedareswara rao Appanad33046a2016-09-30 10:34:59 +0530641 clock-names = "clk_main", "clk_apb";
Michal Simekb976fd62016-02-11 07:19:06 +0100642 reg = <0x0 0xffaf0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100643 interrupt-parent = <&gic>;
644 interrupts = <0 84 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100645 xlnx,bus-width = <64>;
Michal Simekba6ad312016-04-06 10:43:23 +0200646 #stream-id-cells = <1>;
647 iommus = <&smmu 0x86f>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800648 power-domains = <&pd_adma>;
Michal Simek44303df2015-10-30 15:39:18 +0100649 };
650
Naga Sureshkumar Relli90869002016-03-11 13:10:26 +0530651 mc: memory-controller@fd070000 {
652 compatible = "xlnx,zynqmp-ddrc-2.40a";
Michal Simekb976fd62016-02-11 07:19:06 +0100653 reg = <0x0 0xfd070000 0x0 0x30000>;
Naga Sureshkumar Relli90869002016-03-11 13:10:26 +0530654 interrupt-parent = <&gic>;
655 interrupts = <0 112 4>;
656 };
657
Michal Simek44303df2015-10-30 15:39:18 +0100658 nand0: nand@ff100000 {
659 compatible = "arasan,nfc-v3p10";
660 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +0100661 reg = <0x0 0xff100000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100662 clock-names = "clk_sys", "clk_flash";
663 interrupt-parent = <&gic>;
664 interrupts = <0 14 4>;
665 #address-cells = <2>;
666 #size-cells = <1>;
Michal Simekba6ad312016-04-06 10:43:23 +0200667 #stream-id-cells = <1>;
668 iommus = <&smmu 0x872>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800669 power-domains = <&pd_nand>;
Michal Simek44303df2015-10-30 15:39:18 +0100670 };
671
672 gem0: ethernet@ff0b0000 {
Michal Simekda2ad782016-02-11 15:26:46 +0100673 compatible = "cdns,zynqmp-gem";
Michal Simek44303df2015-10-30 15:39:18 +0100674 status = "disabled";
675 interrupt-parent = <&gic>;
676 interrupts = <0 57 4>, <0 57 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100677 reg = <0x0 0xff0b0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100678 clock-names = "pclk", "hclk", "tx_clk";
679 #address-cells = <1>;
680 #size-cells = <0>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100681 #stream-id-cells = <1>;
Michal Simekba6ad312016-04-06 10:43:23 +0200682 iommus = <&smmu 0x874>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800683 power-domains = <&pd_eth0>;
Michal Simek44303df2015-10-30 15:39:18 +0100684 };
685
686 gem1: ethernet@ff0c0000 {
Michal Simekda2ad782016-02-11 15:26:46 +0100687 compatible = "cdns,zynqmp-gem";
Michal Simek44303df2015-10-30 15:39:18 +0100688 status = "disabled";
689 interrupt-parent = <&gic>;
690 interrupts = <0 59 4>, <0 59 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100691 reg = <0x0 0xff0c0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100692 clock-names = "pclk", "hclk", "tx_clk";
693 #address-cells = <1>;
694 #size-cells = <0>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100695 #stream-id-cells = <1>;
Michal Simekba6ad312016-04-06 10:43:23 +0200696 iommus = <&smmu 0x875>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800697 power-domains = <&pd_eth1>;
Michal Simek44303df2015-10-30 15:39:18 +0100698 };
699
700 gem2: ethernet@ff0d0000 {
Michal Simekda2ad782016-02-11 15:26:46 +0100701 compatible = "cdns,zynqmp-gem";
Michal Simek44303df2015-10-30 15:39:18 +0100702 status = "disabled";
703 interrupt-parent = <&gic>;
704 interrupts = <0 61 4>, <0 61 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100705 reg = <0x0 0xff0d0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100706 clock-names = "pclk", "hclk", "tx_clk";
707 #address-cells = <1>;
708 #size-cells = <0>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100709 #stream-id-cells = <1>;
Michal Simekba6ad312016-04-06 10:43:23 +0200710 iommus = <&smmu 0x876>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800711 power-domains = <&pd_eth2>;
Michal Simek44303df2015-10-30 15:39:18 +0100712 };
713
714 gem3: ethernet@ff0e0000 {
Michal Simekda2ad782016-02-11 15:26:46 +0100715 compatible = "cdns,zynqmp-gem";
Michal Simek44303df2015-10-30 15:39:18 +0100716 status = "disabled";
717 interrupt-parent = <&gic>;
718 interrupts = <0 63 4>, <0 63 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100719 reg = <0x0 0xff0e0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100720 clock-names = "pclk", "hclk", "tx_clk";
721 #address-cells = <1>;
722 #size-cells = <0>;
Edgar E. Iglesias7f1d7d92015-11-26 14:12:20 +0100723 #stream-id-cells = <1>;
Michal Simekba6ad312016-04-06 10:43:23 +0200724 iommus = <&smmu 0x877>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800725 power-domains = <&pd_eth3>;
Michal Simek44303df2015-10-30 15:39:18 +0100726 };
727
728 gpio: gpio@ff0a0000 {
729 compatible = "xlnx,zynqmp-gpio-1.0";
730 status = "disabled";
731 #gpio-cells = <0x2>;
732 interrupt-parent = <&gic>;
733 interrupts = <0 16 4>;
Michal Simek9e826b62016-10-20 10:26:13 +0200734 interrupt-controller;
735 #interrupt-cells = <2>;
Michal Simekb976fd62016-02-11 07:19:06 +0100736 reg = <0x0 0xff0a0000 0x0 0x1000>;
Michal Simek0b33e0b12017-08-30 08:06:11 +0200737 gpio-controller;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800738 power-domains = <&pd_gpio>;
Michal Simek44303df2015-10-30 15:39:18 +0100739 };
740
741 i2c0: i2c@ff020000 {
Moritz Fischerde4914b2016-12-22 09:36:11 -0800742 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
Michal Simek44303df2015-10-30 15:39:18 +0100743 status = "disabled";
744 interrupt-parent = <&gic>;
745 interrupts = <0 17 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100746 reg = <0x0 0xff020000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100747 #address-cells = <1>;
748 #size-cells = <0>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800749 power-domains = <&pd_i2c0>;
Michal Simek44303df2015-10-30 15:39:18 +0100750 };
751
752 i2c1: i2c@ff030000 {
Moritz Fischerde4914b2016-12-22 09:36:11 -0800753 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
Michal Simek44303df2015-10-30 15:39:18 +0100754 status = "disabled";
755 interrupt-parent = <&gic>;
756 interrupts = <0 18 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100757 reg = <0x0 0xff030000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100758 #address-cells = <1>;
759 #size-cells = <0>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800760 power-domains = <&pd_i2c1>;
Michal Simek44303df2015-10-30 15:39:18 +0100761 };
762
Naga Sureshkumar Relli55344802016-05-18 12:23:13 +0530763 ocm: memory-controller@ff960000 {
764 compatible = "xlnx,zynqmp-ocmc-1.0";
Michal Simekb976fd62016-02-11 07:19:06 +0100765 reg = <0x0 0xff960000 0x0 0x1000>;
Naga Sureshkumar Relli55344802016-05-18 12:23:13 +0530766 interrupt-parent = <&gic>;
767 interrupts = <0 10 4>;
768 };
769
Michal Simek44303df2015-10-30 15:39:18 +0100770 pcie: pcie@fd0e0000 {
771 compatible = "xlnx,nwl-pcie-2.11";
772 status = "disabled";
773 #address-cells = <3>;
774 #size-cells = <2>;
775 #interrupt-cells = <1>;
Bharat Kumar Gogada7d6ca732016-07-19 20:49:29 +0530776 msi-controller;
Michal Simek44303df2015-10-30 15:39:18 +0100777 device_type = "pci";
778 interrupt-parent = <&gic>;
Michal Simek91a8b0e2016-01-20 12:59:23 +0100779 interrupts = <0 118 4>,
Bharat Kumar Gogada7d6ca732016-07-19 20:49:29 +0530780 <0 117 4>,
Michal Simek91a8b0e2016-01-20 12:59:23 +0100781 <0 116 4>,
782 <0 115 4>, /* MSI_1 [63...32] */
783 <0 114 4>; /* MSI_0 [31...0] */
Bharat Kumar Gogada7d6ca732016-07-19 20:49:29 +0530784 interrupt-names = "misc","dummy","intx", "msi1", "msi0";
785 msi-parent = <&pcie>;
Michal Simekb976fd62016-02-11 07:19:06 +0100786 reg = <0x0 0xfd0e0000 0x0 0x1000>,
787 <0x0 0xfd480000 0x0 0x1000>,
Bharat Kumar Gogada688d1be2016-08-02 20:34:13 +0530788 <0x80 0x00000000 0x0 0x1000000>;
Michal Simek44303df2015-10-30 15:39:18 +0100789 reg-names = "breg", "pcireg", "cfg";
Bharat Kumar Gogada688d1be2016-08-02 20:34:13 +0530790 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */
791 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
Rob Herringec2b2d42017-03-21 21:03:13 -0500792 bus-range = <0x00 0xff>;
Bharat Kumar Gogada33aec512016-02-15 21:18:58 +0530793 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
794 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
795 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
796 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
797 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
Filip Drazic2af39322016-08-29 19:32:56 +0200798 power-domains = <&pd_pcie>;
Bharat Kumar Gogada33aec512016-02-15 21:18:58 +0530799 pcie_intc: legacy-interrupt-controller {
800 interrupt-controller;
801 #address-cells = <0>;
802 #interrupt-cells = <1>;
803 };
Michal Simek44303df2015-10-30 15:39:18 +0100804 };
805
806 qspi: spi@ff0f0000 {
Michal Simek24124ab2017-01-16 12:07:33 +0100807 u-boot,dm-pre-reloc;
Michal Simek44303df2015-10-30 15:39:18 +0100808 compatible = "xlnx,zynqmp-qspi-1.0";
809 status = "disabled";
810 clock-names = "ref_clk", "pclk";
811 interrupts = <0 15 4>;
812 interrupt-parent = <&gic>;
813 num-cs = <1>;
Michal Simekb976fd62016-02-11 07:19:06 +0100814 reg = <0x0 0xff0f0000 0x0 0x1000>,
815 <0x0 0xc0000000 0x0 0x8000000>;
Michal Simek44303df2015-10-30 15:39:18 +0100816 #address-cells = <1>;
817 #size-cells = <0>;
Michal Simekba6ad312016-04-06 10:43:23 +0200818 #stream-id-cells = <1>;
819 iommus = <&smmu 0x873>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800820 power-domains = <&pd_qspi>;
Michal Simek44303df2015-10-30 15:39:18 +0100821 };
822
823 rtc: rtc@ffa60000 {
824 compatible = "xlnx,zynqmp-rtc";
825 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +0100826 reg = <0x0 0xffa60000 0x0 0x100>;
Michal Simek44303df2015-10-30 15:39:18 +0100827 interrupt-parent = <&gic>;
828 interrupts = <0 26 4>, <0 27 4>;
829 interrupt-names = "alarm", "sec";
Nava kishore Manne4d9d6982017-01-27 18:20:14 +0530830 calibration = <0x8000>;
Michal Simek44303df2015-10-30 15:39:18 +0100831 };
832
Anurag Kumar Vulishadb6c62e2016-05-17 16:49:01 +0530833 serdes: zynqmp_phy@fd400000 {
834 compatible = "xlnx,zynqmp-psgtr";
835 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +0100836 reg = <0x0 0xfd400000 0x0 0x40000>,
837 <0x0 0xfd3d0000 0x0 0x1000>,
Michal Simekb976fd62016-02-11 07:19:06 +0100838 <0x0 0xff5e0000 0x0 0x1000>;
Anurag Kumar Vulisha0aada392017-02-08 17:09:10 +0530839 reg-names = "serdes", "siou", "lpd";
Michal Simek3940bca2017-01-17 14:36:54 +0100840 nvmem-cells = <&soc_revision>;
841 nvmem-cell-names = "soc_revision";
Anurag Kumar Vulisha98ad47b2017-02-06 21:40:34 +0530842 resets = <&rst 16>, <&rst 59>, <&rst 60>,
843 <&rst 61>, <&rst 62>, <&rst 63>,
844 <&rst 64>, <&rst 3>, <&rst 29>,
845 <&rst 30>, <&rst 31>, <&rst 32>;
846 reset-names = "sata_rst", "usb0_crst", "usb1_crst",
847 "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
848 "usb1_apbrst", "dp_rst", "gem0_rst",
849 "gem1_rst", "gem2_rst", "gem3_rst";
Anurag Kumar Vulishadb6c62e2016-05-17 16:49:01 +0530850 lane0: lane0 {
851 #phy-cells = <4>;
852 };
853 lane1: lane1 {
854 #phy-cells = <4>;
855 };
856 lane2: lane2 {
857 #phy-cells = <4>;
858 };
859 lane3: lane3 {
860 #phy-cells = <4>;
861 };
862 };
863
Michal Simek44303df2015-10-30 15:39:18 +0100864 sata: ahci@fd0c0000 {
865 compatible = "ceva,ahci-1v84";
866 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +0100867 reg = <0x0 0xfd0c0000 0x0 0x2000>;
Michal Simek44303df2015-10-30 15:39:18 +0100868 interrupt-parent = <&gic>;
869 interrupts = <0 133 4>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800870 power-domains = <&pd_sata>;
Anurag Kumar Vulisha110d06b2017-07-04 20:03:42 +0530871 #stream-id-cells = <4>;
872 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
873 <&smmu 0x4c2>, <&smmu 0x4c3>;
874 /* dma-coherent; */
Michal Simek44303df2015-10-30 15:39:18 +0100875 };
876
877 sdhci0: sdhci@ff160000 {
Michal Simekc9811e12016-02-22 09:57:27 +0100878 u-boot,dm-pre-reloc;
Sai Krishna Potthuri0488a5e2016-08-16 14:41:35 +0530879 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
Michal Simek44303df2015-10-30 15:39:18 +0100880 status = "disabled";
881 interrupt-parent = <&gic>;
882 interrupts = <0 48 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100883 reg = <0x0 0xff160000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100884 clock-names = "clk_xin", "clk_ahb";
Sai Krishna Potthuri0488a5e2016-08-16 14:41:35 +0530885 xlnx,device_id = <0>;
Michal Simekba6ad312016-04-06 10:43:23 +0200886 #stream-id-cells = <1>;
887 iommus = <&smmu 0x870>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800888 power-domains = <&pd_sd0>;
Manish Narani5e3c90d2017-07-19 21:16:33 +0530889 nvmem-cells = <&soc_revision>;
890 nvmem-cell-names = "soc_revision";
Michal Simek44303df2015-10-30 15:39:18 +0100891 };
892
893 sdhci1: sdhci@ff170000 {
Michal Simekc9811e12016-02-22 09:57:27 +0100894 u-boot,dm-pre-reloc;
Sai Krishna Potthuri0488a5e2016-08-16 14:41:35 +0530895 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
Michal Simek44303df2015-10-30 15:39:18 +0100896 status = "disabled";
897 interrupt-parent = <&gic>;
898 interrupts = <0 49 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100899 reg = <0x0 0xff170000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100900 clock-names = "clk_xin", "clk_ahb";
Sai Krishna Potthuri0488a5e2016-08-16 14:41:35 +0530901 xlnx,device_id = <1>;
Michal Simekba6ad312016-04-06 10:43:23 +0200902 #stream-id-cells = <1>;
903 iommus = <&smmu 0x871>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800904 power-domains = <&pd_sd1>;
Manish Narani5e3c90d2017-07-19 21:16:33 +0530905 nvmem-cells = <&soc_revision>;
906 nvmem-cell-names = "soc_revision";
Michal Simek44303df2015-10-30 15:39:18 +0100907 };
908
Michal Simek9c77cb72017-11-02 11:51:59 +0100909 pinctrl0: pinctrl@ff180000 {
910 compatible = "xlnx,pinctrl-zynqmp";
911 status = "disabled";
912 reg = <0x0 0xff180000 0x0 0x1000>;
913 };
914
Michal Simek44303df2015-10-30 15:39:18 +0100915 smmu: smmu@fd800000 {
916 compatible = "arm,mmu-500";
Michal Simekb976fd62016-02-11 07:19:06 +0100917 reg = <0x0 0xfd800000 0x0 0x20000>;
Michal Simekba6ad312016-04-06 10:43:23 +0200918 #iommu-cells = <1>;
Naga Sureshkumar Relli10f2a292017-03-09 20:00:13 +0530919 status = "disabled";
Michal Simek44303df2015-10-30 15:39:18 +0100920 #global-interrupts = <1>;
921 interrupt-parent = <&gic>;
Edgar E. Iglesias88a85aa2015-11-26 14:12:19 +0100922 interrupts = <0 155 4>,
923 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
924 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
925 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
926 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
Michal Simek44303df2015-10-30 15:39:18 +0100927 };
928
929 spi0: spi@ff040000 {
930 compatible = "cdns,spi-r1p6";
931 status = "disabled";
932 interrupt-parent = <&gic>;
933 interrupts = <0 19 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100934 reg = <0x0 0xff040000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100935 clock-names = "ref_clk", "pclk";
936 #address-cells = <1>;
937 #size-cells = <0>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800938 power-domains = <&pd_spi0>;
Michal Simek44303df2015-10-30 15:39:18 +0100939 };
940
941 spi1: spi@ff050000 {
942 compatible = "cdns,spi-r1p6";
943 status = "disabled";
944 interrupt-parent = <&gic>;
945 interrupts = <0 20 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100946 reg = <0x0 0xff050000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100947 clock-names = "ref_clk", "pclk";
948 #address-cells = <1>;
949 #size-cells = <0>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800950 power-domains = <&pd_spi1>;
Michal Simek44303df2015-10-30 15:39:18 +0100951 };
952
953 ttc0: timer@ff110000 {
954 compatible = "cdns,ttc";
955 status = "disabled";
956 interrupt-parent = <&gic>;
957 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100958 reg = <0x0 0xff110000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100959 timer-width = <32>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800960 power-domains = <&pd_ttc0>;
Michal Simek44303df2015-10-30 15:39:18 +0100961 };
962
963 ttc1: timer@ff120000 {
964 compatible = "cdns,ttc";
965 status = "disabled";
966 interrupt-parent = <&gic>;
967 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100968 reg = <0x0 0xff120000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100969 timer-width = <32>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800970 power-domains = <&pd_ttc1>;
Michal Simek44303df2015-10-30 15:39:18 +0100971 };
972
973 ttc2: timer@ff130000 {
974 compatible = "cdns,ttc";
975 status = "disabled";
976 interrupt-parent = <&gic>;
977 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100978 reg = <0x0 0xff130000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100979 timer-width = <32>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800980 power-domains = <&pd_ttc2>;
Michal Simek44303df2015-10-30 15:39:18 +0100981 };
982
983 ttc3: timer@ff140000 {
984 compatible = "cdns,ttc";
985 status = "disabled";
986 interrupt-parent = <&gic>;
987 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100988 reg = <0x0 0xff140000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +0100989 timer-width = <32>;
Soren Brinkmann8f4e3972016-01-11 15:34:42 -0800990 power-domains = <&pd_ttc3>;
Michal Simek44303df2015-10-30 15:39:18 +0100991 };
992
993 uart0: serial@ff000000 {
Michal Simekc9811e12016-02-22 09:57:27 +0100994 u-boot,dm-pre-reloc;
Michal Simekca2f5872015-11-27 13:22:58 +0100995 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
Michal Simek44303df2015-10-30 15:39:18 +0100996 status = "disabled";
997 interrupt-parent = <&gic>;
998 interrupts = <0 21 4>;
Michal Simekb976fd62016-02-11 07:19:06 +0100999 reg = <0x0 0xff000000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +01001000 clock-names = "uart_clk", "pclk";
Soren Brinkmann8f4e3972016-01-11 15:34:42 -08001001 power-domains = <&pd_uart0>;
Michal Simek44303df2015-10-30 15:39:18 +01001002 };
1003
1004 uart1: serial@ff010000 {
Michal Simekc9811e12016-02-22 09:57:27 +01001005 u-boot,dm-pre-reloc;
Michal Simekca2f5872015-11-27 13:22:58 +01001006 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
Michal Simek44303df2015-10-30 15:39:18 +01001007 status = "disabled";
1008 interrupt-parent = <&gic>;
1009 interrupts = <0 22 4>;
Michal Simekb976fd62016-02-11 07:19:06 +01001010 reg = <0x0 0xff010000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +01001011 clock-names = "uart_clk", "pclk";
Soren Brinkmann8f4e3972016-01-11 15:34:42 -08001012 power-domains = <&pd_uart1>;
Michal Simek44303df2015-10-30 15:39:18 +01001013 };
1014
Manish Naranif7346ef2017-03-27 17:47:00 +05301015 usb0: usb0@ff9d0000 {
Michal Simeka84de482016-04-07 15:06:07 +02001016 #address-cells = <2>;
Michal Simekb976fd62016-02-11 07:19:06 +01001017 #size-cells = <2>;
Michal Simek44303df2015-10-30 15:39:18 +01001018 status = "disabled";
Michal Simeka84de482016-04-07 15:06:07 +02001019 compatible = "xlnx,zynqmp-dwc3";
Manish Naranif7346ef2017-03-27 17:47:00 +05301020 reg = <0x0 0xff9d0000 0x0 0x100>;
Michal Simeka84de482016-04-07 15:06:07 +02001021 clock-names = "bus_clk", "ref_clk";
Soren Brinkmann8f4e3972016-01-11 15:34:42 -08001022 power-domains = <&pd_usb0>;
Michal Simeka84de482016-04-07 15:06:07 +02001023 ranges;
Anurag Kumar Vulisha8e5a4e62017-03-02 14:40:51 +05301024 nvmem-cells = <&soc_revision>;
1025 nvmem-cell-names = "soc_revision";
Michal Simeka84de482016-04-07 15:06:07 +02001026
1027 dwc3_0: dwc3@fe200000 {
1028 compatible = "snps,dwc3";
1029 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +01001030 reg = <0x0 0xfe200000 0x0 0x40000>;
Michal Simeka84de482016-04-07 15:06:07 +02001031 interrupt-parent = <&gic>;
Manish Narani2ef98662017-01-18 17:34:48 +05301032 interrupts = <0 65 4>, <0 69 4>;
Anurag Kumar Vulisha8861dcf2017-06-20 16:25:16 +05301033 #stream-id-cells = <1>;
1034 iommus = <&smmu 0x860>;
Anurag Kumar Vulisha397a08a2017-03-10 19:18:17 +05301035 snps,quirk-frame-length-adjustment = <0x20>;
Michal Simeka84de482016-04-07 15:06:07 +02001036 snps,refclk_fladj;
Manish Naranif7346ef2017-03-27 17:47:00 +05301037 /* dma-coherent; */
Michal Simeka84de482016-04-07 15:06:07 +02001038 };
Michal Simek44303df2015-10-30 15:39:18 +01001039 };
1040
Manish Naranif7346ef2017-03-27 17:47:00 +05301041 usb1: usb1@ff9e0000 {
Michal Simeka84de482016-04-07 15:06:07 +02001042 #address-cells = <2>;
Michal Simekb976fd62016-02-11 07:19:06 +01001043 #size-cells = <2>;
Michal Simek44303df2015-10-30 15:39:18 +01001044 status = "disabled";
Michal Simeka84de482016-04-07 15:06:07 +02001045 compatible = "xlnx,zynqmp-dwc3";
Manish Naranif7346ef2017-03-27 17:47:00 +05301046 reg = <0x0 0xff9e0000 0x0 0x100>;
Michal Simeka84de482016-04-07 15:06:07 +02001047 clock-names = "bus_clk", "ref_clk";
Soren Brinkmann8f4e3972016-01-11 15:34:42 -08001048 power-domains = <&pd_usb1>;
Michal Simeka84de482016-04-07 15:06:07 +02001049 ranges;
Anurag Kumar Vulisha8e5a4e62017-03-02 14:40:51 +05301050 nvmem-cells = <&soc_revision>;
1051 nvmem-cell-names = "soc_revision";
Michal Simeka84de482016-04-07 15:06:07 +02001052
1053 dwc3_1: dwc3@fe300000 {
1054 compatible = "snps,dwc3";
1055 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +01001056 reg = <0x0 0xfe300000 0x0 0x40000>;
Michal Simeka84de482016-04-07 15:06:07 +02001057 interrupt-parent = <&gic>;
Manish Narani2ef98662017-01-18 17:34:48 +05301058 interrupts = <0 70 4>, <0 74 4>;
Anurag Kumar Vulisha8861dcf2017-06-20 16:25:16 +05301059 #stream-id-cells = <1>;
1060 iommus = <&smmu 0x861>;
Anurag Kumar Vulisha397a08a2017-03-10 19:18:17 +05301061 snps,quirk-frame-length-adjustment = <0x20>;
Michal Simeka84de482016-04-07 15:06:07 +02001062 snps,refclk_fladj;
Manish Naranif7346ef2017-03-27 17:47:00 +05301063 /* dma-coherent; */
Michal Simeka84de482016-04-07 15:06:07 +02001064 };
Michal Simek44303df2015-10-30 15:39:18 +01001065 };
1066
1067 watchdog0: watchdog@fd4d0000 {
1068 compatible = "cdns,wdt-r1p2";
1069 status = "disabled";
1070 interrupt-parent = <&gic>;
Punnaiah Choudary Kallurid3fd4332015-11-04 12:34:17 +05301071 interrupts = <0 113 1>;
Michal Simekb976fd62016-02-11 07:19:06 +01001072 reg = <0x0 0xfd4d0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +01001073 timeout-sec = <10>;
1074 };
1075
Michal Simek795ebc02017-11-02 12:04:43 +01001076 xilinx_ams: ams@ffa50000 {
1077 compatible = "xlnx,zynqmp-ams";
1078 status = "disabled";
1079 interrupt-parent = <&gic>;
1080 interrupts = <0 56 4>;
1081 interrupt-names = "ams-irq";
1082 reg = <0x0 0xffa50000 0x0 0x800>;
1083 reg-names = "ams-base";
1084 #address-cells = <2>;
1085 #size-cells = <2>;
1086 #io-channel-cells = <1>;
1087 ranges;
1088
1089 ams_ps: ams_ps@ffa50800 {
1090 compatible = "xlnx,zynqmp-ams-ps";
1091 status = "disabled";
1092 reg = <0x0 0xffa50800 0x0 0x400>;
1093 };
1094
1095 ams_pl: ams_pl@ffa50c00 {
1096 compatible = "xlnx,zynqmp-ams-pl";
1097 status = "disabled";
1098 reg = <0x0 0xffa50c00 0x0 0x400>;
1099 };
1100 };
1101
Hyun Kwon695d75a2015-11-23 17:12:54 -08001102 xlnx_dp: dp@fd4a0000 {
Michal Simek44303df2015-10-30 15:39:18 +01001103 compatible = "xlnx,v-dp";
1104 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +01001105 reg = <0x0 0xfd4a0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +01001106 interrupts = <0 119 4>;
1107 interrupt-parent = <&gic>;
1108 clock-names = "aclk", "aud_clk";
Jyotheeswar Reddy Mutthareddyvari5f9b0832017-01-02 14:34:51 +05301109 power-domains = <&pd_dp>;
Michal Simek44303df2015-10-30 15:39:18 +01001110 xlnx,dp-version = "v1.2";
1111 xlnx,max-lanes = <2>;
1112 xlnx,max-link-rate = <540000>;
1113 xlnx,max-bpc = <16>;
1114 xlnx,enable-ycrcb;
1115 xlnx,colormetry = "rgb";
1116 xlnx,bpc = <8>;
1117 xlnx,audio-chan = <2>;
1118 xlnx,dp-sub = <&xlnx_dp_sub>;
Hyun Kwon939cfea2015-11-23 17:12:55 -08001119 xlnx,max-pclock-frequency = <300000>;
Michal Simek44303df2015-10-30 15:39:18 +01001120 };
1121
Hyun Kwon695d75a2015-11-23 17:12:54 -08001122 xlnx_dp_sub: dp_sub@fd4aa000 {
Michal Simek44303df2015-10-30 15:39:18 +01001123 compatible = "xlnx,dp-sub";
1124 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +01001125 reg = <0x0 0xfd4aa000 0x0 0x1000>,
1126 <0x0 0xfd4ab000 0x0 0x1000>,
1127 <0x0 0xfd4ac000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +01001128 reg-names = "blend", "av_buf", "aud";
1129 xlnx,output-fmt = "rgb";
Hyun Kwon939cfea2015-11-23 17:12:55 -08001130 xlnx,vid-fmt = "yuyv";
1131 xlnx,gfx-fmt = "rgb565";
Jyotheeswar Reddy Mutthareddyvari5f9b0832017-01-02 14:34:51 +05301132 power-domains = <&pd_dp>;
Michal Simek44303df2015-10-30 15:39:18 +01001133 };
1134
1135 xlnx_dpdma: dma@fd4c0000 {
1136 compatible = "xlnx,dpdma";
1137 status = "disabled";
Michal Simekb976fd62016-02-11 07:19:06 +01001138 reg = <0x0 0xfd4c0000 0x0 0x1000>;
Michal Simek44303df2015-10-30 15:39:18 +01001139 interrupts = <0 122 4>;
1140 interrupt-parent = <&gic>;
1141 clock-names = "axi_clk";
Jyotheeswar Reddy Mutthareddyvari5f9b0832017-01-02 14:34:51 +05301142 power-domains = <&pd_dp>;
Michal Simek44303df2015-10-30 15:39:18 +01001143 dma-channels = <6>;
1144 #dma-cells = <1>;
Michal Simekc926e6f2016-11-11 13:21:04 +01001145 dma-video0channel {
Michal Simek44303df2015-10-30 15:39:18 +01001146 compatible = "xlnx,video0";
1147 };
Michal Simekc926e6f2016-11-11 13:21:04 +01001148 dma-video1channel {
Michal Simek44303df2015-10-30 15:39:18 +01001149 compatible = "xlnx,video1";
1150 };
Michal Simekc926e6f2016-11-11 13:21:04 +01001151 dma-video2channel {
Michal Simek44303df2015-10-30 15:39:18 +01001152 compatible = "xlnx,video2";
1153 };
Michal Simekc926e6f2016-11-11 13:21:04 +01001154 dma-graphicschannel {
Michal Simek44303df2015-10-30 15:39:18 +01001155 compatible = "xlnx,graphics";
1156 };
Michal Simekc926e6f2016-11-11 13:21:04 +01001157 dma-audio0channel {
Michal Simek44303df2015-10-30 15:39:18 +01001158 compatible = "xlnx,audio0";
1159 };
Michal Simekc926e6f2016-11-11 13:21:04 +01001160 dma-audio1channel {
Michal Simek44303df2015-10-30 15:39:18 +01001161 compatible = "xlnx,audio1";
1162 };
1163 };
1164 };
1165};