blob: 4be41ddbf057ce41335a61ff992f11320921c004 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Yen Lin96a78ac2012-03-06 19:00:23 +00002/*
3 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
4 * Copyright (c) 2010-2011 NVIDIA Corporation
5 * NVIDIA Corporation <www.nvidia.com>
Yen Lin96a78ac2012-03-06 19:00:23 +00006 */
7
8#include <common.h>
Simon Glassb0e6ef42014-12-10 08:55:57 -07009#include <dm.h>
10#include <errno.h>
Yen Lin96a78ac2012-03-06 19:00:23 +000011#include <i2c.h>
12#include <asm/io.h>
Bryan Wu3c27fa22016-08-05 16:10:35 -060013#include <clk.h>
14#include <reset.h>
Stephen Warrenfc607d92016-09-13 10:46:02 -060015#ifndef CONFIG_TEGRA186
Yen Lin96a78ac2012-03-06 19:00:23 +000016#include <asm/arch/clock.h>
17#include <asm/arch/funcmux.h>
Bryan Wu3c27fa22016-08-05 16:10:35 -060018#endif
19#include <asm/arch/gpio.h>
Tom Warren150c2492012-09-19 15:50:56 -070020#include <asm/arch-tegra/tegra_i2c.h>
Yen Lin96a78ac2012-03-06 19:00:23 +000021
Simon Glassb0e6ef42014-12-10 08:55:57 -070022enum i2c_type {
23 TYPE_114,
24 TYPE_STD,
25 TYPE_DVC,
26};
27
Yen Lin96a78ac2012-03-06 19:00:23 +000028/* Information about i2c controller */
29struct i2c_bus {
30 int id;
Bryan Wu3c27fa22016-08-05 16:10:35 -060031 struct reset_ctl reset_ctl;
32 struct clk clk;
Yen Lin96a78ac2012-03-06 19:00:23 +000033 int speed;
34 int pinmux_config;
35 struct i2c_control *control;
36 struct i2c_ctlr *regs;
Simon Glassb0e6ef42014-12-10 08:55:57 -070037 enum i2c_type type;
Yen Lin96a78ac2012-03-06 19:00:23 +000038 int inited; /* bus is inited */
39};
40
Yen Lin96a78ac2012-03-06 19:00:23 +000041static void set_packet_mode(struct i2c_bus *i2c_bus)
42{
43 u32 config;
44
45 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
46
Simon Glassb0e6ef42014-12-10 08:55:57 -070047 if (i2c_bus->type == TYPE_DVC) {
Yen Lin96a78ac2012-03-06 19:00:23 +000048 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
49
50 writel(config, &dvc->cnfg);
51 } else {
52 writel(config, &i2c_bus->regs->cnfg);
53 /*
54 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
55 * issues, i.e., some slaves may be wrongly detected.
56 */
57 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
58 }
59}
60
61static void i2c_reset_controller(struct i2c_bus *i2c_bus)
62{
63 /* Reset I2C controller. */
Bryan Wu3c27fa22016-08-05 16:10:35 -060064 reset_assert(&i2c_bus->reset_ctl);
65 udelay(1);
66 reset_deassert(&i2c_bus->reset_ctl);
67 udelay(1);
Yen Lin96a78ac2012-03-06 19:00:23 +000068
69 /* re-program config register to packet mode */
70 set_packet_mode(i2c_bus);
71}
72
Bryan Wu3c27fa22016-08-05 16:10:35 -060073static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
74{
75 int ret;
76
77 ret = reset_assert(&i2c_bus->reset_ctl);
78 if (ret)
79 return ret;
80 ret = clk_enable(&i2c_bus->clk);
81 if (ret)
82 return ret;
83 ret = clk_set_rate(&i2c_bus->clk, rate);
84 if (IS_ERR_VALUE(ret))
85 return ret;
86 ret = reset_deassert(&i2c_bus->reset_ctl);
87 if (ret)
88 return ret;
89
90 return 0;
91}
Bryan Wu3c27fa22016-08-05 16:10:35 -060092
Yen Lin96a78ac2012-03-06 19:00:23 +000093static void i2c_init_controller(struct i2c_bus *i2c_bus)
94{
Simon Glassb0e6ef42014-12-10 08:55:57 -070095 if (!i2c_bus->speed)
96 return;
97 debug("%s: speed=%d\n", __func__, i2c_bus->speed);
Yen Lin96a78ac2012-03-06 19:00:23 +000098 /*
99 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
100 * here, in section 23.3.1, but in fact we seem to need a factor of
101 * 16 to get the right frequency.
102 */
Bryan Wu3c27fa22016-08-05 16:10:35 -0600103 i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
Tom Warrene32624e2013-02-08 07:25:30 +0000104
Simon Glassb0e6ef42014-12-10 08:55:57 -0700105 if (i2c_bus->type == TYPE_114) {
Tom Warrene32624e2013-02-08 07:25:30 +0000106 /*
107 * T114 I2C went to a single clock source for standard/fast and
108 * HS clock speeds. The new clock rate setting calculation is:
109 * SCL = CLK_SOURCE.I2C /
110 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
111 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
112 *
113 * NOTE: We do this here, after the initial clock/pll start,
114 * because if we read the clk_div reg before the controller
115 * is running, we hang, and we need it for the new calc.
116 */
117 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
Bryan Wu3c27fa22016-08-05 16:10:35 -0600118 unsigned rate = CLK_MULT_STD_FAST_MODE *
119 (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2;
Tom Warrene32624e2013-02-08 07:25:30 +0000120 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
121 clk_div_stdfst_mode);
122
Bryan Wu3c27fa22016-08-05 16:10:35 -0600123 i2c_init_clock(i2c_bus, rate);
Tom Warrene32624e2013-02-08 07:25:30 +0000124 }
Yen Lin96a78ac2012-03-06 19:00:23 +0000125
126 /* Reset I2C controller. */
127 i2c_reset_controller(i2c_bus);
128
129 /* Configure I2C controller. */
Simon Glassb0e6ef42014-12-10 08:55:57 -0700130 if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */
Yen Lin96a78ac2012-03-06 19:00:23 +0000131 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
132
133 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
134 }
135
Bryan Wu3c27fa22016-08-05 16:10:35 -0600136#ifndef CONFIG_TEGRA186
Stephen Warrenfc607d92016-09-13 10:46:02 -0600137 funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
Bryan Wu3c27fa22016-08-05 16:10:35 -0600138#endif
Yen Lin96a78ac2012-03-06 19:00:23 +0000139}
140
141static void send_packet_headers(
142 struct i2c_bus *i2c_bus,
143 struct i2c_trans_info *trans,
Stephen Warren68049a02014-06-25 10:57:27 -0600144 u32 packet_id,
145 bool end_with_repeated_start)
Yen Lin96a78ac2012-03-06 19:00:23 +0000146{
147 u32 data;
148
149 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
150 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
151 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
152 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
153 writel(data, &i2c_bus->control->tx_fifo);
154 debug("pkt header 1 sent (0x%x)\n", data);
155
156 /* prepare header2 */
157 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
158 writel(data, &i2c_bus->control->tx_fifo);
159 debug("pkt header 2 sent (0x%x)\n", data);
160
161 /* prepare IO specific header: configure the slave address */
162 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
163
164 /* Enable Read if it is not a write transaction */
165 if (!(trans->flags & I2C_IS_WRITE))
166 data |= PKT_HDR3_READ_MODE_MASK;
Stephen Warren68049a02014-06-25 10:57:27 -0600167 if (end_with_repeated_start)
168 data |= PKT_HDR3_REPEAT_START_MASK;
Yen Lin96a78ac2012-03-06 19:00:23 +0000169
170 /* Write I2C specific header */
171 writel(data, &i2c_bus->control->tx_fifo);
172 debug("pkt header 3 sent (0x%x)\n", data);
173}
174
175static int wait_for_tx_fifo_empty(struct i2c_control *control)
176{
177 u32 count;
178 int timeout_us = I2C_TIMEOUT_USEC;
179
180 while (timeout_us >= 0) {
181 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
182 >> TX_FIFO_EMPTY_CNT_SHIFT;
183 if (count == I2C_FIFO_DEPTH)
184 return 1;
185 udelay(10);
186 timeout_us -= 10;
187 }
188
189 return 0;
190}
191
192static int wait_for_rx_fifo_notempty(struct i2c_control *control)
193{
194 u32 count;
195 int timeout_us = I2C_TIMEOUT_USEC;
196
197 while (timeout_us >= 0) {
198 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
199 >> TX_FIFO_FULL_CNT_SHIFT;
200 if (count)
201 return 1;
202 udelay(10);
203 timeout_us -= 10;
204 }
205
206 return 0;
207}
208
209static int wait_for_transfer_complete(struct i2c_control *control)
210{
211 int int_status;
212 int timeout_us = I2C_TIMEOUT_USEC;
213
214 while (timeout_us >= 0) {
215 int_status = readl(&control->int_status);
216 if (int_status & I2C_INT_NO_ACK_MASK)
217 return -int_status;
218 if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
219 return -int_status;
220 if (int_status & I2C_INT_XFER_COMPLETE_MASK)
221 return 0;
222
223 udelay(10);
224 timeout_us -= 10;
225 }
226
227 return -1;
228}
229
230static int send_recv_packets(struct i2c_bus *i2c_bus,
231 struct i2c_trans_info *trans)
232{
233 struct i2c_control *control = i2c_bus->control;
234 u32 int_status;
235 u32 words;
236 u8 *dptr;
237 u32 local;
238 uchar last_bytes;
239 int error = 0;
240 int is_write = trans->flags & I2C_IS_WRITE;
241
242 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
243 int_status = readl(&control->int_status);
244 writel(int_status, &control->int_status);
245
Stephen Warren68049a02014-06-25 10:57:27 -0600246 send_packet_headers(i2c_bus, trans, 1,
247 trans->flags & I2C_USE_REPEATED_START);
Yen Lin96a78ac2012-03-06 19:00:23 +0000248
249 words = DIV_ROUND_UP(trans->num_bytes, 4);
250 last_bytes = trans->num_bytes & 3;
251 dptr = trans->buf;
252
253 while (words) {
254 u32 *wptr = (u32 *)dptr;
255
256 if (is_write) {
257 /* deal with word alignment */
Stephen Warren981b14f2014-06-25 10:57:28 -0600258 if ((words == 1) && last_bytes) {
259 local = 0;
260 memcpy(&local, dptr, last_bytes);
Thierry Reding8e67c5d2015-07-22 15:33:22 -0600261 } else if ((unsigned long)dptr & 3) {
Yen Lin96a78ac2012-03-06 19:00:23 +0000262 memcpy(&local, dptr, sizeof(u32));
Yen Lin96a78ac2012-03-06 19:00:23 +0000263 } else {
Stephen Warren981b14f2014-06-25 10:57:28 -0600264 local = *wptr;
Yen Lin96a78ac2012-03-06 19:00:23 +0000265 }
Stephen Warren981b14f2014-06-25 10:57:28 -0600266 writel(local, &control->tx_fifo);
267 debug("pkt data sent (0x%x)\n", local);
Yen Lin96a78ac2012-03-06 19:00:23 +0000268 if (!wait_for_tx_fifo_empty(control)) {
269 error = -1;
270 goto exit;
271 }
272 } else {
273 if (!wait_for_rx_fifo_notempty(control)) {
274 error = -1;
275 goto exit;
276 }
277 /*
278 * for the last word, we read into our local buffer,
279 * in case that caller did not provide enough buffer.
280 */
281 local = readl(&control->rx_fifo);
282 if ((words == 1) && last_bytes)
283 memcpy(dptr, (char *)&local, last_bytes);
Thierry Reding8e67c5d2015-07-22 15:33:22 -0600284 else if ((unsigned long)dptr & 3)
Yen Lin96a78ac2012-03-06 19:00:23 +0000285 memcpy(dptr, &local, sizeof(u32));
286 else
287 *wptr = local;
288 debug("pkt data received (0x%x)\n", local);
289 }
290 words--;
291 dptr += sizeof(u32);
292 }
293
294 if (wait_for_transfer_complete(control)) {
295 error = -1;
296 goto exit;
297 }
298 return 0;
299exit:
300 /* error, reset the controller. */
301 i2c_reset_controller(i2c_bus);
302
303 return error;
304}
305
Simon Glassb0e6ef42014-12-10 08:55:57 -0700306static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
Stephen Warren68049a02014-06-25 10:57:27 -0600307 u32 len, bool end_with_repeated_start)
Yen Lin96a78ac2012-03-06 19:00:23 +0000308{
309 int error;
310 struct i2c_trans_info trans_info;
311
312 trans_info.address = addr;
313 trans_info.buf = data;
314 trans_info.flags = I2C_IS_WRITE;
Stephen Warren68049a02014-06-25 10:57:27 -0600315 if (end_with_repeated_start)
316 trans_info.flags |= I2C_USE_REPEATED_START;
Yen Lin96a78ac2012-03-06 19:00:23 +0000317 trans_info.num_bytes = len;
318 trans_info.is_10bit_address = 0;
319
Simon Glassb0e6ef42014-12-10 08:55:57 -0700320 error = send_recv_packets(i2c_bus, &trans_info);
Yen Lin96a78ac2012-03-06 19:00:23 +0000321 if (error)
Tom Warren29f3e3f2012-09-04 17:00:24 -0700322 debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
Yen Lin96a78ac2012-03-06 19:00:23 +0000323
324 return error;
325}
326
Simon Glassb0e6ef42014-12-10 08:55:57 -0700327static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
Simon Glassd84eb852012-10-30 07:28:52 +0000328 u32 len)
Yen Lin96a78ac2012-03-06 19:00:23 +0000329{
330 int error;
331 struct i2c_trans_info trans_info;
332
333 trans_info.address = addr | 1;
334 trans_info.buf = data;
335 trans_info.flags = 0;
336 trans_info.num_bytes = len;
337 trans_info.is_10bit_address = 0;
338
Simon Glassb0e6ef42014-12-10 08:55:57 -0700339 error = send_recv_packets(i2c_bus, &trans_info);
Yen Lin96a78ac2012-03-06 19:00:23 +0000340 if (error)
Tom Warren29f3e3f2012-09-04 17:00:24 -0700341 debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
Yen Lin96a78ac2012-03-06 19:00:23 +0000342
343 return error;
344}
345
Simon Glassb0e6ef42014-12-10 08:55:57 -0700346static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
Yen Lin96a78ac2012-03-06 19:00:23 +0000347{
Simon Glassb0e6ef42014-12-10 08:55:57 -0700348 struct i2c_bus *i2c_bus = dev_get_priv(dev);
Simon Glassd84eb852012-10-30 07:28:52 +0000349
Simon Glassb0e6ef42014-12-10 08:55:57 -0700350 i2c_bus->speed = speed;
351 i2c_init_controller(i2c_bus);
Yen Lin96a78ac2012-03-06 19:00:23 +0000352
353 return 0;
354}
355
Simon Glassb0e6ef42014-12-10 08:55:57 -0700356static int tegra_i2c_probe(struct udevice *dev)
Yen Lin96a78ac2012-03-06 19:00:23 +0000357{
Simon Glassb0e6ef42014-12-10 08:55:57 -0700358 struct i2c_bus *i2c_bus = dev_get_priv(dev);
Bryan Wu3c27fa22016-08-05 16:10:35 -0600359 int ret;
Simon Glassb0e6ef42014-12-10 08:55:57 -0700360 bool is_dvc;
361
362 i2c_bus->id = dev->seq;
Simon Glass39de8432015-03-25 12:21:55 -0600363 i2c_bus->type = dev_get_driver_data(dev);
Simon Glassd8554d02017-07-25 08:30:06 -0600364 i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
365 if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
366 debug("%s: Cannot get regs address\n", __func__);
367 return -EINVAL;
368 }
Yen Lin96a78ac2012-03-06 19:00:23 +0000369
Bryan Wu3c27fa22016-08-05 16:10:35 -0600370 ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
371 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900372 pr_err("reset_get_by_name() failed: %d\n", ret);
Bryan Wu3c27fa22016-08-05 16:10:35 -0600373 return ret;
374 }
Stephen Warrenb4ee0812016-08-18 11:08:43 -0600375 ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
Bryan Wu3c27fa22016-08-05 16:10:35 -0600376 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900377 pr_err("clk_get_by_name() failed: %d\n", ret);
Bryan Wu3c27fa22016-08-05 16:10:35 -0600378 return ret;
379 }
Stephen Warrenfc607d92016-09-13 10:46:02 -0600380
381#ifndef CONFIG_TEGRA186
382 /*
383 * We don't have a binding for pinmux yet. Leave it out for now. So
384 * far no one needs anything other than the default.
385 */
Yen Lin96a78ac2012-03-06 19:00:23 +0000386 i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
Yen Lin96a78ac2012-03-06 19:00:23 +0000387
388 /*
389 * We can't specify the pinmux config in the fdt, so I2C2 will not
390 * work on Seaboard. It normally has no devices on it anyway.
391 * You could add in this little hack if you need to use it.
392 * The correct solution is a pinmux binding in the fdt.
393 *
Stephen Warrenfc607d92016-09-13 10:46:02 -0600394 * if (i2c_bus->clk.id == PERIPH_ID_I2C2)
Yen Lin96a78ac2012-03-06 19:00:23 +0000395 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
396 */
Bryan Wu3c27fa22016-08-05 16:10:35 -0600397#endif
Yen Lin96a78ac2012-03-06 19:00:23 +0000398
Simon Glass39de8432015-03-25 12:21:55 -0600399 is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
Simon Glassb0e6ef42014-12-10 08:55:57 -0700400 if (is_dvc) {
401 i2c_bus->control =
402 &((struct dvc_ctlr *)i2c_bus->regs)->control;
403 } else {
404 i2c_bus->control = &i2c_bus->regs->control;
Yen Lin96a78ac2012-03-06 19:00:23 +0000405 }
Simon Glassb0e6ef42014-12-10 08:55:57 -0700406 i2c_init_controller(i2c_bus);
Stephen Warrenfc607d92016-09-13 10:46:02 -0600407 debug("%s: controller bus %d at %p, speed %d: ",
408 is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, i2c_bus->speed);
Yen Lin96a78ac2012-03-06 19:00:23 +0000409
410 return 0;
411}
412
Yen Lin96a78ac2012-03-06 19:00:23 +0000413/* i2c write version without the register address */
Simon Glassb0e6ef42014-12-10 08:55:57 -0700414static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
Jeroen Hofstee19d7bf32014-10-08 22:57:46 +0200415 int len, bool end_with_repeated_start)
Yen Lin96a78ac2012-03-06 19:00:23 +0000416{
417 int rc;
418
419 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
420 debug("write_data: ");
421 /* use rc for counter */
422 for (rc = 0; rc < len; ++rc)
423 debug(" 0x%02x", buffer[rc]);
424 debug("\n");
425
426 /* Shift 7-bit address over for lower-level i2c functions */
Simon Glassb0e6ef42014-12-10 08:55:57 -0700427 rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
Stephen Warren68049a02014-06-25 10:57:27 -0600428 end_with_repeated_start);
Yen Lin96a78ac2012-03-06 19:00:23 +0000429 if (rc)
430 debug("i2c_write_data(): rc=%d\n", rc);
431
432 return rc;
433}
434
435/* i2c read version without the register address */
Simon Glassb0e6ef42014-12-10 08:55:57 -0700436static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
437 int len)
Yen Lin96a78ac2012-03-06 19:00:23 +0000438{
439 int rc;
440
441 debug("inside i2c_read_data():\n");
442 /* Shift 7-bit address over for lower-level i2c functions */
Simon Glassb0e6ef42014-12-10 08:55:57 -0700443 rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
Yen Lin96a78ac2012-03-06 19:00:23 +0000444 if (rc) {
445 debug("i2c_read_data(): rc=%d\n", rc);
446 return rc;
447 }
448
449 debug("i2c_read_data: ");
450 /* reuse rc for counter*/
451 for (rc = 0; rc < len; ++rc)
452 debug(" 0x%02x", buffer[rc]);
453 debug("\n");
454
455 return 0;
456}
457
458/* Probe to see if a chip is present. */
Simon Glassb0e6ef42014-12-10 08:55:57 -0700459static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
460 uint chip_flags)
Yen Lin96a78ac2012-03-06 19:00:23 +0000461{
Simon Glassb0e6ef42014-12-10 08:55:57 -0700462 struct i2c_bus *i2c_bus = dev_get_priv(bus);
Yen Lin96a78ac2012-03-06 19:00:23 +0000463 int rc;
Simon Glassb0e6ef42014-12-10 08:55:57 -0700464 u8 reg;
Yen Lin96a78ac2012-03-06 19:00:23 +0000465
Simon Glassb0e6ef42014-12-10 08:55:57 -0700466 /* Shift 7-bit address over for lower-level i2c functions */
467 rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, &reg, sizeof(reg),
468 false);
469
470 return rc;
Yen Lin96a78ac2012-03-06 19:00:23 +0000471}
472
Simon Glassb0e6ef42014-12-10 08:55:57 -0700473static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
474 int nmsgs)
Yen Lin96a78ac2012-03-06 19:00:23 +0000475{
Simon Glassb0e6ef42014-12-10 08:55:57 -0700476 struct i2c_bus *i2c_bus = dev_get_priv(bus);
477 int ret;
Yen Lin96a78ac2012-03-06 19:00:23 +0000478
Simon Glassb0e6ef42014-12-10 08:55:57 -0700479 debug("i2c_xfer: %d messages\n", nmsgs);
480 for (; nmsgs > 0; nmsgs--, msg++) {
481 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
Yen Lin96a78ac2012-03-06 19:00:23 +0000482
Simon Glassb0e6ef42014-12-10 08:55:57 -0700483 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
484 if (msg->flags & I2C_M_RD) {
485 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
486 msg->len);
487 } else {
488 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
489 msg->len, next_is_read);
Yen Lin96a78ac2012-03-06 19:00:23 +0000490 }
Simon Glassb0e6ef42014-12-10 08:55:57 -0700491 if (ret) {
492 debug("i2c_write: error sending\n");
493 return -EREMOTEIO;
Yen Lin96a78ac2012-03-06 19:00:23 +0000494 }
495 }
496
497 return 0;
498}
499
Simon Glassb0e6ef42014-12-10 08:55:57 -0700500int tegra_i2c_get_dvc_bus(struct udevice **busp)
Yen Lin96a78ac2012-03-06 19:00:23 +0000501{
Simon Glassb0e6ef42014-12-10 08:55:57 -0700502 struct udevice *bus;
Yen Lin96a78ac2012-03-06 19:00:23 +0000503
Simon Glassb0e6ef42014-12-10 08:55:57 -0700504 for (uclass_first_device(UCLASS_I2C, &bus);
505 bus;
506 uclass_next_device(&bus)) {
Simon Glass39de8432015-03-25 12:21:55 -0600507 if (dev_get_driver_data(bus) == TYPE_DVC) {
Simon Glassb0e6ef42014-12-10 08:55:57 -0700508 *busp = bus;
509 return 0;
Yen Lin96a78ac2012-03-06 19:00:23 +0000510 }
511 }
512
Simon Glassb0e6ef42014-12-10 08:55:57 -0700513 return -ENODEV;
514}
515
516static const struct dm_i2c_ops tegra_i2c_ops = {
517 .xfer = tegra_i2c_xfer,
518 .probe_chip = tegra_i2c_probe_chip,
519 .set_bus_speed = tegra_i2c_set_bus_speed,
520};
521
Simon Glassb0e6ef42014-12-10 08:55:57 -0700522static const struct udevice_id tegra_i2c_ids[] = {
523 { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
524 { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
525 { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
526 { }
527};
Simon Glasse31c1e52012-04-02 13:19:01 +0000528
Simon Glassb0e6ef42014-12-10 08:55:57 -0700529U_BOOT_DRIVER(i2c_tegra) = {
530 .name = "i2c_tegra",
531 .id = UCLASS_I2C,
532 .of_match = tegra_i2c_ids,
Simon Glassb0e6ef42014-12-10 08:55:57 -0700533 .probe = tegra_i2c_probe,
Simon Glassb0e6ef42014-12-10 08:55:57 -0700534 .priv_auto_alloc_size = sizeof(struct i2c_bus),
535 .ops = &tegra_i2c_ops,
536};