blob: 0e6073c6425be323cc906794e35057a3656a01c5 [file] [log] [blame]
Heiko Schocher67fa8c22010-02-22 16:43:02 +05301/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
5 *
6 * (C) Copyright 2009
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
Holger Brunck8170aef2012-07-05 05:37:46 +00009 * (C) Copyright 2011-2012
10 * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
11 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
Holger Brunck83b40c32011-06-16 18:11:15 +053012 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020013 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher67fa8c22010-02-22 16:43:02 +053014 */
15
16/*
17 * for linking errors see
18 * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
19 */
20
Holger Brunck83b40c32011-06-16 18:11:15 +053021#ifndef _CONFIG_KM_KIRKWOOD_H
22#define _CONFIG_KM_KIRKWOOD_H
Heiko Schocher67fa8c22010-02-22 16:43:02 +053023
Holger Brunck48ced622012-07-05 05:05:06 +000024/* KM_KIRKWOOD */
Holger Brunck8170aef2012-07-05 05:37:46 +000025#if defined(CONFIG_KM_KIRKWOOD)
26#define CONFIG_IDENT_STRING "\nKeymile Kirkwood"
Holger Brunckd9354532012-07-05 05:05:02 +000027#define CONFIG_HOSTNAME km_kirkwood
Holger Brunck48ced622012-07-05 05:05:06 +000028#define CONFIG_KM_DISABLE_PCIE
Heiko Schocherf3e93612012-10-25 11:07:00 +020029#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunck48ced622012-07-05 05:05:06 +000030
31/* KM_KIRKWOOD_PCI */
Holger Brunck8170aef2012-07-05 05:37:46 +000032#elif defined(CONFIG_KM_KIRKWOOD_PCI)
33#define CONFIG_IDENT_STRING "\nKeymile Kirkwood PCI"
Holger Brunckd9354532012-07-05 05:05:02 +000034#define CONFIG_HOSTNAME km_kirkwood_pci
Heiko Schocherf3e93612012-10-25 11:07:00 +020035#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunck48ced622012-07-05 05:05:06 +000036#define CONFIG_KM_FPGA_CONFIG
37
Holger Brunck8170aef2012-07-05 05:37:46 +000038/* KM_NUSA */
39#elif defined(CONFIG_KM_NUSA)
Heiko Schocherf3e93612012-10-25 11:07:00 +020040#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunck8170aef2012-07-05 05:37:46 +000041#define CONFIG_IDENT_STRING "\nKeymile NUSA"
Holger Brunckd9354532012-07-05 05:05:02 +000042#define CONFIG_HOSTNAME kmnusa
Holger Brunck8170aef2012-07-05 05:37:46 +000043#undef CONFIG_SYS_KWD_CONFIG
44#define CONFIG_SYS_KWD_CONFIG \
45 $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg
46#define CONFIG_KM_ENV_IS_IN_SPI_NOR
47#define CONFIG_KM_FPGA_CONFIG
48#define CONFIG_KM_PIGGY4_88E6352
Valentin Longchampbe3e8be2012-08-16 01:25:20 +000049#define CONFIG_MV88E6352_SWITCH
50#define CONFIG_KM_MVEXTSW_ADDR 0x10
Holger Brunck8170aef2012-07-05 05:37:46 +000051
Holger Brunckf9454392012-07-05 05:05:03 +000052/* KM_MGCOGE3UN */
53#elif defined(CONFIG_KM_MGCOGE3UN)
54#define CONFIG_IDENT_STRING "\nKeymile COGE3UN"
55#define CONFIG_HOSTNAME mgcoge3un
Heiko Schocherf3e93612012-10-25 11:07:00 +020056#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunckf9454392012-07-05 05:05:03 +000057#undef CONFIG_SYS_KWD_CONFIG
58#define CONFIG_SYS_KWD_CONFIG \
59 $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-memphis.cfg
60#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0"
61#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
62#define CONFIG_KM_DISABLE_PCIE
63#define CONFIG_KM_PIGGY4_88E6061
64
65/* KMCOGE5UN */
Holger Brunckd9354532012-07-05 05:05:02 +000066#elif defined(CONFIG_KM_COGE5UN)
67#define CONFIG_IDENT_STRING "\nKeymile COGE5UN"
Heiko Schocherf3e93612012-10-25 11:07:00 +020068#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunckd9354532012-07-05 05:05:02 +000069#undef CONFIG_SYS_KWD_CONFIG
70#define CONFIG_SYS_KWD_CONFIG \
71 $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg
72#define CONFIG_KM_ENV_IS_IN_SPI_NOR
73#define CONFIG_PIGGY_MAC_ADRESS_OFFSET 3
74#define CONFIG_HOSTNAME kmcoge5un
75#define CONFIG_KM_DISABLE_PCIE
76#define CONFIG_KM_PIGGY4_88E6352
Holger Brunck6ef64862012-07-05 05:05:04 +000077
78/* KM_PORTL2 */
79#elif defined(CONFIG_KM_PORTL2)
80#define CONFIG_IDENT_STRING "\nKeymile Port-L2"
81#define CONFIG_HOSTNAME portl2
Heiko Schocherf3e93612012-10-25 11:07:00 +020082#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunck6ef64862012-07-05 05:05:04 +000083#define CONFIG_KM_PIGGY4_88E6061
84
Holger Brunck90639fe2013-01-15 22:51:22 +000085/* KM_SUV31 */
86#elif defined(CONFIG_KM_SUV31)
Heiko Schocherea818db2013-01-29 08:53:15 +010087#define CONFIG_KM_IVM_BUS 1 /* I2C2 (Mux-Port 1)*/
Holger Brunck90639fe2013-01-15 22:51:22 +000088#define CONFIG_IDENT_STRING "\nKeymile SUV31"
89#define CONFIG_HOSTNAME kmsuv31
90#define CONFIG_KM_ENV_IS_IN_SPI_NOR
91#define CONFIG_KM_FPGA_CONFIG
92
Holger Brunck8170aef2012-07-05 05:37:46 +000093#else
94#error ("Board unsupported")
95#endif
96
Heiko Schocher67fa8c22010-02-22 16:43:02 +053097/* include common defines/options for all arm based Keymile boards */
Valentin Longchamp264eaa02011-05-04 01:47:33 +000098#include "km/km_arm.h"
Heiko Schocher67fa8c22010-02-22 16:43:02 +053099
Holger Brunck8170aef2012-07-05 05:37:46 +0000100#ifndef CONFIG_KM_ENV_IS_IN_SPI_NOR
Heiko Schocherea818db2013-01-29 08:53:15 +0100101#define KM_ENV_BUS 5 /* I2C2 (Mux-Port 5)*/
Holger Brunck8170aef2012-07-05 05:37:46 +0000102#endif
103
104#if defined(CONFIG_KM_PIGGY4_88E6352)
105/*
106 * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
107 * an Marvell 88E6352 simple switch.
108 * In this case we have to change the default settings for the etherent mac.
109 * There is NO ethernet phy. The ARM and Switch are conencted directly over
110 * RGMII in MAC-MAC mode
111 * In this case 1GBit full duplex and autoneg off
112 */
113#define PORT_SERIAL_CONTROL_VALUE ( \
114 MVGBE_FORCE_LINK_PASS | \
115 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
116 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
117 MVGBE_ADV_NO_FLOW_CTRL | \
118 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
119 MVGBE_FORCE_BP_MODE_NO_JAM | \
120 (1 << 9) /* Reserved bit has to be 1 */ | \
121 MVGBE_DO_NOT_FORCE_LINK_FAIL | \
122 MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
123 MVGBE_DTE_ADV_0 | \
124 MVGBE_MIIPHY_MAC_MODE | \
125 MVGBE_AUTO_NEG_NO_CHANGE | \
126 MVGBE_MAX_RX_PACKET_1552BYTE | \
127 MVGBE_CLR_EXT_LOOPBACK | \
128 MVGBE_SET_FULL_DUPLEX_MODE | \
129 MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
130 MVGBE_SET_GMII_SPEED_TO_1000 |\
131 MVGBE_SET_MII_SPEED_TO_100)
132
133#endif
Heiko Schocher731b9682011-03-08 10:53:51 +0100134
Holger Brunckf9454392012-07-05 05:05:03 +0000135#ifdef CONFIG_KM_PIGGY4_88E6061
136/*
137 * Some keymile boards like mgcoge3un have their PIGGY4 connected via
138 * an Marvell 88E6061 simple switch.
139 * In this case we have to change the default settings for the
140 * ethernet phy connected to the kirkwood.
141 * In this case 100MB full duplex and autoneg off
142 */
143#define PORT_SERIAL_CONTROL_VALUE ( \
144 MVGBE_FORCE_LINK_PASS | \
145 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
146 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
147 MVGBE_ADV_NO_FLOW_CTRL | \
148 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
149 MVGBE_FORCE_BP_MODE_NO_JAM | \
150 (1 << 9) /* Reserved bit has to be 1 */ | \
151 MVGBE_DO_NOT_FORCE_LINK_FAIL | \
152 MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
153 MVGBE_DTE_ADV_0 | \
154 MVGBE_MIIPHY_MAC_MODE | \
155 MVGBE_AUTO_NEG_NO_CHANGE | \
156 MVGBE_MAX_RX_PACKET_1552BYTE | \
157 MVGBE_CLR_EXT_LOOPBACK | \
158 MVGBE_SET_FULL_DUPLEX_MODE | \
159 MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
160 MVGBE_SET_GMII_SPEED_TO_10_100 |\
161 MVGBE_SET_MII_SPEED_TO_100)
162#endif
163
Holger Brunckf9454392012-07-05 05:05:03 +0000164#ifdef CONFIG_KM_DISABLE_PCI
165#undef CONFIG_KIRKWOOD_PCIE_INIT
166#endif
Valentin Longchampb37f7722012-07-05 05:05:05 +0000167
Valentin Longchampb37f7722012-07-05 05:05:05 +0000168
Holger Brunck83b40c32011-06-16 18:11:15 +0530169#endif /* _CONFIG_KM_KIRKWOOD */