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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * Config header file for Cogent platform using an MPC8xx CPU module
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1 /* This is an MPC860 CPU */
37#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
38
wdenkc837dcb2004-01-20 23:12:12 +000039#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
40
wdenk0f8c9762002-08-19 11:57:05 +000041/* Cogent Modular Architecture options */
42#define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */
43#define CONFIG_CMA102 1 /* ...on a CMA102 motherboard */
44#define CONFIG_CMA302 1 /* ...with a CMA302 flash I/O module */
45
46/* serial console configuration */
47#undef CONFIG_8xx_CONS_SMC1
48#undef CONFIG_8xx_CONS_SMC2
49#define CONFIG_8xx_CONS_NONE /* not on 8xx serial ports (eg on cogent m/b) */
50
51#if defined(CONFIG_CMA286_60_OLD)
52#define CONFIG_8xx_GCLK_FREQ 33333000 /* define if cant use get_gclk_freq */
53#endif
54
55#define CONFIG_BAUDRATE 230400
56
57#define CONFIG_HARD_I2C /* I2C with hardware support */
58#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
59#define CFG_I2C_SLAVE 0x7F
60
61
Jon Loeliger37e4f242007-07-04 22:31:56 -050062/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -050063 * BOOTP options
64 */
65#define CONFIG_BOOTP_BOOTFILESIZE
66#define CONFIG_BOOTP_BOOTPATH
67#define CONFIG_BOOTP_GATEWAY
68#define CONFIG_BOOTP_HOSTNAME
69
70
71/*
Jon Loeliger37e4f242007-07-04 22:31:56 -050072 * Command line configuration.
73 */
74#include <config_cmd_default.h>
wdenk0f8c9762002-08-19 11:57:05 +000075
Jon Loeliger37e4f242007-07-04 22:31:56 -050076#define CONFIG_CMD_KGDB
77#define CONFIG_CMD_I2C
78
79#undef CONFIG_CMD_NET
80
wdenk0f8c9762002-08-19 11:57:05 +000081
82#if 0
83#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
84#else
85#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
86#endif
87#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
88
89#define CONFIG_BOOTARGS "root=/dev/ram rw"
90
Jon Loeliger37e4f242007-07-04 22:31:56 -050091#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +000092#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
93#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
94#define CONFIG_KGDB_NONE /* define if kgdb on something else */
95#define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */
96#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
97#endif
98
99#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
100
101/*
102 * Miscellaneous configurable options
103 */
104#define CFG_LONGHELP /* undef to save memory */
105#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500106#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000107#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
108#else
109#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
110#endif
111#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
112#define CFG_MAXARGS 16 /* max number of command args */
113#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
114
115#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
116#define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
117
118#define CFG_LOAD_ADDR 0x100000 /* default load address */
119
120#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
121
122#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
123
124#define CFG_ALLOC_DPRAM
125
126/*
127 * Low Level Configuration Settings
128 * (address mappings, register initial values, etc.)
129 * You should know what you are doing if you make changes here.
130 */
131
132/*-----------------------------------------------------------------------
133 * Low Level Cogent settings
134 * if CFG_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
135 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
136 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
137 * (second 2 for CMA120 only)
138 */
139#define CFG_CMA_MB_BASE 0x00000000 /* base of m/b address space */
140
141#include <configs/cogent_common.h>
142
143#define CFG_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
144#define CONFIG_CONS_INDEX 1
145#define CFG_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
wdenka8c7c702003-12-06 19:49:23 +0000146#define CONFIG_SHOW_ACTIVITY
wdenk0f8c9762002-08-19 11:57:05 +0000147#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
148/*
149 * flash exists on the motherboard
150 * set these four according to TOP dipsw:
151 * TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
152 * TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
153 */
154#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
155#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
156#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
157#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
158#endif
159#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
160#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
161
162/*-----------------------------------------------------------------------
163 * Internal Memory Mapped Register
164 */
165#define CFG_IMMR 0xFF000000
166
167/*-----------------------------------------------------------------------
168 * Definitions for initial stack pointer and data area (in DPRAM)
169 */
170#define CFG_INIT_RAM_ADDR CFG_IMMR
171#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
172#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
173#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
174#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
175
176/*-----------------------------------------------------------------------
177 * Start addresses for the final memory configuration
178 * (Set up by the startup code)
179 * Please note that CFG_SDRAM_BASE _must_ start at 0
180 */
181#define CFG_SDRAM_BASE CMA_MB_RAM_BASE
182#ifdef CONFIG_CMA302
183#define CFG_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
184#else
185#define CFG_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
186#endif
187#define CFG_MONITOR_BASE TEXT_BASE
188#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
189#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
190
191/*
192 * For booting Linux, the board info and command line data
193 * have to be in the first 8 MB of memory, since this is
194 * the maximum mapped by the Linux kernel during initialization.
195 */
196#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
197/*-----------------------------------------------------------------------
198 * FLASH organization
199 */
200#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
201#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
202
203#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
204#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
205
206#define CFG_ENV_IS_IN_FLASH 1
207#define CFG_ENV_ADDR CFG_FLASH_BASE /* Addr of Environment Sector */
208#ifdef CONFIG_CMA302
209#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
210#define CFG_ENV_SECT_SIZE (512*1024) /* see README - env sect real size */
211#else
212#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
213#endif
214/*-----------------------------------------------------------------------
215 * Cache Configuration
216 */
217#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger37e4f242007-07-04 22:31:56 -0500218#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000219#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
220#endif
221
222
223/*-----------------------------------------------------------------------
224 * SYPCR - System Protection Control 11-9
225 * SYPCR can only be written once after reset!
226 *-----------------------------------------------------------------------
227 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
228 */
229#if defined(CONFIG_WATCHDOG)
230#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
231 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
232#else
233#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
234#endif /* CONFIG_WATCHDOG */
235
236/*-----------------------------------------------------------------------
237 * SIUMCR - SIU Module Configuration 11-6
238 *-----------------------------------------------------------------------
239 * PCMCIA config., multi-function pin tri-state
240 */
241#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
242
243/*-----------------------------------------------------------------------
244 * TBSCR - Time Base Status and Control 11-26
245 *-----------------------------------------------------------------------
246 * Clear Reference Interrupt Status, Timebase freezing enabled
247 */
248#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
249
250/*-----------------------------------------------------------------------
251 * PISCR - Periodic Interrupt Status and Control 11-31
252 *-----------------------------------------------------------------------
253 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
254 */
255#define CFG_PISCR (PISCR_PS | PISCR_PITF)
256
257/*-----------------------------------------------------------------------
258 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
259 *-----------------------------------------------------------------------
260 * Reset PLL lock status sticky bit, timer expired status bit and timer
261 * interrupt status bit - leave PLL multiplication factor unchanged !
262 */
263#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
264
265/*-----------------------------------------------------------------------
266 * SCCR - System Clock and reset Control Register 15-27
267 *-----------------------------------------------------------------------
268 * Set clock output, timebase and RTC source and divider,
269 * power management and some other internal clocks
270 */
271#define SCCR_MASK SCCR_EBDF11
272#define CFG_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
273 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
274 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
275 SCCR_DFALCD00)
276
277/*-----------------------------------------------------------------------
278 * PCMCIA stuff
279 *-----------------------------------------------------------------------
280 *
281 */
282#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
283#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
284#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
285#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
286#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
287#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
288#define CFG_PCMCIA_IO_ADDR (0xEC000000)
289#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
290
291/*-----------------------------------------------------------------------
292 *
293 *-----------------------------------------------------------------------
294 *
295 */
296/*#define CFG_DER 0x2002000F*/
297#define CFG_DER 0
298
299#if defined(CONFIG_CMA286_60_OLD)
300
301/*
302 * Init Memory Controller:
303 *
304 * NOTE: although the names (CFG_xRn_PRELIM) suggest preliminary settings,
305 * they are actually the final settings for this cpu/board, because the
306 * flash and RAM are on the motherboard, accessed via the CMAbus, and the
307 * mappings are pretty much fixed.
308 *
309 * (the *_SIZE vars must be a power of 2)
310 */
311
312#define CFG_CMA_CS0_BASE TEXT_BASE /* EPROM */
313#define CFG_CMA_CS0_SIZE (1 << 20)
314#define CFG_CMA_CS1_BASE CMA_MB_RAM_BASE /* RAM + I/O SLOT 1 */
315#define CFG_CMA_CS1_SIZE (64 << 20)
316#define CFG_CMA_CS2_BASE CMA_MB_SLOT2_BASE /* I/O SLOTS 2 + 3 */
317#define CFG_CMA_CS2_SIZE (64 << 20)
318#define CFG_CMA_CS3_BASE CMA_MB_ROMLOW_BASE /* M/B I/O */
319#define CFG_CMA_CS3_SIZE (32 << 20)
320
321/*
322 * CS0 maps the EPROM on the cpu module
323 * Set it for 4 wait states, address CFG_MONITOR_BASE and size 1M
324 *
325 * Note: We must have already transferred control to the final location
326 * of the EPROM before these are used, because when BR0/OR0 are set, the
327 * mirror of the eprom at any other addresses will disappear.
328 */
329
330/* base address = CFG_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
331#define CFG_BR0_PRELIM ((CFG_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
332/* mask size CFG_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
333#define CFG_OR0_PRELIM ((~(CFG_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
334
335/*
336 * CS1 maps motherboard DRAM and motherboard I/O slot 1
337 * (each 32Mbyte in size)
338 */
339
340/* base address = CFG_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
341#define CFG_BR1_PRELIM ((CFG_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
342/* mask size CFG_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
343#define CFG_OR1_PRELIM ((~(CFG_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
344
345/*
346 * CS2 maps motherboard I/O slots 2 and 3
347 * (each 32Mbyte in size)
348 */
349
350/* base address = CFG_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
351#define CFG_BR2_PRELIM ((CFG_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
352/* mask size CFG_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
353#define CFG_OR2_PRELIM ((~(CFG_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
354
355/*
356 * CS3 maps motherboard I/O
357 * (32Mbyte in size)
358 */
359
360/* base address = CFG_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
361#define CFG_BR3_PRELIM ((CFG_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
362/* mask size CFG_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
363#define CFG_OR3_PRELIM ((~(CFG_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
364
365#endif
366
367/*
368 * Internal Definitions
369 *
370 * Boot Flags
371 */
372#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
373#define BOOTFLAG_WARM 0x02 /* Software reboot */
374
375#endif /* __CONFIG_H */