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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mingkai Hua8d97582013-07-04 17:33:43 +08002/**
3 * Copyright 2013 Freescale Semiconductor
4 * Author: Mingkai Hu <Mingkai.Hu@freescale.com>
5 * Po Liu <Po.Liu@freescale.com>
6 *
Mingkai Hua8d97582013-07-04 17:33:43 +08007 * This file provides support for the ngPIXIS, a board-specific FPGA used on
8 * some Freescale reference boards.
9 */
10
11/*
12 * CPLD register set. Feel free to add board-specific #ifdefs where necessary.
13 */
14struct cpld_data {
15 u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */
16 u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */
17 u8 hwver; /* 0x2 - Hardware Version Register */
18 u8 cpldver; /* 0x3 - Software Version Register */
19 u8 res[12];
20 u8 rstcon; /* 0x10 - Reset control register */
21 u8 flhcsr; /* 0x11 - Flash control and status Register */
22 u8 wdcsr; /* 0x12 - Watchdog control and status Register */
23 u8 wdkick; /* 0x13 - Watchdog kick Register */
24 u8 fancsr; /* 0x14 - Fan control and status Register */
25 u8 ledcsr; /* 0x15 - LED control and status Register */
26 u8 misccsr; /* 0x16 - Misc control and status Register */
27 u8 bootor; /* 0x17 - Boot configure override Register */
28 u8 bootcfg1; /* 0x18 - Boot configure 1 Register */
29 u8 bootcfg2; /* 0x19 - Boot configure 2 Register */
30 u8 bootcfg3; /* 0x1a - Boot configure 3 Register */
31 u8 bootcfg4; /* 0x1b - Boot configure 4 Register */
32};
33
34#define CPLD_BANKSEL_EN 0x02
35#define CPLD_BANKSEL_MASK 0x3f
36#define CPLD_SELECT_BANK1 0xc0
37#define CPLD_SELECT_BANK2 0x80
38#define CPLD_SELECT_BANK3 0x40
39#define CPLD_SELECT_BANK4 0x00