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Vladimir Barinov60c04672015-02-14 01:06:13 +03001/*
2 * include/configs/porter.h
3 * This file is Porter board configuration.
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 * Copyright (C) 2015 Cogent Embedded, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0
9 */
10
11#ifndef __PORTER_H
12#define __PORTER_H
13
14#undef DEBUG
15#define CONFIG_R8A7791
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090016#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Porter"
Vladimir Barinov60c04672015-02-14 01:06:13 +030017
18#include "rcar-gen2-common.h"
19
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090020#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Vladimir Barinov60c04672015-02-14 01:06:13 +030021#define CONFIG_SYS_TEXT_BASE 0x70000000
22#else
23#define CONFIG_SYS_TEXT_BASE 0xE6304000
24#endif
25
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090026#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
Vladimir Barinov60c04672015-02-14 01:06:13 +030027#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
28#else
29#define CONFIG_SYS_INIT_SP_ADDR 0xE633fffC
30#endif
31#define STACK_AREA_SIZE 0xC000
32#define LOW_LEVEL_MERAM_STACK \
33 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
34
35/* MEMORY */
36#define RCAR_GEN2_SDRAM_BASE 0x40000000
37#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024)
38#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024)
39
40/* SCIF */
41#define CONFIG_SCIF_CONSOLE
42
43/* FLASH */
44#define CONFIG_SPI
Vladimir Barinov60c04672015-02-14 01:06:13 +030045#define CONFIG_SH_QSPI
Vladimir Barinov60c04672015-02-14 01:06:13 +030046#define CONFIG_SPI_FLASH_QUAD
Vladimir Barinov60c04672015-02-14 01:06:13 +030047
48/* SH Ether */
Vladimir Barinov60c04672015-02-14 01:06:13 +030049#define CONFIG_SH_ETHER
50#define CONFIG_SH_ETHER_USE_PORT 0
51#define CONFIG_SH_ETHER_PHY_ADDR 0x1
52#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
53#define CONFIG_SH_ETHER_CACHE_WRITEBACK
54#define CONFIG_SH_ETHER_CACHE_INVALIDATE
55#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
56#define CONFIG_PHYLIB
57#define CONFIG_PHY_MICREL
58#define CONFIG_BITBANGMII
59#define CONFIG_BITBANGMII_MULTI
60
61/* Board Clock */
62#define RMOBILE_XTAL_CLK 20000000u
63#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
64#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
65#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
66#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
67
68#define CONFIG_SYS_TMU_CLK_DIV 4
69
70/* i2c */
Vladimir Barinov60c04672015-02-14 01:06:13 +030071#define CONFIG_SYS_I2C
72#define CONFIG_SYS_I2C_SH
73#define CONFIG_SYS_I2C_SLAVE 0x7F
74#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
75#define CONFIG_SYS_I2C_SH_SPEED0 400000
76#define CONFIG_SYS_I2C_SH_SPEED1 400000
77#define CONFIG_SYS_I2C_SH_SPEED2 400000
78#define CONFIG_SH_I2C_DATA_HIGH 4
79#define CONFIG_SH_I2C_DATA_LOW 5
80#define CONFIG_SH_I2C_CLOCK 10000000
81
82#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
83
84/* USB */
Vladimir Barinov60c04672015-02-14 01:06:13 +030085#define CONFIG_USB_EHCI_RMOBILE
86#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
Vladimir Barinov60c04672015-02-14 01:06:13 +030087
88/* SD */
Vladimir Barinov60c04672015-02-14 01:06:13 +030089#define CONFIG_SH_SDHI_FREQ 97500000
90
91/* Module stop status bits */
92/* INTC-RT */
93#define CONFIG_SMSTP0_ENA 0x00400000
94/* MSIF */
95#define CONFIG_SMSTP2_ENA 0x00002000
96/* INTC-SYS, IRQC */
97#define CONFIG_SMSTP4_ENA 0x00000180
98/* SCIF0 */
99#define CONFIG_SMSTP7_ENA 0x00200000
100
101#endif /* __PORTER_H */