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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefan Roeseae691e52009-01-21 17:24:49 +01002/*
3 * (C) Copyright 2009 Stefan Roese <sr@denx.de>, DENX Software Engineering
4 *
5 * Copyright (C) 2006 Micronas GmbH
Stefan Roeseae691e52009-01-21 17:24:49 +01006 */
7
8#ifndef _SCC_H
9#define _SCC_H
10
11#define DMA_READ 0 /* SCC read DMA */
12#define DMA_WRITE 1 /* SCC write DMA */
13
14#define DMA_LINEAR 0 /* DMA linear buffer access method */
15#define DMA_CYCLIC 1 /* DMA cyclic buffer access method */
16
17#define DMA_START 0 /* DMA command - start DMA */
18#define DMA_STOP 1 /* DMA command - stop DMA */
19#define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */
20#define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */
21
22#define AGU_ACTIVE 0 /* enable AGU address calculation */
23#define AGU_BYPASS 1 /* set AGU to bypass mode */
24
25#define USE_NO_FH 0 /* order the DMA to not use FH */
26#define USE_FH 1 /* order the DMA to work with FH*/
27
28#define SCC_DBG_IDLE 0 /* DEBUG status (idle interfaces) */
29#define SCC_DBG_SYNC_RES 0x0001 /* synchronuous reset */
30
31#define SCC_TO_IMMEDIATE 1 /* takeover command issued immediately*/
32#define TO_DMA_CFG 2 /* takeover command for the DMA config*/
33
34#define DMA_CMD_RESET 0
35#define DMA_CMD_SETUP 1
36#define DMA_CMD_START 2
37#define DMA_CMD_STOP 3
38
39#define DMA_STATE_RESET 0
40#define DMA_STATE_SETUP 1
41#define DMA_STATE_START 2
42#define DMA_STATE_ERROR 3
43
44#define SRMD 0
45#define STRM_D 1
46#define STRM_P 2
47
48/*
49 * Slowest Monterey domain is DVP 27 MHz (324/27 = 12; 12*16 = 192 CPU clocks)
50 */
51#define RESET_TIME 2 /* cycle calc see in SCC_Reset */
52
53struct scc_descriptor {
54 char *pu_name; /* PU identifier */
55 char *scc_instance; /* SCC Name */
56 u32 profile; /* SCC VCI_D profile */
57
58 u32 base_address; /* base address of the SCC unit reg shell*/
59
60 /* SCS Interconnect configuration */
61 u32 p_scc_id; /* instance number of SCC unit */
62 u32 p_mci_id; /* memory channel ID */
63
64 /* DMA Registers configuration */
65 u32 p_dma_channels_rd; /* Number of Read DMA channels */
66 u32 p_dma_channels_wr; /* Number of Write DMA channels */
67
68 u32 p_dma_packet_desc; /* Number of packet descriptors */
69 u32 p_dma_mci_desc; /* Number of MCI_CFG Descriptors */
70
71 int use_fh; /* the flag tells if SCC uses an FH */
72
73 int p_si2ocp_id; /* instance number of SI2OCP unit */
74 int hw_dma_cfg; /* HW or SW DMA config flag */
75 int hw_dma_start; /* HW or SW DMA start/stop flag */
76
77 u32 *buffer_tag_list; /* list of the buffer tags available */
78 u32 *csize_list; /* list of the valid CSIZE values */
79};
80
81struct scc_dma_state {
82 u32 scc_id:8; /* SCC id */
83 u32 dma_id:8; /* DMA id, used for match with array idx*/
84 u32 buffer_tag:8; /* mem buf tag, assigned to this DMA */
85 u32 dma_status:2; /* state of DMA, of the DMA_STATE_ const*/
86 u32 dma_drs:2; /* DMA dir, either DMA_READ or DMA_WRITE*/
87 u32 dma_cmd:4; /* last executed command on this DMA */
88};
89
90union scc_cmd {
91 u32 reg;
92 struct {
93 u32 res1:19; /* reserved */
94 u32 drs:1; /* DMA Register Set */
95 u32 rid:2; /* Register Identifier */
96 u32 id:6; /* DMA Identifier */
97 u32 action:4; /* DMA Command encoding */
98 } bits;
99};
100
101union scc_dma_cfg {
102 u32 reg;
103 struct {
104 u32 res1:17; /* reserved */
105 u32 agu_mode:1; /* AGU Mode */
106 u32 res2:1; /* reserved */
107 u32 fh_mode:1; /* Fifo Handler */
108 u32 buffer_type:1; /* Defines type of mem buffers */
109 u32 mci_cfg_id:1; /* MCI_CFG register selector */
110 u32 packet_cfg_id:1; /* PACKET_CFG register selector */
111 u32 buffer_id:8; /* DMA Buffer Identifier */
112 } bits;
113};
114
115union scc_debug {
116 u32 reg;
117 struct {
118 u32 res1:20; /* reserved */
119 u32 arg:8; /* SCC Debug Command Argument (#) */
120 u32 cmd:4; /* SCC Debug Command Register */
121 } bits;
122};
123
124union scc_softwareconfiguration {
125 u32 reg;
126 struct {
127 u32 res1:28; /* reserved */
128 u32 clock_status:1; /* clock on/off */
129 u32 packet_select:1; /* active SCC packet id */
130 u32 enable_status:1; /* enabled [1/0] */
131 u32 active_status:1; /* 1=active 0=reset */
132 } bits;
133};
134
135/*
136 * System on Chip Channel ID
137 */
138enum scc_id {
139 SCC_NULL = -1, /* illegal SCC identifier */
140 SCC_FE_3DCOMB_WR, /* SCC_FE_3DCOMB Write channel */
141 SCC_FE_3DCOMB_RD, /* SCC_FE_3DCOMB Read channel */
142 SCC_DI_TNR_WR, /* SCC_DI_TNR Write channel */
143 SCC_DI_TNR_FIELD_RD, /* SCC_DI_TNR_FIELD Read channel */
144 SCC_DI_TNR_FRAME_RD, /* SCC_DI_TNR_FRAME Read channel */
145 SCC_DI_MVAL_WR, /* SCC_DI_MVAL Write channel */
146 SCC_DI_MVAL_RD, /* SCC_DI_MVAL Read channel */
147 SCC_RC_FRAME_WR, /* SCC_RC_FRAME Write channel */
148 SCC_RC_FRAME0_RD, /* SCC_RC_FRAME0 Read channel */
149 SCC_OPT_FIELD0_RD, /* SCC_OPT_FIELD0 Read channel */
150 SCC_OPT_FIELD1_RD, /* SCC_OPT_FIELD1 Read channel */
151 SCC_OPT_FIELD2_RD, /* SCC_OPT_FIELD2 Read channel */
152 SCC_PIP_FRAME_WR, /* SCC_PIP_FRAME Write channel */
153 SCC_PIP_FRAME_RD, /* SCC_PIP_FRAME Read channel */
154 SCC_DP_AGPU_RD, /* SCC_DP_AGPU Read channel */
155 SCC_EWARP_RW, /* SCC_EWARP Read/Write channel */
156 SCC_DP_OSD_RD, /* SCC_DP_OSD Read channel */
157 SCC_DP_GRAPHIC_RD, /* SCC_DP_GRAPHIC Read channel */
158 SCC_DVP_OSD_RD, /* SCC_DVP_OSD Read channel */
159 SCC_DVP_VBI_RD, /* SCC_DVP_VBI Read channel */
160 SCC_TSIO_WR, /* SCC_TSIO Write channel */
161 SCC_TSIO_RD, /* SCC_TSIO Read channel */
162 SCC_TSD_WR, /* SCC_TSD Write channel */
163 SCC_VD_UD_ST_RW, /* SCC_VD_UD_ST Read/Write channel */
164 SCC_VD_FRR_RD, /* SCC_VD_FRR Read channel */
165 SCC_VD_FRW_DISP_WR, /* SCC_VD_FRW_DISP Write channel */
166 SCC_MR_VD_M_Y_RD, /* SCC_MR_VD_M_Y Read channel */
167 SCC_MR_VD_M_C_RD, /* SCC_MR_VD_M_C Read channel */
168 SCC_MR_VD_S_Y_RD, /* SCC_MR_VD_S_Y Read channel */
169 SCC_MR_VD_S_C_RD, /* SCC_MR_VD_S_C Read channel */
170 SCC_GA_WR, /* SCC_GA Write channel */
171 SCC_GA_SRC1_RD, /* SCC_GA_SRC1 Read channel */
172 SCC_GA_SRC2_RD, /* SCC_GA_SRC2 Read channel */
173 SCC_AD_RD, /* SCC_AD Read channel */
174 SCC_AD_WR, /* SCC_AD Write channel */
175 SCC_ABP_RD, /* SCC_ABP Read channel */
176 SCC_ABP_WR, /* SCC_ABP Write channel */
177 SCC_EBI_RW, /* SCC_EBI Read/Write channel */
178 SCC_USB_RW, /* SCC_USB Read/Write channel */
179 SCC_CPU1_SPDMA_RW, /* SCC_CPU1_SPDMA Read/Write channel */
180 SCC_CPU1_BRIDGE_RW, /* SCC_CPU1_BRIDGE Read/Write channel */
181 SCC_MAX /* maximum limit on the SCC id */
182};
183
184int scc_set_usb_address_generation_mode(u32 agu_mode);
185int scc_dma_cmd(enum scc_id id, u32 cmd, u32 dma_id, u32 drs);
186int scc_setup_dma(enum scc_id id, u32 buffer_tag,
187 u32 type, u32 fh_mode, u32 drs, u32 dma_id);
188int scc_enable(enum scc_id id, u32 value);
189int scc_reset(enum scc_id id, u32 value);
190
191#endif /* _SCC_H */