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Vipin KUMAR5b1b1882010-06-29 10:53:34 +05301/*
2 * (C) Copyright 2010
3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Vipin KUMAR5b1b1882010-06-29 10:53:34 +05306 */
7
8/*
Simon Glass64dcd252015-04-05 16:07:40 -06009 * Designware ethernet IP driver for U-Boot
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053010 */
11
12#include <common.h>
Simon Glass75577ba2015-04-05 16:07:41 -060013#include <dm.h>
Simon Glass64dcd252015-04-05 16:07:40 -060014#include <errno.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053015#include <miiphy.h>
16#include <malloc.h>
Bin Meng8b7ee662015-09-11 03:24:35 -070017#include <pci.h>
Stefan Roeseef760252012-05-07 12:04:25 +020018#include <linux/compiler.h>
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053019#include <linux/err.h>
20#include <asm/io.h>
21#include "designware.h"
22
Simon Glass75577ba2015-04-05 16:07:41 -060023DECLARE_GLOBAL_DATA_PTR;
24
Alexey Brodkin92a190a2014-01-22 20:54:06 +040025#if !defined(CONFIG_PHYLIB)
26# error "DesignWare Ether MAC requires PHYLIB - missing CONFIG_PHYLIB"
27#endif
28
29static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
30{
31 struct eth_mac_regs *mac_p = bus->priv;
32 ulong start;
33 u16 miiaddr;
34 int timeout = CONFIG_MDIO_TIMEOUT;
35
36 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
37 ((reg << MIIREGSHIFT) & MII_REGMSK);
38
39 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
40
41 start = get_timer(0);
42 while (get_timer(start) < timeout) {
43 if (!(readl(&mac_p->miiaddr) & MII_BUSY))
44 return readl(&mac_p->miidata);
45 udelay(10);
46 };
47
Simon Glass64dcd252015-04-05 16:07:40 -060048 return -ETIMEDOUT;
Alexey Brodkin92a190a2014-01-22 20:54:06 +040049}
50
51static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
52 u16 val)
53{
54 struct eth_mac_regs *mac_p = bus->priv;
55 ulong start;
56 u16 miiaddr;
Simon Glass64dcd252015-04-05 16:07:40 -060057 int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
Alexey Brodkin92a190a2014-01-22 20:54:06 +040058
59 writel(val, &mac_p->miidata);
60 miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
61 ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
62
63 writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
64
65 start = get_timer(0);
66 while (get_timer(start) < timeout) {
67 if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
68 ret = 0;
69 break;
70 }
71 udelay(10);
72 };
73
74 return ret;
75}
76
Simon Glass64dcd252015-04-05 16:07:40 -060077static int dw_mdio_init(const char *name, struct eth_mac_regs *mac_regs_p)
Alexey Brodkin92a190a2014-01-22 20:54:06 +040078{
79 struct mii_dev *bus = mdio_alloc();
80
81 if (!bus) {
82 printf("Failed to allocate MDIO bus\n");
Simon Glass64dcd252015-04-05 16:07:40 -060083 return -ENOMEM;
Alexey Brodkin92a190a2014-01-22 20:54:06 +040084 }
85
86 bus->read = dw_mdio_read;
87 bus->write = dw_mdio_write;
Simon Glass64dcd252015-04-05 16:07:40 -060088 snprintf(bus->name, sizeof(bus->name), name);
Alexey Brodkin92a190a2014-01-22 20:54:06 +040089
90 bus->priv = (void *)mac_regs_p;
91
92 return mdio_register(bus);
93}
Vipin Kumar13edd172012-03-26 00:09:56 +000094
Simon Glass64dcd252015-04-05 16:07:40 -060095static void tx_descs_init(struct dw_eth_dev *priv)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053096{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +053097 struct eth_dma_regs *dma_p = priv->dma_regs_p;
98 struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
99 char *txbuffs = &priv->txbuffs[0];
100 struct dmamacdescr *desc_p;
101 u32 idx;
102
103 for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
104 desc_p = &desc_table_p[idx];
105 desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
106 desc_p->dmamac_next = &desc_table_p[idx + 1];
107
108#if defined(CONFIG_DW_ALTDESCRIPTOR)
109 desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
110 DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
111 DESC_TXSTS_TXCHECKINSCTRL | \
112 DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
113
114 desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
115 desc_p->dmamac_cntl = 0;
116 desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
117#else
118 desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
119 desc_p->txrx_status = 0;
120#endif
121 }
122
123 /* Correcting the last pointer of the chain */
124 desc_p->dmamac_next = &desc_table_p[0];
125
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400126 /* Flush all Tx buffer descriptors at once */
127 flush_dcache_range((unsigned int)priv->tx_mac_descrtable,
128 (unsigned int)priv->tx_mac_descrtable +
129 sizeof(priv->tx_mac_descrtable));
130
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530131 writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
Alexey Brodkin74cb7082014-01-13 13:28:38 +0400132 priv->tx_currdescnum = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530133}
134
Simon Glass64dcd252015-04-05 16:07:40 -0600135static void rx_descs_init(struct dw_eth_dev *priv)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530136{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530137 struct eth_dma_regs *dma_p = priv->dma_regs_p;
138 struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
139 char *rxbuffs = &priv->rxbuffs[0];
140 struct dmamacdescr *desc_p;
141 u32 idx;
142
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400143 /* Before passing buffers to GMAC we need to make sure zeros
144 * written there right after "priv" structure allocation were
145 * flushed into RAM.
146 * Otherwise there's a chance to get some of them flushed in RAM when
147 * GMAC is already pushing data to RAM via DMA. This way incoming from
148 * GMAC data will be corrupted. */
149 flush_dcache_range((unsigned int)rxbuffs, (unsigned int)rxbuffs +
150 RX_TOTAL_BUFSIZE);
151
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530152 for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
153 desc_p = &desc_table_p[idx];
154 desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
155 desc_p->dmamac_next = &desc_table_p[idx + 1];
156
157 desc_p->dmamac_cntl =
158 (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
159 DESC_RXCTRL_RXCHAIN;
160
161 desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
162 }
163
164 /* Correcting the last pointer of the chain */
165 desc_p->dmamac_next = &desc_table_p[0];
166
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400167 /* Flush all Rx buffer descriptors at once */
168 flush_dcache_range((unsigned int)priv->rx_mac_descrtable,
169 (unsigned int)priv->rx_mac_descrtable +
170 sizeof(priv->rx_mac_descrtable));
171
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530172 writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
Alexey Brodkin74cb7082014-01-13 13:28:38 +0400173 priv->rx_currdescnum = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530174}
175
Simon Glass64dcd252015-04-05 16:07:40 -0600176static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530177{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530178 struct eth_mac_regs *mac_p = priv->mac_regs_p;
179 u32 macid_lo, macid_hi;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530180
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400181 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
182 (mac_id[3] << 24);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530183 macid_hi = mac_id[4] + (mac_id[5] << 8);
184
185 writel(macid_hi, &mac_p->macaddr0hi);
186 writel(macid_lo, &mac_p->macaddr0lo);
187
188 return 0;
189}
190
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400191static void dw_adjust_link(struct eth_mac_regs *mac_p,
192 struct phy_device *phydev)
193{
194 u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
195
196 if (!phydev->link) {
197 printf("%s: No link.\n", phydev->dev->name);
198 return;
199 }
200
201 if (phydev->speed != 1000)
202 conf |= MII_PORTSELECT;
203
204 if (phydev->speed == 100)
205 conf |= FES_100;
206
207 if (phydev->duplex)
208 conf |= FULLDPLXMODE;
209
210 writel(conf, &mac_p->conf);
211
212 printf("Speed: %d, %s duplex%s\n", phydev->speed,
213 (phydev->duplex) ? "full" : "half",
214 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
215}
216
Simon Glass64dcd252015-04-05 16:07:40 -0600217static void _dw_eth_halt(struct dw_eth_dev *priv)
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400218{
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400219 struct eth_mac_regs *mac_p = priv->mac_regs_p;
220 struct eth_dma_regs *dma_p = priv->dma_regs_p;
221
222 writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
223 writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
224
225 phy_shutdown(priv->phydev);
226}
227
Simon Glass64dcd252015-04-05 16:07:40 -0600228static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530229{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530230 struct eth_mac_regs *mac_p = priv->mac_regs_p;
231 struct eth_dma_regs *dma_p = priv->dma_regs_p;
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400232 unsigned int start;
Simon Glass64dcd252015-04-05 16:07:40 -0600233 int ret;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530234
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400235 writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
Vipin Kumar13edd172012-03-26 00:09:56 +0000236
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400237 start = get_timer(0);
238 while (readl(&dma_p->busmode) & DMAMAC_SRST) {
Alexey Brodkin875143f2015-01-13 17:10:24 +0300239 if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
240 printf("DMA reset timeout\n");
Simon Glass64dcd252015-04-05 16:07:40 -0600241 return -ETIMEDOUT;
Alexey Brodkin875143f2015-01-13 17:10:24 +0300242 }
Stefan Roeseef760252012-05-07 12:04:25 +0200243
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400244 mdelay(100);
245 };
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530246
Bin Mengf3edfd32015-06-15 18:40:19 +0800247 /*
248 * Soft reset above clears HW address registers.
249 * So we have to set it here once again.
250 */
251 _dw_write_hwaddr(priv, enetaddr);
252
Simon Glass64dcd252015-04-05 16:07:40 -0600253 rx_descs_init(priv);
254 tx_descs_init(priv);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530255
Ian Campbell49692c52014-05-08 22:26:35 +0100256 writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530257
Sonic Zhangd2279222015-01-29 14:38:50 +0800258#ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400259 writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
260 &dma_p->opmode);
Sonic Zhangd2279222015-01-29 14:38:50 +0800261#else
262 writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
263 &dma_p->opmode);
264#endif
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530265
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400266 writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530267
Sonic Zhang2ddaf132015-01-29 13:37:31 +0800268#ifdef CONFIG_DW_AXI_BURST_LEN
269 writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
270#endif
271
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400272 /* Start up the PHY */
Simon Glass64dcd252015-04-05 16:07:40 -0600273 ret = phy_startup(priv->phydev);
274 if (ret) {
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400275 printf("Could not initialize PHY %s\n",
276 priv->phydev->dev->name);
Simon Glass64dcd252015-04-05 16:07:40 -0600277 return ret;
Vipin Kumar9afc1af2012-05-07 13:06:44 +0530278 }
279
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400280 dw_adjust_link(mac_p, priv->phydev);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530281
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400282 if (!priv->phydev->link)
Simon Glass64dcd252015-04-05 16:07:40 -0600283 return -EIO;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530284
Armando Viscontiaa510052012-03-26 00:09:55 +0000285 writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530286
287 return 0;
288}
289
Simon Glass64dcd252015-04-05 16:07:40 -0600290static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530291{
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530292 struct eth_dma_regs *dma_p = priv->dma_regs_p;
293 u32 desc_num = priv->tx_currdescnum;
294 struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
Marek Vasut96cec172014-09-15 01:05:23 +0200295 uint32_t desc_start = (uint32_t)desc_p;
296 uint32_t desc_end = desc_start +
297 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
298 uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
299 uint32_t data_end = data_start +
300 roundup(length, ARCH_DMA_MINALIGN);
Ian Campbell964ea7c2014-05-08 22:26:33 +0100301 /*
302 * Strictly we only need to invalidate the "txrx_status" field
303 * for the following check, but on some platforms we cannot
Marek Vasut96cec172014-09-15 01:05:23 +0200304 * invalidate only 4 bytes, so we flush the entire descriptor,
305 * which is 16 bytes in total. This is safe because the
306 * individual descriptors in the array are each aligned to
307 * ARCH_DMA_MINALIGN and padded appropriately.
Ian Campbell964ea7c2014-05-08 22:26:33 +0100308 */
Marek Vasut96cec172014-09-15 01:05:23 +0200309 invalidate_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400310
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530311 /* Check if the descriptor is owned by CPU */
312 if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
313 printf("CPU not owner of tx frame\n");
Simon Glass64dcd252015-04-05 16:07:40 -0600314 return -EPERM;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530315 }
316
Marek Vasut96cec172014-09-15 01:05:23 +0200317 memcpy(desc_p->dmamac_addr, packet, length);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530318
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400319 /* Flush data to be sent */
Marek Vasut96cec172014-09-15 01:05:23 +0200320 flush_dcache_range(data_start, data_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400321
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530322#if defined(CONFIG_DW_ALTDESCRIPTOR)
323 desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
324 desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
325 DESC_TXCTRL_SIZE1MASK;
326
327 desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
328 desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
329#else
330 desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
331 DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
332 DESC_TXCTRL_TXFIRST;
333
334 desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
335#endif
336
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400337 /* Flush modified buffer descriptor */
Marek Vasut96cec172014-09-15 01:05:23 +0200338 flush_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400339
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530340 /* Test the wrap-around condition. */
341 if (++desc_num >= CONFIG_TX_DESCR_NUM)
342 desc_num = 0;
343
344 priv->tx_currdescnum = desc_num;
345
346 /* Start the transmission */
347 writel(POLL_DATA, &dma_p->txpolldemand);
348
349 return 0;
350}
351
Simon Glass75577ba2015-04-05 16:07:41 -0600352static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530353{
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400354 u32 status, desc_num = priv->rx_currdescnum;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530355 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
Simon Glass75577ba2015-04-05 16:07:41 -0600356 int length = -EAGAIN;
Marek Vasut96cec172014-09-15 01:05:23 +0200357 uint32_t desc_start = (uint32_t)desc_p;
358 uint32_t desc_end = desc_start +
359 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
360 uint32_t data_start = (uint32_t)desc_p->dmamac_addr;
361 uint32_t data_end;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530362
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400363 /* Invalidate entire buffer descriptor */
Marek Vasut96cec172014-09-15 01:05:23 +0200364 invalidate_dcache_range(desc_start, desc_end);
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400365
366 status = desc_p->txrx_status;
367
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530368 /* Check if the owner is the CPU */
369 if (!(status & DESC_RXSTS_OWNBYDMA)) {
370
371 length = (status & DESC_RXSTS_FRMLENMSK) >> \
372 DESC_RXSTS_FRMLENSHFT;
373
Alexey Brodkin50b0df82014-01-22 20:49:09 +0400374 /* Invalidate received data */
Marek Vasut96cec172014-09-15 01:05:23 +0200375 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
376 invalidate_dcache_range(data_start, data_end);
Simon Glass75577ba2015-04-05 16:07:41 -0600377 *packetp = desc_p->dmamac_addr;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530378 }
379
Simon Glass75577ba2015-04-05 16:07:41 -0600380 return length;
381}
382
383static int _dw_free_pkt(struct dw_eth_dev *priv)
384{
385 u32 desc_num = priv->rx_currdescnum;
386 struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
387 uint32_t desc_start = (uint32_t)desc_p;
388 uint32_t desc_end = desc_start +
389 roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
390
391 /*
392 * Make the current descriptor valid again and go to
393 * the next one
394 */
395 desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
396
397 /* Flush only status field - others weren't changed */
398 flush_dcache_range(desc_start, desc_end);
399
400 /* Test the wrap-around condition. */
401 if (++desc_num >= CONFIG_RX_DESCR_NUM)
402 desc_num = 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530403 priv->rx_currdescnum = desc_num;
404
Simon Glass75577ba2015-04-05 16:07:41 -0600405 return 0;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530406}
407
Simon Glass64dcd252015-04-05 16:07:40 -0600408static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530409{
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400410 struct phy_device *phydev;
411 int mask = 0xffffffff;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530412
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400413#ifdef CONFIG_PHY_ADDR
414 mask = 1 << CONFIG_PHY_ADDR;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530415#endif
416
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400417 phydev = phy_find_by_mask(priv->bus, mask, priv->interface);
418 if (!phydev)
Simon Glass64dcd252015-04-05 16:07:40 -0600419 return -ENODEV;
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530420
Ian Campbell15e82e52014-04-28 20:14:05 +0100421 phy_connect_dev(phydev, dev);
422
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400423 phydev->supported &= PHY_GBIT_FEATURES;
424 phydev->advertising = phydev->supported;
425
426 priv->phydev = phydev;
427 phy_config(phydev);
428
Simon Glass64dcd252015-04-05 16:07:40 -0600429 return 0;
430}
431
Simon Glass75577ba2015-04-05 16:07:41 -0600432#ifndef CONFIG_DM_ETH
Simon Glass64dcd252015-04-05 16:07:40 -0600433static int dw_eth_init(struct eth_device *dev, bd_t *bis)
434{
435 return _dw_eth_init(dev->priv, dev->enetaddr);
436}
437
438static int dw_eth_send(struct eth_device *dev, void *packet, int length)
439{
440 return _dw_eth_send(dev->priv, packet, length);
441}
442
443static int dw_eth_recv(struct eth_device *dev)
444{
Simon Glass75577ba2015-04-05 16:07:41 -0600445 uchar *packet;
446 int length;
447
448 length = _dw_eth_recv(dev->priv, &packet);
449 if (length == -EAGAIN)
450 return 0;
451 net_process_received_packet(packet, length);
452
453 _dw_free_pkt(dev->priv);
454
455 return 0;
Simon Glass64dcd252015-04-05 16:07:40 -0600456}
457
458static void dw_eth_halt(struct eth_device *dev)
459{
460 return _dw_eth_halt(dev->priv);
461}
462
463static int dw_write_hwaddr(struct eth_device *dev)
464{
465 return _dw_write_hwaddr(dev->priv, dev->enetaddr);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530466}
467
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400468int designware_initialize(ulong base_addr, u32 interface)
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530469{
470 struct eth_device *dev;
471 struct dw_eth_dev *priv;
472
473 dev = (struct eth_device *) malloc(sizeof(struct eth_device));
474 if (!dev)
475 return -ENOMEM;
476
477 /*
478 * Since the priv structure contains the descriptors which need a strict
479 * buswidth alignment, memalign is used to allocate memory
480 */
Ian Campbell1c848a22014-05-08 22:26:32 +0100481 priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
482 sizeof(struct dw_eth_dev));
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530483 if (!priv) {
484 free(dev);
485 return -ENOMEM;
486 }
487
488 memset(dev, 0, sizeof(struct eth_device));
489 memset(priv, 0, sizeof(struct dw_eth_dev));
490
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400491 sprintf(dev->name, "dwmac.%lx", base_addr);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530492 dev->iobase = (int)base_addr;
493 dev->priv = priv;
494
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530495 priv->dev = dev;
496 priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
497 priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
498 DW_DMA_BASE_OFFSET);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530499
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530500 dev->init = dw_eth_init;
501 dev->send = dw_eth_send;
502 dev->recv = dw_eth_recv;
503 dev->halt = dw_eth_halt;
504 dev->write_hwaddr = dw_write_hwaddr;
505
506 eth_register(dev);
507
Alexey Brodkin92a190a2014-01-22 20:54:06 +0400508 priv->interface = interface;
509
510 dw_mdio_init(dev->name, priv->mac_regs_p);
511 priv->bus = miiphy_get_dev_by_name(dev->name);
512
Simon Glass64dcd252015-04-05 16:07:40 -0600513 return dw_phy_init(priv, dev);
Vipin KUMAR5b1b1882010-06-29 10:53:34 +0530514}
Simon Glass75577ba2015-04-05 16:07:41 -0600515#endif
516
517#ifdef CONFIG_DM_ETH
518static int designware_eth_start(struct udevice *dev)
519{
520 struct eth_pdata *pdata = dev_get_platdata(dev);
521
522 return _dw_eth_init(dev->priv, pdata->enetaddr);
523}
524
525static int designware_eth_send(struct udevice *dev, void *packet, int length)
526{
527 struct dw_eth_dev *priv = dev_get_priv(dev);
528
529 return _dw_eth_send(priv, packet, length);
530}
531
Simon Glassa1ca92e2015-07-06 16:47:49 -0600532static int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
Simon Glass75577ba2015-04-05 16:07:41 -0600533{
534 struct dw_eth_dev *priv = dev_get_priv(dev);
535
536 return _dw_eth_recv(priv, packetp);
537}
538
539static int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
540 int length)
541{
542 struct dw_eth_dev *priv = dev_get_priv(dev);
543
544 return _dw_free_pkt(priv);
545}
546
547static void designware_eth_stop(struct udevice *dev)
548{
549 struct dw_eth_dev *priv = dev_get_priv(dev);
550
551 return _dw_eth_halt(priv);
552}
553
554static int designware_eth_write_hwaddr(struct udevice *dev)
555{
556 struct eth_pdata *pdata = dev_get_platdata(dev);
557 struct dw_eth_dev *priv = dev_get_priv(dev);
558
559 return _dw_write_hwaddr(priv, pdata->enetaddr);
560}
561
Bin Meng8b7ee662015-09-11 03:24:35 -0700562static int designware_eth_bind(struct udevice *dev)
563{
564#ifdef CONFIG_DM_PCI
565 static int num_cards;
566 char name[20];
567
568 /* Create a unique device name for PCI type devices */
569 if (device_is_on_pci_bus(dev)) {
570 sprintf(name, "eth_designware#%u", num_cards++);
571 device_set_name(dev, name);
572 }
573#endif
574
575 return 0;
576}
577
Simon Glass75577ba2015-04-05 16:07:41 -0600578static int designware_eth_probe(struct udevice *dev)
579{
580 struct eth_pdata *pdata = dev_get_platdata(dev);
581 struct dw_eth_dev *priv = dev_get_priv(dev);
Bin Mengf0dc73c2015-09-03 05:37:29 -0700582 u32 iobase = pdata->iobase;
Simon Glass75577ba2015-04-05 16:07:41 -0600583 int ret;
584
Bin Meng8b7ee662015-09-11 03:24:35 -0700585#ifdef CONFIG_DM_PCI
586 /*
587 * If we are on PCI bus, either directly attached to a PCI root port,
588 * or via a PCI bridge, fill in platdata before we probe the hardware.
589 */
590 if (device_is_on_pci_bus(dev)) {
591 pci_dev_t bdf = pci_get_bdf(dev);
592
593 dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
594 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
595 iobase = pci_mem_to_phys(bdf, iobase);
596
597 pdata->iobase = iobase;
598 pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
599 }
600#endif
601
Bin Mengf0dc73c2015-09-03 05:37:29 -0700602 debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
603 priv->mac_regs_p = (struct eth_mac_regs *)iobase;
604 priv->dma_regs_p = (struct eth_dma_regs *)(iobase + DW_DMA_BASE_OFFSET);
Simon Glass75577ba2015-04-05 16:07:41 -0600605 priv->interface = pdata->phy_interface;
606
607 dw_mdio_init(dev->name, priv->mac_regs_p);
608 priv->bus = miiphy_get_dev_by_name(dev->name);
609
610 ret = dw_phy_init(priv, dev);
611 debug("%s, ret=%d\n", __func__, ret);
612
613 return ret;
614}
615
Bin Meng5d2459f2015-10-07 21:32:38 -0700616static int designware_eth_remove(struct udevice *dev)
617{
618 struct dw_eth_dev *priv = dev_get_priv(dev);
619
620 free(priv->phydev);
621 mdio_unregister(priv->bus);
622 mdio_free(priv->bus);
623
624 return 0;
625}
626
Simon Glass75577ba2015-04-05 16:07:41 -0600627static const struct eth_ops designware_eth_ops = {
628 .start = designware_eth_start,
629 .send = designware_eth_send,
630 .recv = designware_eth_recv,
631 .free_pkt = designware_eth_free_pkt,
632 .stop = designware_eth_stop,
633 .write_hwaddr = designware_eth_write_hwaddr,
634};
635
636static int designware_eth_ofdata_to_platdata(struct udevice *dev)
637{
638 struct eth_pdata *pdata = dev_get_platdata(dev);
639 const char *phy_mode;
640
641 pdata->iobase = dev_get_addr(dev);
642 pdata->phy_interface = -1;
643 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
644 if (phy_mode)
645 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
646 if (pdata->phy_interface == -1) {
647 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
648 return -EINVAL;
649 }
650
651 return 0;
652}
653
654static const struct udevice_id designware_eth_ids[] = {
655 { .compatible = "allwinner,sun7i-a20-gmac" },
Marek Vasutb9628592015-07-25 18:38:44 +0200656 { .compatible = "altr,socfpga-stmmac" },
Simon Glass75577ba2015-04-05 16:07:41 -0600657 { }
658};
659
Marek Vasut9f76f102015-07-25 18:42:34 +0200660U_BOOT_DRIVER(eth_designware) = {
Simon Glass75577ba2015-04-05 16:07:41 -0600661 .name = "eth_designware",
662 .id = UCLASS_ETH,
663 .of_match = designware_eth_ids,
664 .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
Bin Meng8b7ee662015-09-11 03:24:35 -0700665 .bind = designware_eth_bind,
Simon Glass75577ba2015-04-05 16:07:41 -0600666 .probe = designware_eth_probe,
Bin Meng5d2459f2015-10-07 21:32:38 -0700667 .remove = designware_eth_remove,
Simon Glass75577ba2015-04-05 16:07:41 -0600668 .ops = &designware_eth_ops,
669 .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
670 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
671 .flags = DM_FLAG_ALLOC_PRIV_DMA,
672};
Bin Meng8b7ee662015-09-11 03:24:35 -0700673
674static struct pci_device_id supported[] = {
675 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
676 { }
677};
678
679U_BOOT_PCI_DEVICE(eth_designware, supported);
Simon Glass75577ba2015-04-05 16:07:41 -0600680#endif