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Wolfgang Denk46263f22013-07-28 22:12:45 +02001/*
Wolfgang Denk1b387ef2013-09-17 11:24:06 +02002 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
Wolfgang Denk46263f22013-07-28 22:12:45 +02003 */
wdenkc6097192002-11-03 00:24:07 +00004#include <config.h>
Stefan Roeseb36df562010-09-09 19:18:00 +02005#include <asm/ppc4xx.h>
wdenkc6097192002-11-03 00:24:07 +00006
7#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
8
9#include <ppc_asm.tmpl>
10#include <ppc_defs.h>
11
12#include <asm/cache.h>
13#include <asm/mmu.h>
14
15/******************************************************************************
16 * Function: ext_bus_cntlr_init
17 *
18 * Description: Configures EBC Controller and a few basic chip selects.
19 *
20 * CS0 is setup to get the Boot Flash out of the addresss range
21 * so that we may setup a stack. CS7 is setup so that we can
22 * access and reset the hardware watchdog.
23 *
24 * IMPORTANT: For pass1 this code must run from
25 * cache since you can not reliably change a peripheral banks
26 * timing register (pbxap) while running code from that bank.
27 * For ex., since we are running from ROM on bank 0, we can NOT
28 * execute the code that modifies bank 0 timings from ROM, so
29 * we run it from cache.
30 *
31 * Notes: Does NOT use the stack.
32 *****************************************************************************/
33 .section ".text"
34 .align 2
35 .globl ext_bus_cntlr_init
36 .type ext_bus_cntlr_init, @function
37ext_bus_cntlr_init:
38 mflr r0
39 /********************************************************************
40 * Prefetch entire ext_bus_cntrl_init function into the icache.
41 * This is necessary because we are going to change the same CS we
42 * are executing from. Otherwise a CPU lockup may occur.
43 *******************************************************************/
44 bl ..getAddr
45..getAddr:
46 mflr r3 /* get address of ..getAddr */
47
48 /* Calculate number of cache lines for this function */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
wdenkc6097192002-11-03 00:24:07 +000050 mtctr r4
51..ebcloop:
52 icbt r0, r3 /* prefetch cache line for addr in r3*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
wdenkc6097192002-11-03 00:24:07 +000054 bdnz ..ebcloop /* continue for $CTR cache lines */
55
56 /********************************************************************
57 * Delay to ensure all accesses to ROM are complete before changing
58 * bank 0 timings. 200usec should be enough.
59 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
60 *******************************************************************/
61 addis r3, 0, 0x0
62 ori r3, r3, 0xA000 /* wait 200us from reset */
63 mtctr r3
64..spinlp:
65 bdnz ..spinlp /* spin loop */
66
67 /********************************************************************
68 * Setup External Bus Controller (EBC).
69 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +020070 addi r3, 0, EBC0_CFG
71 mtdcr EBC0_CFGADDR, r3
wdenkc6097192002-11-03 00:24:07 +000072 addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */
73 ori r4, r4, 0x0 /* Drive CS with external master */
Stefan Roesed1c3b272009-09-09 16:25:29 +020074 mtdcr EBC0_CFGDATA, r4
wdenkc6097192002-11-03 00:24:07 +000075
76 /********************************************************************
77 * Change PCIINT signal to PerWE
78 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +020079 mfdcr r4, CPC0_CR1
wdenkc6097192002-11-03 00:24:07 +000080 ori r4, r4, 0x4000
Stefan Roesed1c3b272009-09-09 16:25:29 +020081 mtdcr CPC0_CR1, r4
wdenkc6097192002-11-03 00:24:07 +000082
83 /********************************************************************
84 * Memory Bank 0 (Flash Bank 0) initialization
85 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +020086 addi r3, 0, PB1AP
87 mtdcr EBC0_CFGADDR, r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088 addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
89 ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +020090 mtdcr EBC0_CFGDATA, r4
wdenkc6097192002-11-03 00:24:07 +000091
Stefan Roesed1c3b272009-09-09 16:25:29 +020092 addi r3, 0, PB0CR
93 mtdcr EBC0_CFGADDR, r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094 addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
95 ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +020096 mtdcr EBC0_CFGDATA, r4
wdenkc6097192002-11-03 00:24:07 +000097
98 /********************************************************************
99 * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
100 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200101 addi r3, 0, PB7AP
102 mtdcr EBC0_CFGADDR, r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103 addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
104 ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200105 mtdcr EBC0_CFGDATA, r4
wdenkc6097192002-11-03 00:24:07 +0000106
Stefan Roesed1c3b272009-09-09 16:25:29 +0200107 addi r3, 0, PB7CR
108 mtdcr EBC0_CFGADDR, r3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109 addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
110 ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
Stefan Roesed1c3b272009-09-09 16:25:29 +0200111 mtdcr EBC0_CFGDATA, r4
wdenkc6097192002-11-03 00:24:07 +0000112
113 /* We are all done */
114 mtlr r0 /* Restore link register */
115 blr /* Return to calling function */
116.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
117/* end ext_bus_cntlr_init() */
118
119/******************************************************************************
120 * Function: sdram_init
121 *
122 * Description: Configures SDRAM memory banks.
123 *
124 * Serial Presence Detect, "SPD," reads the SDRAM EEPROM
125 * via the IIC bus and then configures the SDRAM memory
126 * banks appropriately. If Auto Memory Configuration is
127 * is not used, it is assumed that a 4MB 11x8x2, non-ECC,
128 * SDRAM is soldered down.
129 *
130 * Notes: Expects that the stack is already setup.
131 *****************************************************************************/
132 .section ".text"
133 .align 2
134 .globl sdram_init
135 .type sdram_init, @function
136sdram_init:
137 /* save the return info on stack */
138 mflr r0 /* Get link register */
139 stwu r1, -8(r1) /* Save back chain and move SP */
140 stw r0, +12(r1) /* Save link register */
141
142 /*
143 * First call spd_sdram to try to init SDRAM according to the
144 * contents of the SPD EEPROM. If the SPD EEPROM is blank or
145 * erronious, spd_sdram returns 0 in R3.
146 */
wdenkdb2f721f2003-03-06 00:58:30 +0000147 li r3,0
wdenkc6097192002-11-03 00:24:07 +0000148 bl spd_sdram
149 addic. r3, r3, 0 /* Check for error, save dram size */
150 bne ..sdri_done /* If it worked, we're done... */
151
152 /********************************************************************
153 * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
154 * is the SMALLEST SDRAM size the 405 supports. We can do this
155 * because W7O boards have soldered on RAM, and there will always
156 * be some amount present. If we were using DIMMs, we should hang
157 * the board instead, since it doesn't have any RAM to continue
158 * running with.
159 *******************************************************************/
160
161 /*
162 * Disable memory controller to allow
163 * values to be changed.
164 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200165 addi r3, 0, SDRAM0_CFG
Stefan Roesed1c3b272009-09-09 16:25:29 +0200166 mtdcr SDRAM0_CFGADDR, r3
wdenkc6097192002-11-03 00:24:07 +0000167 addis r4, 0, 0x0
168 ori r4, r4, 0x0
Stefan Roesed1c3b272009-09-09 16:25:29 +0200169 mtdcr SDRAM0_CFGDATA, r4
wdenkc6097192002-11-03 00:24:07 +0000170
171 /*
172 * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
173 * All other banks are disabled.
174 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200175 addi r3, 0, SDRAM0_B0CR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200176 mtdcr SDRAM0_CFGADDR, r3
wdenkc6097192002-11-03 00:24:07 +0000177 addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
178 ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200179 mtdcr SDRAM0_CFGDATA, r4
wdenkc6097192002-11-03 00:24:07 +0000180
181 /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
182 addi r4, 0, 0 /* Zero the data reg */
183
184 addi r3, r3, 4 /* Point to MB1CF reg */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200185 mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
186 mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
wdenkc6097192002-11-03 00:24:07 +0000187
188 addi r3, r3, 4 /* Point to MB2CF reg */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200189 mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
190 mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
wdenkc6097192002-11-03 00:24:07 +0000191
192 addi r3, r3, 4 /* Point to MB3CF reg */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200193 mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
194 mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
wdenkc6097192002-11-03 00:24:07 +0000195
196 /********************************************************************
197 * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
198 * To set the appropriate timings, we assume sdram is
199 * 100MHz (pc100 compliant).
200 *******************************************************************/
201
202 /*
203 * Set up SDTR1
204 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200205 addi r3, 0, SDRAM0_TR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200206 mtdcr SDRAM0_CFGADDR, r3
wdenkc6097192002-11-03 00:24:07 +0000207 addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
208 ori r4, r4, 0x400D
Stefan Roesed1c3b272009-09-09 16:25:29 +0200209 mtdcr SDRAM0_CFGDATA, r4
wdenkc6097192002-11-03 00:24:07 +0000210
211 /*
212 * Set RTR
213 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200214 addi r3, 0, SDRAM0_RTR
Stefan Roesed1c3b272009-09-09 16:25:29 +0200215 mtdcr SDRAM0_CFGADDR, r3
wdenkc6097192002-11-03 00:24:07 +0000216 addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200217 mtdcr SDRAM0_CFGDATA, r4
wdenkc6097192002-11-03 00:24:07 +0000218
219 /********************************************************************
220 * Delay to ensure 200usec have elapsed since reset. Assume worst
221 * case that the core is running 200Mhz:
222 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
223 *******************************************************************/
224 addis r3, 0, 0x0000
225 ori r3, r3, 0xA000 /* Wait 200us from reset */
226 mtctr r3
227..spinlp2:
228 bdnz ..spinlp2 /* spin loop */
229
230 /********************************************************************
231 * Set memory controller options reg, MCOPT1.
232 *******************************************************************/
Stefan Roese95b602b2009-09-24 13:59:57 +0200233 addi r3, 0, SDRAM0_CFG
Stefan Roesed1c3b272009-09-09 16:25:29 +0200234 mtdcr SDRAM0_CFGADDR, r3
wdenkc6097192002-11-03 00:24:07 +0000235 addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
236 ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200237 mtdcr SDRAM0_CFGDATA, r4 /* EMDULR=1 */
wdenkc6097192002-11-03 00:24:07 +0000238
239..sdri_done:
240 /* restore and return */
241 lwz r0, +12(r1) /* Get saved link register */
242 addi r1, r1, +8 /* Remove frame from stack */
243 mtlr r0 /* Restore link register */
244 blr /* Return to calling function */
245.Lfe1: .size sdram_init,.Lfe1-sdram_init
246/* end sdram_init() */