blob: 1cfb2c22795edad5177eccd3bfea9ec8e753a092 [file] [log] [blame]
Mingkai Hua8d97582013-07-04 17:33:43 +08001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
York Sun3aab0cd2013-08-12 14:57:12 -07004 * SPDX-License-Identifier: GPL-2.0+
Mingkai Hua8d97582013-07-04 17:33:43 +08005 */
6
7/*
8 * C29XPCIE board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#define CONFIG_PHYS_64BIT
15
16#ifdef CONFIG_C29XPCIE
17#define CONFIG_PPC_C29X
18#endif
19
20#ifdef CONFIG_SPIFLASH
21#define CONFIG_RAMBOOT_SPIFLASH
22#define CONFIG_SYS_TEXT_BASE 0x11000000
23#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
24#endif
25
26#ifndef CONFIG_SYS_TEXT_BASE
27#define CONFIG_SYS_TEXT_BASE 0xeff80000
28#endif
29
30#ifndef CONFIG_RESET_VECTOR_ADDRESS
31#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
32#endif
33
34#ifndef CONFIG_SYS_MONITOR_BASE
35#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
36#endif
37
38/* High Level Configuration Options */
39#define CONFIG_BOOKE /* BOOKE */
40#define CONFIG_E500 /* BOOKE e500 family */
41#define CONFIG_MPC85xx
42#define CONFIG_FSL_IFC /* Enable IFC Support */
43#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
44
45#define CONFIG_PCI /* Enable PCI/PCIE */
46#ifdef CONFIG_PCI
47#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
48#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
49#define CONFIG_PCI_INDIRECT_BRIDGE
50#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
51#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
52
53#define CONFIG_CMD_NET
54#define CONFIG_CMD_PCI
55
56#define CONFIG_E1000
57
58/*
59 * PCI Windows
60 * Memory space is mapped 1-1, but I/O space must start from 0.
61 */
62/* controller 1, Slot 1, tgtid 1, Base address a000 */
63#define CONFIG_SYS_PCIE1_NAME "Slot 1"
64#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
65#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
66#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
67#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
68#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
69#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
70#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
71#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
72
73#define CONFIG_PCI_PNP /* do pci plug-and-play */
74
75#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
76#define CONFIG_DOS_PARTITION
77#endif
78
79#define CONFIG_FSL_LAW /* Use common FSL init code */
80#define CONFIG_TSEC_ENET
81#define CONFIG_ENV_OVERWRITE
82
83#define CONFIG_DDR_CLK_FREQ 100000000
84#define CONFIG_SYS_CLK_FREQ 66666666
85
86#define CONFIG_HWCONFIG
87
88/*
89 * These can be toggled for performance analysis, otherwise use default.
90 */
91#define CONFIG_L2_CACHE /* toggle L2 cache */
92#define CONFIG_BTB /* toggle branch predition */
93
94#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
95
96#define CONFIG_ENABLE_36BIT_PHYS
97
98#define CONFIG_ADDR_MAP 1
99#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
100
101#define CONFIG_SYS_MEMTEST_START 0x00200000
102#define CONFIG_SYS_MEMTEST_END 0x00400000
103#define CONFIG_PANIC_HANG
104
105/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700106#define CONFIG_SYS_FSL_DDR3
Mingkai Hua8d97582013-07-04 17:33:43 +0800107#define CONFIG_DDR_SPD
108#define CONFIG_SYS_SPD_BUS_NUM 0
109#define SPD_EEPROM_ADDRESS 0x50
110#define CONFIG_SYS_DDR_RAW_TIMING
111
112/* DDR ECC Setup*/
113#define CONFIG_DDR_ECC
114#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
115#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
116
117#define CONFIG_SYS_SDRAM_SIZE 512
118#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
119#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
120
121#define CONFIG_DIMM_SLOTS_PER_CTLR 1
122#define CONFIG_CHIP_SELECTS_PER_CTRL 1
123
124#define CONFIG_SYS_CCSRBAR 0xffe00000
125#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
126
127/* Platform SRAM setting */
128#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
129#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
130 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
131#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
132
133/*
134 * IFC Definitions
135 */
136/* NOR Flash on IFC */
137#define CONFIG_SYS_FLASH_BASE 0xec000000
138#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
139
140#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
141
142#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
143#define CONFIG_SYS_MAX_FLASH_BANKS 1
144
145#define CONFIG_SYS_FLASH_QUIET_TEST
146#define CONFIG_FLASH_SHOW_PROGRESS 45
147#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
148#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
149
150/* 16Bit NOR Flash - S29GL512S10TFI01 */
151#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
152 CSPR_PORT_SIZE_16 | \
153 CSPR_MSEL_NOR | \
154 CSPR_V)
155#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
156#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
Po Liuac2785c2013-08-21 14:22:18 +0800157
Mingkai Hua8d97582013-07-04 17:33:43 +0800158#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
159 FTIM0_NOR_TEADC(0x5) | \
160 FTIM0_NOR_TEAHC(0x5))
Po Liuac2785c2013-08-21 14:22:18 +0800161#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
162 FTIM1_NOR_TRAD_NOR(0x1A) |\
163 FTIM1_NOR_TSEQRAD_NOR(0x13))
Mingkai Hua8d97582013-07-04 17:33:43 +0800164#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
165 FTIM2_NOR_TCH(0x4) | \
Po Liuac2785c2013-08-21 14:22:18 +0800166 FTIM2_NOR_TWPH(0x0E) | \
Mingkai Hua8d97582013-07-04 17:33:43 +0800167 FTIM2_NOR_TWP(0x1c))
168#define CONFIG_SYS_NOR_FTIM3 0x0
169
170/* CFI for NOR Flash */
171#define CONFIG_FLASH_CFI_DRIVER
172#define CONFIG_SYS_FLASH_CFI
173#define CONFIG_SYS_FLASH_EMPTY_INFO
174#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
175
176/* NAND Flash on IFC */
177#define CONFIG_NAND_FSL_IFC
178#define CONFIG_SYS_NAND_BASE 0xff800000
179#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
180
181#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
182
183#define CONFIG_SYS_MAX_NAND_DEVICE 1
184#define CONFIG_MTD_NAND_VERIFY_WRITE
185#define CONFIG_CMD_NAND
186#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
187
188/* 8Bit NAND Flash - K9F1G08U0B */
189#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
190 | CSPR_PORT_SIZE_8 \
191 | CSPR_MSEL_NAND \
192 | CSPR_V)
193#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
Prabhakar Kushwahaaffd5202013-10-04 10:05:50 +0530194#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
Mingkai Hua8d97582013-07-04 17:33:43 +0800195#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
196 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
197 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
Prabhakar Kushwahaaffd5202013-10-04 10:05:50 +0530198 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
199 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
200 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
201 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
Mingkai Hua8d97582013-07-04 17:33:43 +0800202#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
203 FTIM0_NAND_TWP(0x0c) | \
204 FTIM0_NAND_TWCHT(0x08) | \
205 FTIM0_NAND_TWH(0x06))
206#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
207 FTIM1_NAND_TWBE(0x1d) | \
208 FTIM1_NAND_TRR(0x08) | \
209 FTIM1_NAND_TRP(0x0c))
210#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
211 FTIM2_NAND_TREH(0x0a) | \
212 FTIM2_NAND_TWHRE(0x18))
213#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
214
215#define CONFIG_SYS_NAND_DDR_LAW 11
216
217/* Set up IFC registers for boot location NOR/NAND */
218#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
219#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
220#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
221#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
222#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
223#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
224#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
225#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
226#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
227#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
Prabhakar Kushwahaaffd5202013-10-04 10:05:50 +0530228#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
Mingkai Hua8d97582013-07-04 17:33:43 +0800229#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
230#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
231#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
232#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
233
234/* CPLD on IFC, selected by CS2 */
235#define CONFIG_SYS_CPLD_BASE 0xffdf0000
236#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
237 | CONFIG_SYS_CPLD_BASE)
238
239#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
240 | CSPR_PORT_SIZE_8 \
241 | CSPR_MSEL_GPCM \
242 | CSPR_V)
243#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
244#define CONFIG_SYS_CSOR2 0x0
245/* CPLD Timing parameters for IFC CS2 */
246#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
247 FTIM0_GPCM_TEADC(0x0e) | \
248 FTIM0_GPCM_TEAHC(0x0e))
249#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
250 FTIM1_GPCM_TRAD(0x1f))
251#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
252 FTIM2_GPCM_TCH(0x0) | \
253 FTIM2_GPCM_TWP(0x1f))
254#define CONFIG_SYS_CS2_FTIM3 0x0
255
256#if defined(CONFIG_RAMBOOT_SPIFLASH)
257#define CONFIG_SYS_RAMBOOT
258#define CONFIG_SYS_EXTRA_ENV_RELOC
259#endif
260
261#define CONFIG_BOARD_EARLY_INIT_R
262
263#define CONFIG_SYS_INIT_RAM_LOCK
264#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
265#define CONFIG_SYS_INIT_RAM_END 0x00004000
266
267#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \
268 - GENERATED_GBL_DATA_SIZE)
269#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
270
271#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
272#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
273
274/* Serial Port */
275#define CONFIG_CONS_INDEX 1
276#define CONFIG_SYS_NS16550
277#define CONFIG_SYS_NS16550_SERIAL
278#define CONFIG_SYS_NS16550_REG_SIZE 1
279#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
280
281#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
282#define CONFIG_SYS_CONSOLE_IS_IN_ENV
283
284#define CONFIG_SYS_BAUDRATE_TABLE \
285 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
286
287#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
288#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
289
290/* Use the HUSH parser */
291#define CONFIG_SYS_HUSH_PARSER
292
293/*
294 * Pass open firmware flat tree
295 */
296#define CONFIG_OF_LIBFDT
297#define CONFIG_OF_BOARD_SETUP
298#define CONFIG_OF_STDOUT_VIA_ALIAS
299
300/* new uImage format support */
301#define CONFIG_FIT
302#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
303
304#define CONFIG_SYS_I2C
305#define CONFIG_SYS_I2C_FSL
306#define CONFIG_SYS_FSL_I2C_SPEED 400000
307#define CONFIG_SYS_FSL_I2C2_SPEED 400000
308#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
309#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
310#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
311#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
312
313/* I2C EEPROM */
314/* enable read and write access to EEPROM */
315#define CONFIG_CMD_EEPROM
316#define CONFIG_SYS_I2C_MULTI_EEPROMS
317#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
318#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
319#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
320
321#define CONFIG_CMD_I2C
322
323/* eSPI - Enhanced SPI */
324#define CONFIG_FSL_ESPI
325#define CONFIG_SPI_FLASH
326#define CONFIG_SPI_FLASH_SPANSION
327#define CONFIG_SPI_FLASH_EON
328#define CONFIG_CMD_SF
329#define CONFIG_SF_DEFAULT_SPEED 10000000
330#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
331
332#ifdef CONFIG_TSEC_ENET
333#define CONFIG_NET_MULTI
334#define CONFIG_MII /* MII PHY management */
335#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
336#define CONFIG_TSEC1 1
337#define CONFIG_TSEC1_NAME "eTSEC1"
338#define CONFIG_TSEC2 1
339#define CONFIG_TSEC2_NAME "eTSEC2"
340
341/* Default mode is RGMII mode */
342#define TSEC1_PHY_ADDR 0
343#define TSEC2_PHY_ADDR 2
344
345#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
346#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
347
348#define CONFIG_ETHPRIME "eTSEC1"
349
350#define CONFIG_PHY_GIGE
351#endif /* CONFIG_TSEC_ENET */
352
353/*
354 * Environment
355 */
356#if defined(CONFIG_SYS_RAMBOOT)
357#if defined(CONFIG_RAMBOOT_SPIFLASH)
358#define CONFIG_ENV_IS_IN_SPI_FLASH
359#define CONFIG_ENV_SPI_BUS 0
360#define CONFIG_ENV_SPI_CS 0
361#define CONFIG_ENV_SPI_MAX_HZ 10000000
362#define CONFIG_ENV_SPI_MODE 0
363#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
364#define CONFIG_ENV_SECT_SIZE 0x10000
365#define CONFIG_ENV_SIZE 0x2000
366#endif
367#else
368#define CONFIG_ENV_IS_IN_FLASH
369#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
370#define CONFIG_ENV_ADDR 0xfff80000
371#else
372#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
373#endif
374#define CONFIG_ENV_SIZE 0x2000
375#define CONFIG_ENV_SECT_SIZE 0x20000
376#endif
377
378#define CONFIG_LOADS_ECHO
379#define CONFIG_SYS_LOADS_BAUD_CHANGE
380
381/*
382 * Command line configuration.
383 */
384#include <config_cmd_default.h>
385
386#define CONFIG_CMD_ERRATA
387#define CONFIG_CMD_ELF
388#define CONFIG_CMD_IRQ
389#define CONFIG_CMD_MII
390#define CONFIG_CMD_PING
391#define CONFIG_CMD_SETEXPR
392#define CONFIG_CMD_REGINFO
393
394/*
395 * Miscellaneous configurable options
396 */
397#define CONFIG_SYS_LONGHELP /* undef to save memory */
398#define CONFIG_CMDLINE_EDITING /* Command-line editing */
399#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
400#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Mingkai Hua8d97582013-07-04 17:33:43 +0800401
402#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
403#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
404 /* Print Buffer Size */
405#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
406#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Mingkai Hua8d97582013-07-04 17:33:43 +0800407
408/*
409 * For booting Linux, the board info and command line data
410 * have to be in the first 64 MB of memory, since this is
411 * the maximum mapped by the Linux kernel during initialization.
412 */
413#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
414#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
415
416/*
417 * Environment Configuration
418 */
419
420#ifdef CONFIG_TSEC_ENET
421#define CONFIG_HAS_ETH0
422#define CONFIG_HAS_ETH1
423#endif
424
425#define CONFIG_ROOTPATH "/opt/nfsroot"
426#define CONFIG_BOOTFILE "uImage"
427#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
428
429/* default location for tftp and bootm */
430#define CONFIG_LOADADDR 1000000
431
432#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
433
434#define CONFIG_BAUDRATE 115200
435
Po Liu9c25ee62013-09-26 09:40:11 +0800436#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
437
Mingkai Hua8d97582013-07-04 17:33:43 +0800438#define CONFIG_EXTRA_ENV_SETTINGS \
439 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
440 "netdev=eth0\0" \
441 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
442 "loadaddr=1000000\0" \
443 "consoledev=ttyS0\0" \
444 "ramdiskaddr=2000000\0" \
445 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
446 "fdtaddr=c00000\0" \
447 "fdtfile=name/of/device-tree.dtb\0" \
448 "othbootargs=ramdisk_size=600000\0" \
449
450#define CONFIG_RAMBOOTCOMMAND \
451 "setenv bootargs root=/dev/ram rw " \
452 "console=$consoledev,$baudrate $othbootargs; " \
453 "tftp $ramdiskaddr $ramdiskfile;" \
454 "tftp $loadaddr $bootfile;" \
455 "tftp $fdtaddr $fdtfile;" \
456 "bootm $loadaddr $ramdiskaddr $fdtaddr"
457
458#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
459
460#endif /* __CONFIG_H */