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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
3 *
4 * This file is based on similar values for other boards found in
5 * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
wdenke2211742002-11-02 23:30:20 +00008 */
9
10/*
11 * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
12 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
wdenke2211742002-11-02 23:30:20 +000017/*-----------------------------------------------------------------------
18 * High Level Configuration Options
19 * (easy to change)
20 */
21
22#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
23#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */
24
Wolfgang Denk2ae18242010-10-06 09:05:45 +020025#define CONFIG_SYS_TEXT_BASE 0xffb00000
26
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050027#define CONFIG_CPM2 1 /* Has a CPM2 */
28
wdenke2211742002-11-02 23:30:20 +000029/*-----------------------------------------------------------------------
30 * select serial console configuration
31 *
32 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
33 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
34 * for SCC).
35 *
36 * if CONFIG_CONS_NONE is defined, then the serial console routines must
37 * defined elsewhere (for example, on the cogent platform, there are serial
38 * ports on the motherboard which are used for the serial console - see
39 * cogent/cma101/serial.[ch]).
40 */
41#define CONFIG_CONS_ON_SMC /* define if console on SMC */
42#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
43#undef CONFIG_CONS_NONE /* define if console on something else */
44#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
45
46/*-----------------------------------------------------------------------
47 * select ethernet configuration
48 *
49 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
50 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
51 * for FCC)
52 *
53 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050054 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenke2211742002-11-02 23:30:20 +000055 */
56#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
57#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
58#undef CONFIG_ETHER_NONE /* define if ether on something else */
59#define CONFIG_ETHER_INDEX 3 /* which channel for ether */
60
61#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
62
63/*-----------------------------------------------------------------------
64 * - Rx-CLK is CLK14
65 * - Tx-CLK is CLK16
66 * - Select bus for bd/buffers (see 28-13)
67 * - Half duplex
68 */
Mike Frysingerd4590da2011-10-17 05:38:58 +000069# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
70# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071# define CONFIG_SYS_CPMFCR_RAMTYPE 0
72# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenke2211742002-11-02 23:30:20 +000073
74#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
75
76/* other options */
77
78#define CONFIG_8260_CLKIN 66666666 /* in Hz */
79#define CONFIG_BAUDRATE 19200
80
Jon Loeliger7be044e2007-07-09 21:24:19 -050081/*
82 * BOOTP options
83 */
84#define CONFIG_BOOTP_SUBNETMASK
85#define CONFIG_BOOTP_GATEWAY
86#define CONFIG_BOOTP_HOSTNAME
87#define CONFIG_BOOTP_BOOTPATH
88#define CONFIG_BOOTP_BOOTFILESIZE
wdenke2211742002-11-02 23:30:20 +000089
90/*
91 * select i2c support configuration
92 *
93 * Supported configurations are {none, software, hardware} drivers.
94 * If the software driver is chosen, there are some additional
95 * configuration items that the driver uses to drive the port pins.
96 */
Heiko Schocherea818db2013-01-29 08:53:15 +010097#define CONFIG_SYS_I2C
98#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
99#define CONFIG_SYS_I2C_SOFT_SPEED 400000
100#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
wdenke2211742002-11-02 23:30:20 +0000101/*
102 * Software (bit-bang) I2C driver configuration
103 */
wdenke2211742002-11-02 23:30:20 +0000104#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
105#define I2C_ACTIVE (iop->pdir |= 0x00010000)
106#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
107#define I2C_READ ((iop->pdat & 0x00010000) != 0)
108#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
109 else iop->pdat &= ~0x00010000
110#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
111 else iop->pdat &= ~0x00020000
112#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
wdenke2211742002-11-02 23:30:20 +0000113
wdenke2211742002-11-02 23:30:20 +0000114
Jon Loeliger348f2582007-07-08 13:46:18 -0500115/*
116 * Command line configuration.
117 */
118#include <config_cmd_default.h>
wdenke2211742002-11-02 23:30:20 +0000119
120
121#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
122#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
123#define CONFIG_BOOTARGS "root=/dev/ram rw"
124
Jon Loeliger348f2582007-07-08 13:46:18 -0500125#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000126#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
127#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
128#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
129#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
130#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
131#endif
132
133#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
134
135/*-----------------------------------------------------------------------
136 * Miscellaneous configurable options
137 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger348f2582007-07-08 13:46:18 -0500139#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000141#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000143#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
145#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
146#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
149#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000150
151#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */
152 /* for versions < 2.4.5-pre5 */
153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_RESET_ADDRESS 0x04400000
wdenke2211742002-11-02 23:30:20 +0000157
158#define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */
159
160/*-----------------------------------------------------------------------
161 * For booting Linux, the board info and command line data
162 * have to be in the first 8 MB of memory, since this is
163 * the maximum mapped by the Linux kernel during initialization.
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000166
167/*-----------------------------------------------------------------------
168 * Start addresses for the final memory configuration (Setup by the
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169 * startup code). Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0.
wdenke2211742002-11-02 23:30:20 +0000170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_SDRAM_BASE 0x00000000
172#define CONFIG_SYS_FLASH_BASE 0xFF800000
wdenke2211742002-11-02 23:30:20 +0000173
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200174#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
176#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000177
178/*-----------------------------------------------------------------------
179 * FLASH organization
180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
182#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
183#define CONFIG_SYS_MAX_FLASH_SIZE (CONFIG_SYS_MAX_FLASH_SECT * 0x10000) /* 4 MB */
wdenke2211742002-11-02 23:30:20 +0000184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */
186#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenke2211742002-11-02 23:30:20 +0000187
188/* Environment in FLASH, there is little space left in Serial EEPROM */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200189#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200190#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x10000) /* 2. sector */
wdenke2211742002-11-02 23:30:20 +0000192
193
194/*-----------------------------------------------------------------------
195 * Hard Reset Configuration Words
196 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenke2211742002-11-02 23:30:20 +0000198 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenke2211742002-11-02 23:30:20 +0000200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\
wdenke2211742002-11-02 23:30:20 +0000202 ( HRCW_L2CPC10 | HRCW_ISB110 ) |\
203 ( HRCW_MMR11 | HRCW_APPC10 ) |\
204 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
205 ) /* 0x14863245 */
206
207/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_HRCW_SLAVE1 0
209#define CONFIG_SYS_HRCW_SLAVE2 0
210#define CONFIG_SYS_HRCW_SLAVE3 0
211#define CONFIG_SYS_HRCW_SLAVE4 0
212#define CONFIG_SYS_HRCW_SLAVE5 0
213#define CONFIG_SYS_HRCW_SLAVE6 0
214#define CONFIG_SYS_HRCW_SLAVE7 0
wdenke2211742002-11-02 23:30:20 +0000215
216/*-----------------------------------------------------------------------
217 * Internal Memory Mapped Register
218 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_IMMR 0xFF000000 /* We keep original value */
wdenke2211742002-11-02 23:30:20 +0000220
221/*-----------------------------------------------------------------------
222 * Definitions for initial stack pointer and data area (in DPRAM)
223 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200225#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200226#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000228
229/*-----------------------------------------------------------------------
wdenke2211742002-11-02 23:30:20 +0000230 * Cache Configuration
231 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger348f2582007-07-08 13:46:18 -0500233#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000235#endif
236
237/*-----------------------------------------------------------------------
238 * HIDx - Hardware Implementation-dependent Registers 2-11
239 *-----------------------------------------------------------------------
240 * HID0 also contains cache control.
241 *
242 * HID1 has only read-only information - nothing to set.
243 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200245 HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
247#define CONFIG_SYS_HID2 0
wdenke2211742002-11-02 23:30:20 +0000248
249/*-----------------------------------------------------------------------
250 * RMR - Reset Mode Register 5-5
251 *-----------------------------------------------------------------------
252 * turn on Checkstop Reset Enable
253 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_RMR RMR_CSRE
wdenke2211742002-11-02 23:30:20 +0000255
256/*-----------------------------------------------------------------------
257 * BCR - Bus Configuration 4-25
258 *-----------------------------------------------------------------------
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_BCR 0xA01C0000
wdenke2211742002-11-02 23:30:20 +0000261
262/*-----------------------------------------------------------------------
263 * SIUMCR - SIU Module Configuration 4-31
264 *-----------------------------------------------------------------------
265 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_SIUMCR 0X4205C000
wdenke2211742002-11-02 23:30:20 +0000267
268/*-----------------------------------------------------------------------
269 * SYPCR - System Protection Control 4-35
270 * SYPCR can only be written once after reset!
271 *-----------------------------------------------------------------------
272 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
273 */
274#if defined (CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenke2211742002-11-02 23:30:20 +0000276 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
277#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenke2211742002-11-02 23:30:20 +0000279 SYPCR_SWRI|SYPCR_SWP)
280#endif /* CONFIG_WATCHDOG */
281
282/*-----------------------------------------------------------------------
283 * TMCNTSC - Time Counter Status and Control 4-40
284 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
285 * and enable Time Counter
286 *-----------------------------------------------------------------------
287 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenke2211742002-11-02 23:30:20 +0000289
290/*-----------------------------------------------------------------------
291 * PISCR - Periodic Interrupt Status and Control 4-42
292 *-----------------------------------------------------------------------
293 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
294 * Periodic timer
295 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenke2211742002-11-02 23:30:20 +0000297
298/*-----------------------------------------------------------------------
299 * SCCR - System Clock Control 9-8
300 *-----------------------------------------------------------------------
301 * Ensure DFBRG is Divide by 16
302 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_SCCR 0
wdenke2211742002-11-02 23:30:20 +0000304
305/*-----------------------------------------------------------------------
306 * RCCR - RISC Controller Configuration 13-7
307 *-----------------------------------------------------------------------
308 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_RCCR 0
wdenke2211742002-11-02 23:30:20 +0000310
311/*-----------------------------------------------------------------------
312 * Init Memory Controller:
313 *
314 * Bank Bus Machine PortSz Device
315 * ---- --- ------- ------ ------
316 * 0 60x GPCM 64 bit FLASH
317 * 1 60x SDRAM 64 bit SDRAM
318 */
319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) | 0x0801)
321#define CONFIG_SYS_OR0_PRELIM 0xFF800882
322#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
323#define CONFIG_SYS_OR1_PRELIM 0xF8002CD0
wdenke2211742002-11-02 23:30:20 +0000324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_PSDMR 0x404A241A
326#define CONFIG_SYS_MPTPR 0x00007400
327#define CONFIG_SYS_PSRT 0x00000007
wdenke2211742002-11-02 23:30:20 +0000328
329#endif /* __CONFIG_H */