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goda.yusukec2042f52008-01-25 20:46:36 +09001/*
2 * Configuation settings for the Renesas Solutions Migo-R board
3 *
4 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
goda.yusukec2042f52008-01-25 20:46:36 +09007 */
8
9#ifndef __MIGO_R_H
10#define __MIGO_R_H
11
12#undef DEBUG
13#define CONFIG_SH 1
14#define CONFIG_SH4 1
15#define CONFIG_CPU_SH7722 1
16#define CONFIG_MIGO_R 1
17
18#define CONFIG_CMD_LOADB
19#define CONFIG_CMD_LOADS
20#define CONFIG_CMD_FLASH
21#define CONFIG_CMD_MEMORY
22#define CONFIG_CMD_NET
23#define CONFIG_CMD_PING
24#define CONFIG_CMD_NFS
goda.yusukec2042f52008-01-25 20:46:36 +090025#define CONFIG_CMD_SDRAM
Mike Frysingerbdab39d2009-01-28 19:08:14 -050026#define CONFIG_CMD_SAVEENV
goda.yusukec2042f52008-01-25 20:46:36 +090027
28#define CONFIG_BAUDRATE 115200
29#define CONFIG_BOOTDELAY 3
30#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
goda.yusukec2042f52008-01-25 20:46:36 +090031
32#define CONFIG_VERSION_VARIABLE
33#undef CONFIG_SHOW_BOOT_PROGRESS
34
35/* SMC9111 */
Ben Warren7194ab82009-10-04 22:37:03 -070036#define CONFIG_SMC91111
goda.yusukec2042f52008-01-25 20:46:36 +090037#define CONFIG_SMC91111_BASE (0xB0000000)
38
39/* MEMORY */
40#define MIGO_R_SDRAM_BASE (0x8C000000)
41#define MIGO_R_FLASH_BASE_1 (0xA0000000)
42#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024)
43
Nobuhiro Iwamatsu8cd73792011-01-17 20:43:40 +090044#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
47#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
48#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
49#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
50#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
goda.yusukec2042f52008-01-25 20:46:36 +090051
52/* SCIF */
Jean-Christophe PLAGNIOL-VILLARD6c58a032008-08-13 01:40:38 +020053#define CONFIG_SCIF_CONSOLE 1
goda.yusukec2042f52008-01-25 20:46:36 +090054#define CONFIG_CONS_SCIF0 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress display of console
goda.yusukec2042f52008-01-25 20:46:36 +090056 information at boot */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
58#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
goda.yusukec2042f52008-01-25 20:46:36 +090059
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE)
61#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
goda.yusukec2042f52008-01-25 20:46:36 +090062
63/* Enable alternate, more extensive, memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#undef CONFIG_SYS_ALT_MEMTEST
goda.yusukec2042f52008-01-25 20:46:36 +090065/* Scratch address used by the alternate memory test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#undef CONFIG_SYS_MEMTEST_SCRATCH
goda.yusukec2042f52008-01-25 20:46:36 +090067
68/* Enable temporary baudrate change while serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#undef CONFIG_SYS_LOADS_BAUD_CHANGE
goda.yusukec2042f52008-01-25 20:46:36 +090070
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE)
goda.yusukec2042f52008-01-25 20:46:36 +090072/* maybe more, but if so u-boot doesn't know about it... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
goda.yusukec2042f52008-01-25 20:46:36 +090074/* default load address for scripts ?!? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
goda.yusukec2042f52008-01-25 20:46:36 +090076
77/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1)
goda.yusukec2042f52008-01-25 20:46:36 +090079/* Monitor size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
goda.yusukec2042f52008-01-25 20:46:36 +090081/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
goda.yusukec2042f52008-01-25 20:46:36 +090084
85/* FLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020087#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#undef CONFIG_SYS_FLASH_QUIET_TEST
goda.yusukec2042f52008-01-25 20:46:36 +090089/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_FLASH_EMPTY_INFO
goda.yusukec2042f52008-01-25 20:46:36 +090091/* Physical start address of Flash memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1)
goda.yusukec2042f52008-01-25 20:46:36 +090093/* Max number of sectors on each Flash chip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_MAX_FLASH_SECT 512
goda.yusukec2042f52008-01-25 20:46:36 +090095
96/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_MAX_FLASH_BANKS 1
98#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) }
goda.yusukec2042f52008-01-25 20:46:36 +090099
100/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
goda.yusukec2042f52008-01-25 20:46:36 +0900102/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
goda.yusukec2042f52008-01-25 20:46:36 +0900104/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
goda.yusukec2042f52008-01-25 20:46:36 +0900106/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
goda.yusukec2042f52008-01-25 20:46:36 +0900108
109/* Use hardware flash sectors protection instead of U-Boot software protection */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#undef CONFIG_SYS_FLASH_PROTECTION
111#undef CONFIG_SYS_DIRECT_FLASH_TFTP
goda.yusukec2042f52008-01-25 20:46:36 +0900112
113/* ENV setting */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200114#define CONFIG_ENV_IS_IN_FLASH
goda.yusukec2042f52008-01-25 20:46:36 +0900115#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200116#define CONFIG_ENV_SECT_SIZE (128 * 1024)
117#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
119/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
120#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200121#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
goda.yusukec2042f52008-01-25 20:46:36 +0900122
123/* Board Clock */
124#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +0900125#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
126#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +0200127#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
goda.yusukec2042f52008-01-25 20:46:36 +0900128
129#endif /* __MIGO_R_H */