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wdenk0e6d7982004-03-14 00:07:33 +00001/*
2 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
3 *
Stefan Roese8a316c92005-08-01 16:49:12 +02004 * (C) Copyright 2005
5 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
wdenk0e6d7982004-03-14 00:07:33 +00008 */
9
10/************************************************************************
wdenk42dfe7a2004-03-14 22:25:36 +000011 * 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com>
wdenk0e6d7982004-03-14 00:07:33 +000012 * Adapted to current Das U-Boot source
13 ***********************************************************************/
14
15
16/************************************************************************
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020017 * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
wdenk0e6d7982004-03-14 00:07:33 +000018 ***********************************************************************/
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23/*-----------------------------------------------------------------------
24 * High Level Configuration Options
25 *----------------------------------------------------------------------*/
26#define CONFIG_OCOTEA 1 /* Board is ebony */
Stefan Roese846b0dd2005-08-08 12:42:22 +020027#define CONFIG_440GX 1 /* Specifc GX support */
Grzegorz Bernackiefa35cf2007-06-15 11:19:28 +020028#define CONFIG_440 1 /* ... PPC440 family */
wdenk0e6d7982004-03-14 00:07:33 +000029#define CONFIG_4xx 1 /* ... PPC4xx family */
30#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
wdenk0e6d7982004-03-14 00:07:33 +000031#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
32
Wolfgang Denk2ae18242010-10-06 09:05:45 +020033#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
34
Stefan Roese72675dc2008-06-06 15:55:21 +020035/*
36 * Include common defines/options for all AMCC eval boards
37 */
38#define CONFIG_HOSTNAME ocotea
39#include "amcc-common.h"
40
wdenk0e6d7982004-03-14 00:07:33 +000041/*-----------------------------------------------------------------------
42 * Base addresses -- Note these are effective addresses where the
43 * actual resources get mapped (not physical addresses)
44 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */
46#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
48#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
wdenk0e6d7982004-03-14 00:07:33 +000049
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
51#define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
wdenk0e6d7982004-03-14 00:07:33 +000052
53/*-----------------------------------------------------------------------
54 * Initial RAM & stack pointer (placed in internal SRAM)
55 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_TEMP_STACK_OCM 1
57#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
58#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +020059#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
wdenk0e6d7982004-03-14 00:07:33 +000060
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020061#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Michael Zaidman800eb092010-09-20 08:51:53 +020062#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
wdenk0e6d7982004-03-14 00:07:33 +000063
wdenk0e6d7982004-03-14 00:07:33 +000064/*-----------------------------------------------------------------------
65 * Serial Port
66 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020067#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
wdenk0e6d7982004-03-14 00:07:33 +000069
70/*-----------------------------------------------------------------------
Stefan Roese8a316c92005-08-01 16:49:12 +020071 * Environment
72 *----------------------------------------------------------------------*/
73/*
74 * Define here the location of the environment variables (FLASH or NVRAM).
75 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
76 * supported for backward compatibility.
77 */
78#if 1
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020079#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese8a316c92005-08-01 16:49:12 +020080#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +020081#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Stefan Roese8a316c92005-08-01 16:49:12 +020082#endif
83
84
85/*-----------------------------------------------------------------------
wdenk0e6d7982004-03-14 00:07:33 +000086 * NVRAM/RTC
87 *
88 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
89 * The DS1743 code assumes this condition (i.e. -- it assumes the base
90 * address for the RTC registers is:
91 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092 * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
wdenk0e6d7982004-03-14 00:07:33 +000093 *
94 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
wdenk0e6d7982004-03-14 00:07:33 +000096#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
97
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +020098#ifdef CONFIG_ENV_IS_IN_NVRAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020099#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
100#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200102#endif /* CONFIG_ENV_IS_IN_NVRAM */
Stefan Roese8a316c92005-08-01 16:49:12 +0200103
wdenk0e6d7982004-03-14 00:07:33 +0000104/*-----------------------------------------------------------------------
105 * FLASH related
106 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */
108#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
wdenk0e6d7982004-03-14 00:07:33 +0000109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#undef CONFIG_SYS_FLASH_CHECKSUM
111#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
112#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk0e6d7982004-03-14 00:07:33 +0000113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_FLASH_ADDR0 0x5555
115#define CONFIG_SYS_FLASH_ADDR1 0x2aaa
116#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char
Stefan Roese8a316c92005-08-01 16:49:12 +0200117
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200118#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200119#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200121#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese8a316c92005-08-01 16:49:12 +0200122
123/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200124#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
125#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200126#endif /* CONFIG_ENV_IS_IN_FLASH */
Stefan Roese8a316c92005-08-01 16:49:12 +0200127
wdenk0e6d7982004-03-14 00:07:33 +0000128/*-----------------------------------------------------------------------
129 * DDR SDRAM
130 *----------------------------------------------------------------------*/
Stefan Roesefa1aef12007-03-07 16:43:00 +0100131#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
wdenk42dfe7a2004-03-14 22:25:36 +0000132#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
Stefan Roesefa1aef12007-03-07 16:43:00 +0100133#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/
wdenk0e6d7982004-03-14 00:07:33 +0000134
135/*-----------------------------------------------------------------------
136 * I2C
137 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000138#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese4f92ed52006-08-07 14:33:32 +0200139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_I2C_MULTI_EEPROMS
141#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
142#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
143#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
144#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenk0e6d7982004-03-14 00:07:33 +0000145
Stefan Roese72675dc2008-06-06 15:55:21 +0200146/*
147 * Default environment variables
148 */
Stefan Roese8a316c92005-08-01 16:49:12 +0200149#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese72675dc2008-06-06 15:55:21 +0200150 CONFIG_AMCC_DEF_ENV \
151 CONFIG_AMCC_DEF_ENV_PPC \
152 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese8a316c92005-08-01 16:49:12 +0200153 "kernel_addr=fff00000\0" \
154 "ramdisk_addr=fff10000\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200155 ""
wdenk0e6d7982004-03-14 00:07:33 +0000156
wdenk0e6d7982004-03-14 00:07:33 +0000157#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
wdenk42dfe7a2004-03-14 22:25:36 +0000158#define CONFIG_PHY1_ADDR 2
159#define CONFIG_PHY2_ADDR 0x10
160#define CONFIG_PHY3_ADDR 0x18
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200161#define CONFIG_HAS_ETH0
162#define CONFIG_HAS_ETH1
163#define CONFIG_HAS_ETH2
164#define CONFIG_HAS_ETH3
wdenk42dfe7a2004-03-14 22:25:36 +0000165#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
wdenk6fb6af62004-03-23 23:20:24 +0000166#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200167#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
168#define CONFIG_PHY_RESET_DELAY 1000
wdenk0e6d7982004-03-14 00:07:33 +0000169
Jon Loeligera5cb2302007-07-04 22:33:13 -0500170/*
Stefan Roese72675dc2008-06-06 15:55:21 +0200171 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500172 */
Jon Loeligera5cb2302007-07-04 22:33:13 -0500173#define CONFIG_CMD_DATE
Jon Loeligera5cb2302007-07-04 22:33:13 -0500174#define CONFIG_CMD_PCI
Jon Loeligera5cb2302007-07-04 22:33:13 -0500175#define CONFIG_CMD_SDRAM
176#define CONFIG_CMD_SNTP
177
wdenk0e6d7982004-03-14 00:07:33 +0000178/*-----------------------------------------------------------------------
179 * PCI stuff
180 *-----------------------------------------------------------------------
181 */
182/* General PCI */
Stefan Roese8a316c92005-08-01 16:49:12 +0200183#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000184#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese8a316c92005-08-01 16:49:12 +0200185#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk42dfe7a2004-03-14 22:25:36 +0000186#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
wdenk0e6d7982004-03-14 00:07:33 +0000188
189/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
wdenk0e6d7982004-03-14 00:07:33 +0000191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
193#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
wdenk0e6d7982004-03-14 00:07:33 +0000194
wdenk0e6d7982004-03-14 00:07:33 +0000195#endif /* __CONFIG_H */