blob: b58a3f632a46350aca34618fa2e483188558f6e9 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stephan Linz09aac752012-07-29 00:25:35 +02002/*
3 * Xilinx SPI driver
4 *
Jagan Tekia7b6ef02015-06-27 00:51:27 +05305 * Supports 8 bit SPI transfers only, with or w/o FIFO
Stephan Linz09aac752012-07-29 00:25:35 +02006 *
Jagan Tekia7b6ef02015-06-27 00:51:27 +05307 * Based on bfin_spi.c, by way of altera_spi.c
Jagan Teki9505c362015-06-29 13:15:18 +05308 * Copyright (c) 2015 Jagan Teki <jteki@openedev.com>
Stephan Linz09aac752012-07-29 00:25:35 +02009 * Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
Jagan Tekia7b6ef02015-06-27 00:51:27 +053010 * Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
11 * Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
12 * Copyright (c) 2005-2008 Analog Devices Inc.
Stephan Linz09aac752012-07-29 00:25:35 +020013 */
Jagan Tekia7b6ef02015-06-27 00:51:27 +053014
Stephan Linz09aac752012-07-29 00:25:35 +020015#include <config.h>
16#include <common.h>
Jagan Teki9505c362015-06-29 13:15:18 +053017#include <dm.h>
18#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060019#include <log.h>
Stephan Linz09aac752012-07-29 00:25:35 +020020#include <malloc.h>
21#include <spi.h>
T Karthik Reddyf2dd6592022-07-16 12:28:46 +053022#include <spi-mem.h>
Jagan Teki5f24d122015-06-27 00:51:37 +053023#include <asm/io.h>
Vipul Kumar0c0de582018-06-30 08:15:18 +053024#include <wait_bit.h>
Simon Glasscd93d622020-05-10 11:40:13 -060025#include <linux/bitops.h>
Stephan Linz09aac752012-07-29 00:25:35 +020026
Jagan Tekif93542a2015-06-27 00:51:26 +053027/*
Jagan Tekia7b6ef02015-06-27 00:51:27 +053028 * [0]: http://www.xilinx.com/support/documentation
Jagan Tekif93542a2015-06-27 00:51:26 +053029 *
Jagan Tekia7b6ef02015-06-27 00:51:27 +053030 * Xilinx SPI Register Definitions
Jagan Tekif93542a2015-06-27 00:51:26 +053031 * [1]: [0]/ip_documentation/xps_spi.pdf
32 * page 8, Register Descriptions
33 * [2]: [0]/ip_documentation/axi_spi_ds742.pdf
34 * page 7, Register Overview Table
35 */
Jagan Tekif93542a2015-06-27 00:51:26 +053036
37/* SPI Control Register (spicr), [1] p9, [2] p8 */
Jagan Teki5ea392d2015-10-23 01:39:31 +053038#define SPICR_LSB_FIRST BIT(9)
39#define SPICR_MASTER_INHIBIT BIT(8)
40#define SPICR_MANUAL_SS BIT(7)
41#define SPICR_RXFIFO_RESEST BIT(6)
42#define SPICR_TXFIFO_RESEST BIT(5)
43#define SPICR_CPHA BIT(4)
44#define SPICR_CPOL BIT(3)
45#define SPICR_MASTER_MODE BIT(2)
46#define SPICR_SPE BIT(1)
47#define SPICR_LOOP BIT(0)
Jagan Tekif93542a2015-06-27 00:51:26 +053048
49/* SPI Status Register (spisr), [1] p11, [2] p10 */
Jagan Teki5ea392d2015-10-23 01:39:31 +053050#define SPISR_SLAVE_MODE_SELECT BIT(5)
51#define SPISR_MODF BIT(4)
52#define SPISR_TX_FULL BIT(3)
53#define SPISR_TX_EMPTY BIT(2)
54#define SPISR_RX_FULL BIT(1)
55#define SPISR_RX_EMPTY BIT(0)
Jagan Tekif93542a2015-06-27 00:51:26 +053056
57/* SPI Data Transmit Register (spidtr), [1] p12, [2] p12 */
Jagan Tekid2436302015-10-23 01:03:44 +053058#define SPIDTR_8BIT_MASK GENMASK(7, 0)
59#define SPIDTR_16BIT_MASK GENMASK(15, 0)
60#define SPIDTR_32BIT_MASK GENMASK(31, 0)
Jagan Tekif93542a2015-06-27 00:51:26 +053061
62/* SPI Data Receive Register (spidrr), [1] p12, [2] p12 */
Jagan Tekid2436302015-10-23 01:03:44 +053063#define SPIDRR_8BIT_MASK GENMASK(7, 0)
64#define SPIDRR_16BIT_MASK GENMASK(15, 0)
65#define SPIDRR_32BIT_MASK GENMASK(31, 0)
Jagan Tekif93542a2015-06-27 00:51:26 +053066
67/* SPI Slave Select Register (spissr), [1] p13, [2] p13 */
68#define SPISSR_MASK(cs) (1 << (cs))
69#define SPISSR_ACT(cs) ~SPISSR_MASK(cs)
70#define SPISSR_OFF ~0UL
71
Jagan Tekif93542a2015-06-27 00:51:26 +053072/* SPI Software Reset Register (ssr) */
73#define SPISSR_RESET_VALUE 0x0a
74
Jagan Tekia7b6ef02015-06-27 00:51:27 +053075#define XILSPI_MAX_XFER_BITS 8
76#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | SPICR_MASTER_MODE | \
T Karthik Reddyf2dd6592022-07-16 12:28:46 +053077 SPICR_SPE | SPICR_MASTER_INHIBIT)
Jagan Tekia7b6ef02015-06-27 00:51:27 +053078#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | SPICR_MANUAL_SS)
79
Ashok Reddy Somaf44bd3b2020-05-18 01:11:00 -060080#define XILINX_SPI_IDLE_VAL GENMASK(7, 0)
Jagan Tekia7b6ef02015-06-27 00:51:27 +053081
Vipul Kumar0c0de582018-06-30 08:15:18 +053082#define XILINX_SPISR_TIMEOUT 10000 /* in milliseconds */
83
Jagan Tekia7b6ef02015-06-27 00:51:27 +053084/* xilinx spi register set */
Jagan Teki9505c362015-06-29 13:15:18 +053085struct xilinx_spi_regs {
Jagan Tekia7b6ef02015-06-27 00:51:27 +053086 u32 __space0__[7];
87 u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
88 u32 ipisr; /* IP Interrupt Status Register (IPISR) */
89 u32 __space1__;
90 u32 ipier; /* IP Interrupt Enable Register (IPIER) */
91 u32 __space2__[5];
92 u32 srr; /* Softare Reset Register (SRR) */
93 u32 __space3__[7];
94 u32 spicr; /* SPI Control Register (SPICR) */
95 u32 spisr; /* SPI Status Register (SPISR) */
96 u32 spidtr; /* SPI Data Transmit Register (SPIDTR) */
97 u32 spidrr; /* SPI Data Receive Register (SPIDRR) */
98 u32 spissr; /* SPI Slave Select Register (SPISSR) */
99 u32 spitfor; /* SPI Transmit FIFO Occupancy Register (SPITFOR) */
100 u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
101};
102
Jagan Teki9505c362015-06-29 13:15:18 +0530103/* xilinx spi priv */
104struct xilinx_spi_priv {
105 struct xilinx_spi_regs *regs;
Jagan Tekif93542a2015-06-27 00:51:26 +0530106 unsigned int freq;
107 unsigned int mode;
Vipul Kumar0c0de582018-06-30 08:15:18 +0530108 unsigned int fifo_depth;
Vipul Kumar83ce6462018-06-30 08:15:19 +0530109 u8 startup;
Jagan Tekif93542a2015-06-27 00:51:26 +0530110};
111
Jagan Teki9505c362015-06-29 13:15:18 +0530112static int xilinx_spi_probe(struct udevice *bus)
Stephan Linz09aac752012-07-29 00:25:35 +0200113{
Jagan Teki9505c362015-06-29 13:15:18 +0530114 struct xilinx_spi_priv *priv = dev_get_priv(bus);
Jiajie Chen4fffbc12023-02-27 23:09:39 +0800115 struct xilinx_spi_regs *regs;
Stephan Linz09aac752012-07-29 00:25:35 +0200116
Johan Jonkera12a73b2023-03-13 01:32:04 +0100117 regs = priv->regs = dev_read_addr_ptr(bus);
Vipul Kumar6e9d9fc2018-06-30 08:15:20 +0530118 priv->fifo_depth = dev_read_u32_default(bus, "fifo-size", 0);
Vipul Kumar0c0de582018-06-30 08:15:18 +0530119
Jagan Teki9505c362015-06-29 13:15:18 +0530120 writel(SPISSR_RESET_VALUE, &regs->srr);
Stephan Linz09aac752012-07-29 00:25:35 +0200121
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530122 /*
123 * Reset RX & TX FIFO
124 * Enable Manual Slave Select Assertion,
125 * Set SPI controller into master mode, and enable it
126 */
127 writel(SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST |
128 SPICR_MANUAL_SS | SPICR_MASTER_MODE | SPICR_SPE,
129 &regs->spicr);
130
Stephan Linz09aac752012-07-29 00:25:35 +0200131 return 0;
132}
133
Jagan Teki9505c362015-06-29 13:15:18 +0530134static void spi_cs_activate(struct udevice *dev, uint cs)
Stephan Linz09aac752012-07-29 00:25:35 +0200135{
Jagan Teki9505c362015-06-29 13:15:18 +0530136 struct udevice *bus = dev_get_parent(dev);
137 struct xilinx_spi_priv *priv = dev_get_priv(bus);
138 struct xilinx_spi_regs *regs = priv->regs;
Stephan Linz09aac752012-07-29 00:25:35 +0200139
Jagan Teki9505c362015-06-29 13:15:18 +0530140 writel(SPISSR_ACT(cs), &regs->spissr);
Stephan Linz09aac752012-07-29 00:25:35 +0200141}
142
Jagan Teki9505c362015-06-29 13:15:18 +0530143static void spi_cs_deactivate(struct udevice *dev)
Stephan Linz09aac752012-07-29 00:25:35 +0200144{
Jagan Teki9505c362015-06-29 13:15:18 +0530145 struct udevice *bus = dev_get_parent(dev);
146 struct xilinx_spi_priv *priv = dev_get_priv(bus);
147 struct xilinx_spi_regs *regs = priv->regs;
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530148 u32 reg;
Jagan Teki9505c362015-06-29 13:15:18 +0530149
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530150 reg = readl(&regs->spicr) | SPICR_RXFIFO_RESEST | SPICR_TXFIFO_RESEST;
151 writel(reg, &regs->spicr);
Jagan Teki9505c362015-06-29 13:15:18 +0530152 writel(SPISSR_OFF, &regs->spissr);
153}
154
155static int xilinx_spi_claim_bus(struct udevice *dev)
156{
157 struct udevice *bus = dev_get_parent(dev);
158 struct xilinx_spi_priv *priv = dev_get_priv(bus);
159 struct xilinx_spi_regs *regs = priv->regs;
160
161 writel(SPISSR_OFF, &regs->spissr);
162 writel(XILSPI_SPICR_DFLT_ON, &regs->spicr);
163
164 return 0;
165}
166
167static int xilinx_spi_release_bus(struct udevice *dev)
168{
169 struct udevice *bus = dev_get_parent(dev);
170 struct xilinx_spi_priv *priv = dev_get_priv(bus);
171 struct xilinx_spi_regs *regs = priv->regs;
172
173 writel(SPISSR_OFF, &regs->spissr);
174 writel(XILSPI_SPICR_DFLT_OFF, &regs->spicr);
175
176 return 0;
177}
178
Vipul Kumar0c0de582018-06-30 08:15:18 +0530179static u32 xilinx_spi_fill_txfifo(struct udevice *bus, const u8 *txp,
180 u32 txbytes)
181{
182 struct xilinx_spi_priv *priv = dev_get_priv(bus);
183 struct xilinx_spi_regs *regs = priv->regs;
184 unsigned char d;
185 u32 i = 0;
186
187 while (txbytes && !(readl(&regs->spisr) & SPISR_TX_FULL) &&
188 i < priv->fifo_depth) {
Ashok Reddy Somaf44bd3b2020-05-18 01:11:00 -0600189 d = txp ? *txp++ : XILINX_SPI_IDLE_VAL;
Vipul Kumar0c0de582018-06-30 08:15:18 +0530190 debug("spi_xfer: tx:%x ", d);
191 /* write out and wait for processing (receive data) */
192 writel(d & SPIDTR_8BIT_MASK, &regs->spidtr);
193 txbytes--;
194 i++;
195 }
196
197 return i;
198}
199
200static u32 xilinx_spi_read_rxfifo(struct udevice *bus, u8 *rxp, u32 rxbytes)
201{
202 struct xilinx_spi_priv *priv = dev_get_priv(bus);
203 struct xilinx_spi_regs *regs = priv->regs;
204 unsigned char d;
205 unsigned int i = 0;
206
207 while (rxbytes && !(readl(&regs->spisr) & SPISR_RX_EMPTY)) {
208 d = readl(&regs->spidrr) & SPIDRR_8BIT_MASK;
209 if (rxp)
210 *rxp++ = d;
211 debug("spi_xfer: rx:%x\n", d);
212 rxbytes--;
213 i++;
214 }
215 debug("Rx_done\n");
216
217 return i;
218}
219
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530220static int start_transfer(struct spi_slave *spi, const void *dout, void *din, u32 len)
Vipul Kumar83ce6462018-06-30 08:15:19 +0530221{
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530222 struct udevice *bus = spi->dev->parent;
Vipul Kumar83ce6462018-06-30 08:15:19 +0530223 struct xilinx_spi_priv *priv = dev_get_priv(bus);
224 struct xilinx_spi_regs *regs = priv->regs;
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530225 u32 count, txbytes, rxbytes;
226 int reg, ret;
227 const unsigned char *txp = (const unsigned char *)dout;
228 unsigned char *rxp = (unsigned char *)din;
Vipul Kumar83ce6462018-06-30 08:15:19 +0530229
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530230 txbytes = len;
231 rxbytes = len;
232 while (txbytes || rxbytes) {
233 /* Disable master transaction */
234 reg = readl(&regs->spicr) | SPICR_MASTER_INHIBIT;
Vipul Kumar83ce6462018-06-30 08:15:19 +0530235 writel(reg, &regs->spicr);
Vipul Kumar0c0de582018-06-30 08:15:18 +0530236 count = xilinx_spi_fill_txfifo(bus, txp, txbytes);
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530237 /* Enable master transaction */
Vipul Kumar0c0de582018-06-30 08:15:18 +0530238 reg = readl(&regs->spicr) & ~SPICR_MASTER_INHIBIT;
239 writel(reg, &regs->spicr);
240 txbytes -= count;
241 if (txp)
242 txp += count;
Stephan Linz09aac752012-07-29 00:25:35 +0200243
Vipul Kumar0c0de582018-06-30 08:15:18 +0530244 ret = wait_for_bit_le32(&regs->spisr, SPISR_TX_EMPTY, true,
245 XILINX_SPISR_TIMEOUT, false);
246 if (ret < 0) {
Jagan Tekia7b6ef02015-06-27 00:51:27 +0530247 printf("XILSPI error: Xfer timeout\n");
Vipul Kumar0c0de582018-06-30 08:15:18 +0530248 return ret;
Stephan Linz09aac752012-07-29 00:25:35 +0200249 }
250
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530251 reg = readl(&regs->spicr) | SPICR_MASTER_INHIBIT;
252 writel(reg, &regs->spicr);
Vipul Kumar0c0de582018-06-30 08:15:18 +0530253 count = xilinx_spi_read_rxfifo(bus, rxp, rxbytes);
254 rxbytes -= count;
Stephan Linz09aac752012-07-29 00:25:35 +0200255 if (rxp)
Vipul Kumar0c0de582018-06-30 08:15:18 +0530256 rxp += count;
Stephan Linz09aac752012-07-29 00:25:35 +0200257 }
258
Stephan Linz09aac752012-07-29 00:25:35 +0200259 return 0;
260}
Jagan Teki9505c362015-06-29 13:15:18 +0530261
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530262static void xilinx_spi_startup_block(struct spi_slave *spi)
263{
264 struct dm_spi_slave_plat *slave_plat =
265 dev_get_parent_plat(spi->dev);
266 unsigned char txp;
267 unsigned char rxp[8];
268
269 /*
270 * Perform a dummy read as a work around for
271 * the startup block issue.
272 */
273 spi_cs_activate(spi->dev, slave_plat->cs);
274 txp = 0x9f;
275 start_transfer(spi, (void *)&txp, NULL, 1);
276
277 start_transfer(spi, NULL, (void *)rxp, 6);
278
279 spi_cs_deactivate(spi->dev);
280}
281
282static int xilinx_spi_mem_exec_op(struct spi_slave *spi,
283 const struct spi_mem_op *op)
284{
285 struct dm_spi_slave_plat *slave_plat =
286 dev_get_parent_plat(spi->dev);
287 static u32 startup;
288 u32 dummy_len, ret;
289
290 /*
291 * This is the work around for the startup block issue in
292 * the spi controller. SPI clock is passing through STARTUP
293 * block to FLASH. STARTUP block don't provide clock as soon
294 * as QSPI provides command. So first command fails.
295 */
296 if (!startup) {
297 xilinx_spi_startup_block(spi);
298 startup++;
299 }
300
301 spi_cs_activate(spi->dev, slave_plat->cs);
302
303 if (op->cmd.opcode) {
304 ret = start_transfer(spi, (void *)&op->cmd.opcode, NULL, 1);
305 if (ret)
306 goto done;
307 }
308 if (op->addr.nbytes) {
309 int i;
310 u8 addr_buf[4];
311
312 for (i = 0; i < op->addr.nbytes; i++)
313 addr_buf[i] = op->addr.val >>
314 (8 * (op->addr.nbytes - i - 1));
315
316 ret = start_transfer(spi, (void *)addr_buf, NULL,
317 op->addr.nbytes);
318 if (ret)
319 goto done;
320 }
321 if (op->dummy.nbytes) {
T Karthik Reddy557832b2022-07-16 12:28:47 +0530322 dummy_len = (op->dummy.nbytes * op->data.buswidth) /
323 op->dummy.buswidth;
324
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530325 ret = start_transfer(spi, NULL, NULL, dummy_len);
326 if (ret)
327 goto done;
328 }
329 if (op->data.nbytes) {
330 if (op->data.dir == SPI_MEM_DATA_IN) {
331 ret = start_transfer(spi, NULL,
332 op->data.buf.in, op->data.nbytes);
333 } else {
334 ret = start_transfer(spi, op->data.buf.out,
335 NULL, op->data.nbytes);
336 }
337 if (ret)
338 goto done;
339 }
340done:
341 spi_cs_deactivate(spi->dev);
342
343 return ret;
344}
345
T Karthik Reddy557832b2022-07-16 12:28:47 +0530346static int xilinx_qspi_check_buswidth(struct spi_slave *slave, u8 width)
347{
348 u32 mode = slave->mode;
349
350 switch (width) {
351 case 1:
352 return 0;
353 case 2:
354 if (mode & SPI_RX_DUAL)
355 return 0;
356 break;
357 case 4:
358 if (mode & SPI_RX_QUAD)
359 return 0;
360 break;
361 }
362
363 return -EOPNOTSUPP;
364}
365
Algapally Santosh Sagar583cebb2023-06-14 03:03:54 -0600366static bool xilinx_qspi_mem_exec_op(struct spi_slave *slave,
367 const struct spi_mem_op *op)
T Karthik Reddy557832b2022-07-16 12:28:47 +0530368{
369 if (xilinx_qspi_check_buswidth(slave, op->cmd.buswidth))
370 return false;
371
372 if (op->addr.nbytes &&
373 xilinx_qspi_check_buswidth(slave, op->addr.buswidth))
374 return false;
375
376 if (op->dummy.nbytes &&
377 xilinx_qspi_check_buswidth(slave, op->dummy.buswidth))
378 return false;
379
380 if (op->data.dir != SPI_MEM_NO_DATA &&
381 xilinx_qspi_check_buswidth(slave, op->data.buswidth))
382 return false;
383
384 return true;
385}
386
Jagan Teki9505c362015-06-29 13:15:18 +0530387static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
388{
389 struct xilinx_spi_priv *priv = dev_get_priv(bus);
390
391 priv->freq = speed;
392
T Karthik Reddyd999a7b2021-03-17 01:01:50 -0600393 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
Jagan Teki9505c362015-06-29 13:15:18 +0530394
395 return 0;
396}
397
398static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
399{
400 struct xilinx_spi_priv *priv = dev_get_priv(bus);
401 struct xilinx_spi_regs *regs = priv->regs;
T Karthik Reddyd999a7b2021-03-17 01:01:50 -0600402 u32 spicr;
Jagan Teki9505c362015-06-29 13:15:18 +0530403
404 spicr = readl(&regs->spicr);
Jagan Tekid5f60732015-09-08 01:26:29 +0530405 if (mode & SPI_LSB_FIRST)
Jagan Teki9505c362015-06-29 13:15:18 +0530406 spicr |= SPICR_LSB_FIRST;
Jagan Tekid5f60732015-09-08 01:26:29 +0530407 if (mode & SPI_CPHA)
Jagan Teki9505c362015-06-29 13:15:18 +0530408 spicr |= SPICR_CPHA;
Jagan Tekid5f60732015-09-08 01:26:29 +0530409 if (mode & SPI_CPOL)
Jagan Teki9505c362015-06-29 13:15:18 +0530410 spicr |= SPICR_CPOL;
Jagan Tekid5f60732015-09-08 01:26:29 +0530411 if (mode & SPI_LOOP)
Jagan Teki9505c362015-06-29 13:15:18 +0530412 spicr |= SPICR_LOOP;
413
414 writel(spicr, &regs->spicr);
415 priv->mode = mode;
416
T Karthik Reddyd999a7b2021-03-17 01:01:50 -0600417 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
Jagan Teki9505c362015-06-29 13:15:18 +0530418
419 return 0;
420}
421
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530422static const struct spi_controller_mem_ops xilinx_spi_mem_ops = {
423 .exec_op = xilinx_spi_mem_exec_op,
T Karthik Reddy557832b2022-07-16 12:28:47 +0530424 .supports_op = xilinx_qspi_mem_exec_op,
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530425};
426
Jagan Teki9505c362015-06-29 13:15:18 +0530427static const struct dm_spi_ops xilinx_spi_ops = {
428 .claim_bus = xilinx_spi_claim_bus,
429 .release_bus = xilinx_spi_release_bus,
Jagan Teki9505c362015-06-29 13:15:18 +0530430 .set_speed = xilinx_spi_set_speed,
431 .set_mode = xilinx_spi_set_mode,
T Karthik Reddyf2dd6592022-07-16 12:28:46 +0530432 .mem_ops = &xilinx_spi_mem_ops,
Jagan Teki9505c362015-06-29 13:15:18 +0530433};
434
435static const struct udevice_id xilinx_spi_ids[] = {
Michal Simek76de51a2015-12-11 12:41:14 +0100436 { .compatible = "xlnx,xps-spi-2.00.a" },
437 { .compatible = "xlnx,xps-spi-2.00.b" },
Jagan Teki9505c362015-06-29 13:15:18 +0530438 { }
439};
440
441U_BOOT_DRIVER(xilinx_spi) = {
442 .name = "xilinx_spi",
443 .id = UCLASS_SPI,
444 .of_match = xilinx_spi_ids,
445 .ops = &xilinx_spi_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700446 .priv_auto = sizeof(struct xilinx_spi_priv),
Jagan Teki9505c362015-06-29 13:15:18 +0530447 .probe = xilinx_spi_probe,
448};