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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 1079432e04ccf71aa3684181186182cd63512f19 / . / board / afeb9260 / afeb9260.c
blob: d1e01653144f40ac343f185b84a0a62202993baf [file] [log] [blame]
Sergey Lapin10794322008-10-31 12:28:43 +0100[diff] [blame^]1/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 * (C) Copyright 2008 Sergey Lapin <slapin@ossfans.org>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/arch/at91sam9260.h>
28#include <asm/arch/at91sam9260_matrix.h>
29#include <asm/arch/at91sam9_smc.h>
30#include <asm/arch/at91_pmc.h>
31#include <asm/arch/at91_rstc.h>
32#include <asm/arch/gpio.h>
33#include <asm/arch/io.h>
34#include <asm/arch/hardware.h>
35#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
36#include <netdev.h>
37#include <net.h>
38#endif
39
40DECLARE_GLOBAL_DATA_PTR;
41
42/* ------------------------------------------------------------------------- */
43/*
44 * Miscelaneous platform dependent initialisations
45 */
46
47static void afeb9260_serial_hw_init(void)
48{
49#ifdef CONFIG_USART0
50 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
51 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
52 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US0);
53#endif
54
55#ifdef CONFIG_USART1
56 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
57 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
58 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US1);
59#endif
60
61#ifdef CONFIG_USART2
62 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
63 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
64 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_US2);
65#endif
66
67#ifdef CONFIG_USART3 /* DBGU */
68 at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
69 at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
70 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
71#endif
72}
73
74static void afeb9260_nand_hw_init(void)
75{
76 unsigned long csa;
77
78 /* Enable CS3 */
79 csa = at91_sys_read(AT91_MATRIX_EBICSA);
80 at91_sys_write(AT91_MATRIX_EBICSA,
81 csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
82
83 /* Configure SMC CS3 for NAND/SmartMedia */
84 at91_sys_write(AT91_SMC_SETUP(3),
85 AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
86 AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
87 at91_sys_write(AT91_SMC_PULSE(3),
88 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
89 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
90 at91_sys_write(AT91_SMC_CYCLE(3),
91 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
92 at91_sys_write(AT91_SMC_MODE(3),
93 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
94 AT91_SMC_EXNWMODE_DISABLE |
95 AT91_SMC_DBW_8 |
96 AT91_SMC_TDF_(2));
97
98 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
99
100 /* Configure RDY/BSY */
101 at91_set_gpio_input(AT91_PIN_PC13, 1);
102
103 /* Enable NandFlash */
104 at91_set_gpio_output(AT91_PIN_PC14, 1);
105}
106
107static void afeb9260_spi_hw_init(void)
108{
109 at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */
110 at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */
111
112 at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
113 at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
114 at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
115
116 /* Enable clock */
117 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0);
118}
119
120#ifdef CONFIG_MACB
121static void afeb9260_macb_hw_init(void)
122{
123 /* Enable clock */
124 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
125
126 /*
127 * Disable pull-up on:
128 * RXDV (PA17) => PHY normal mode (not Test mode)
129 * ERX0 (PA14) => PHY ADDR0
130 * ERX1 (PA15) => PHY ADDR1
131 * ERX2 (PA25) => PHY ADDR2
132 * ERX3 (PA26) => PHY ADDR3
133 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
134 *
135 * PHY has internal pull-down
136 */
137 writel(pin_to_mask(AT91_PIN_PA14) |
138 pin_to_mask(AT91_PIN_PA15) |
139 pin_to_mask(AT91_PIN_PA17) |
140 pin_to_mask(AT91_PIN_PA25) |
141 pin_to_mask(AT91_PIN_PA26) |
142 pin_to_mask(AT91_PIN_PA28),
143 pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
144
145 /* Need to reset PHY -> 500ms reset */
146 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
147 AT91_RSTC_ERSTL | (0x0D << 8) |
148 AT91_RSTC_URSTEN);
149
150 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
151
152 /* Wait for end hardware reset */
153 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
154
155 /* Restore NRST value */
156 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
157 AT91_RSTC_ERSTL | (0x0 << 8) |
158 AT91_RSTC_URSTEN);
159
160 /* Re-enable pull-up */
161 writel(pin_to_mask(AT91_PIN_PA14) |
162 pin_to_mask(AT91_PIN_PA15) |
163 pin_to_mask(AT91_PIN_PA17) |
164 pin_to_mask(AT91_PIN_PA25) |
165 pin_to_mask(AT91_PIN_PA26) |
166 pin_to_mask(AT91_PIN_PA28),
167 pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
168
169 at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
170 at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
171 at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
172 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
173 at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
174 at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
175 at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
176 at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
177 at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
178 at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
179
180#ifndef CONFIG_RMII
181 at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
182 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
183 at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
184 at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
185 at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
186 at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */
187 at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */
188 at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
189#endif
190
191}
192#endif
193
194int board_init(void)
195{
196 /* Enable Ctrlc */
197 console_init_f();
198
199 /* arch number of AT91SAM9260EK-Board */
200 gd->bd->bi_arch_number = MACH_TYPE_AFEB9260;
201 /* adress of boot parameters */
202 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
203
204 afeb9260_serial_hw_init();
205#ifdef CONFIG_CMD_NAND
206 afeb9260_nand_hw_init();
207#endif
208 afeb9260_spi_hw_init();
209#ifdef CONFIG_MACB
210 afeb9260_macb_hw_init();
211#endif
212
213 return 0;
214}
215
216int dram_init(void)
217{
218 gd->bd->bi_dram[0].start = PHYS_SDRAM;
219 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
220 return 0;
221}
222
223#ifdef CONFIG_RESET_PHY_R
224void reset_phy(void)
225{
226#ifdef CONFIG_MACB
227 /*
228 * Initialize ethernet HW addr prior to starting Linux,
229 * needed for nfsroot
230 */
231 eth_init(gd->bd);
232#endif
233}
234#endif
235
236int board_eth_init(bd_t *bis)
237{
238 int rc = 0;
239#ifdef CONFIG_MACB
240 rc = macb_eth_initialize(0, (void *)AT91_BASE_EMAC, 0x01);
241#endif
242 return rc;
243}