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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 107b3fb484ed960f0c269deff9eaf7cc6f83b0de / . / arch / arm / mach-uniphier / clk / clk-ph1-ld4.c
blob: 4de9bfb102c605b2ad26c521b53998ec2be275b1 [file] [log] [blame]
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]1/*
Masahiro Yamadaf6e7f072015-05-29 17:30:00 +0900[diff] [blame]2 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
Masahiro Yamadaf6e7f072015-05-29 17:30:00 +0900[diff] [blame]7#include <linux/io.h>
Masahiro Yamada107b3fb2016-01-09 01:51:13 +0900[diff] [blame^]8
9#include "../init.h"
10#include "../sc-regs.h"
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]11
Masahiro Yamada323d1f92015-09-22 00:27:39 +0900[diff] [blame]12void ph1_ld4_clk_init(void)
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]13{
14 u32 tmp;
15
16 /* deassert reset */
17 tmp = readl(SC_RSTCTRL);
Masahiro Yamada198a97a2015-02-27 02:26:51 +0900[diff] [blame]18#ifdef CONFIG_UNIPHIER_ETH
19 tmp |= SC_RSTCTRL_NRST_ETHER;
20#endif
Masahiro Yamada42ca6982015-02-27 02:26:53 +0900[diff] [blame]21#ifdef CONFIG_USB_EHCI_UNIPHIER
22 tmp |= SC_RSTCTRL_NRST_STDMAC;
23#endif
Masahiro Yamada198a97a2015-02-27 02:26:51 +0900[diff] [blame]24#ifdef CONFIG_NAND_DENALI
25 tmp |= SC_RSTCTRL_NRST_NAND;
26#endif
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]27 writel(tmp, SC_RSTCTRL);
28 readl(SC_RSTCTRL); /* dummy read */
29
30 /* privide clocks */
31 tmp = readl(SC_CLKCTRL);
Masahiro Yamada198a97a2015-02-27 02:26:51 +0900[diff] [blame]32#ifdef CONFIG_UNIPHIER_ETH
33 tmp |= SC_CLKCTRL_CEN_ETHER;
34#endif
35#ifdef CONFIG_USB_EHCI_UNIPHIER
Masahiro Yamada42ca6982015-02-27 02:26:53 +0900[diff] [blame]36 tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
Masahiro Yamada198a97a2015-02-27 02:26:51 +0900[diff] [blame]37#endif
38#ifdef CONFIG_NAND_DENALI
39 tmp |= SC_CLKCTRL_CEN_NAND;
40#endif
Masahiro Yamada5894ca02014-10-03 19:21:06 +0900[diff] [blame]41 writel(tmp, SC_CLKCTRL);
42 readl(SC_CLKCTRL); /* dummy read */
43}