blob: 4bf05d2033616fbd3401250b057f6582befbb2f9 [file] [log] [blame]
Scott Wood96b8a052007-04-16 14:54:15 -05001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
Scott Wood96b8a052007-04-16 14:54:15 -050021 */
22/*
23 * mpc8313epb board configuration file
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 */
32#define CONFIG_E300 1
Peter Tyser0f898602009-05-22 17:23:24 -050033#define CONFIG_MPC83xx 1
Peter Tyser2c7920a2009-05-22 17:23:25 -050034#define CONFIG_MPC831x 1
Scott Wood96b8a052007-04-16 14:54:15 -050035#define CONFIG_MPC8313 1
36#define CONFIG_MPC8313ERDB 1
37
38#define CONFIG_PCI
Scott Wood96b8a052007-04-16 14:54:15 -050039
Timur Tabi89c77842008-02-08 13:15:55 -060040#define CONFIG_MISC_INIT_R
41
42/*
43 * On-board devices
York Sun4ce1e232008-05-15 15:26:27 -050044 *
45 * TSEC1 is VSC switch
46 * TSEC2 is SoC TSEC
Timur Tabi89c77842008-02-08 13:15:55 -060047 */
48#define CONFIG_VSC7385_ENET
York Sun4ce1e232008-05-15 15:26:27 -050049#define CONFIG_TSEC2
Timur Tabi89c77842008-02-08 13:15:55 -060050
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#ifdef CONFIG_SYS_66MHZ
Kim Phillips5c5d3242007-04-25 12:34:38 -050052#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#elif defined(CONFIG_SYS_33MHZ)
Kim Phillips5c5d3242007-04-25 12:34:38 -050054#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
Scott Wood96b8a052007-04-16 14:54:15 -050055#else
56#error Unknown oscillator frequency.
57#endif
58
59#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
60
61#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
62
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_IMMR 0xE0000000
Scott Wood96b8a052007-04-16 14:54:15 -050064
Scott Woode4c09502008-06-30 14:13:28 -050065#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
Scott Woode4c09502008-06-30 14:13:28 -050067#endif
68
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_MEMTEST_START 0x00001000
70#define CONFIG_SYS_MEMTEST_END 0x07f00000
Scott Wood96b8a052007-04-16 14:54:15 -050071
72/* Early revs of this board will lock up hard when attempting
73 * to access the PMC registers, unless a JTAG debugger is
74 * connected, or some resistor modifications are made.
75 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1
Scott Wood96b8a052007-04-16 14:54:15 -050077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
79#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Scott Wood96b8a052007-04-16 14:54:15 -050080
81/*
Timur Tabi89c77842008-02-08 13:15:55 -060082 * Device configurations
83 */
84
85/* Vitesse 7385 */
86
87#ifdef CONFIG_VSC7385_ENET
88
York Sun4ce1e232008-05-15 15:26:27 -050089#define CONFIG_TSEC1
Timur Tabi89c77842008-02-08 13:15:55 -060090
91/* The flash address and size of the VSC7385 firmware image */
92#define CONFIG_VSC7385_IMAGE 0xFE7FE000
93#define CONFIG_VSC7385_IMAGE_SIZE 8192
94
95#endif
96
97/*
Scott Wood96b8a052007-04-16 14:54:15 -050098 * DDR Setup
99 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
101#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
102#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Scott Wood96b8a052007-04-16 14:54:15 -0500103
104/*
105 * Manually set up DDR parameters, as this board does not
106 * seem to have the SPD connected to I2C.
107 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_DDR_SIZE 128 /* MB */
109#define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530110 | 0x00010000 /* TODO */ \
Scott Wood96b8a052007-04-16 14:54:15 -0500111 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530112 /* 0x80010102 */
Scott Wood96b8a052007-04-16 14:54:15 -0500113
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_DDR_TIMING_3 0x00000000
115#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
Scott Wood96b8a052007-04-16 14:54:15 -0500116 | ( 0 << TIMING_CFG0_WRT_SHIFT ) \
117 | ( 0 << TIMING_CFG0_RRT_SHIFT ) \
118 | ( 0 << TIMING_CFG0_WWT_SHIFT ) \
119 | ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
120 | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
121 | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
122 | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
123 /* 0x00220802 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530125 | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
Scott Wood96b8a052007-04-16 14:54:15 -0500126 | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
127 | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530128 | (10 << TIMING_CFG1_REFREC_SHIFT ) \
Scott Wood96b8a052007-04-16 14:54:15 -0500129 | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
130 | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
131 | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530132 /* 0x3835a322 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530134 | ( 5 << TIMING_CFG2_CPO_SHIFT ) \
Scott Wood96b8a052007-04-16 14:54:15 -0500135 | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
136 | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
137 | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
138 | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530139 | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) )
140 /* 0x129048c6 */ /* P9-45,may need tuning */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530142 | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
143 /* 0x05100500 */
Scott Wood96b8a052007-04-16 14:54:15 -0500144#if defined(CONFIG_DDR_2T_TIMING)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500146 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Scott Wood96b8a052007-04-16 14:54:15 -0500147 | SDRAM_CFG_2T_EN \
148 | SDRAM_CFG_DBW_32 )
149#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500151 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Scott Wood96b8a052007-04-16 14:54:15 -0500152 | SDRAM_CFG_32_BE )
153 /* 0x43080000 */
154#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_SDRAM_CFG2 0x00401000
Scott Wood96b8a052007-04-16 14:54:15 -0500156/* set burst length to 8 for 32-bit data path */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
Poonam Aggrwale1d8ed22008-01-14 09:41:14 +0530158 | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
159 /* 0x44480632 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_DDR_MODE_2 0x8000C000
Scott Wood96b8a052007-04-16 14:54:15 -0500161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Scott Wood96b8a052007-04-16 14:54:15 -0500163 /*0x02000000*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_DDRCDR_VALUE ( DDRCDR_EN \
Scott Wood96b8a052007-04-16 14:54:15 -0500165 | DDRCDR_PZ_NOMZ \
166 | DDRCDR_NZ_NOMZ \
167 | DDRCDR_M_ODR )
168
169/*
170 * FLASH on the Local Bus
171 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200173#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
175#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */
176#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
177#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
178#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
Scott Wood96b8a052007-04-16 14:54:15 -0500179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \
Wolfgang Denka7676ea2007-05-16 01:16:53 +0200181 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
182 BR_V) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_NOR_OR_PRELIM ( 0xFF800000 /* 8 MByte */ \
Scott Wood96b8a052007-04-16 14:54:15 -0500184 | OR_GPCM_XACS \
185 | OR_GPCM_SCY_9 \
186 | OR_GPCM_EHTR \
187 | OR_GPCM_EAD )
188 /* 0xFF006FF7 TODO SLOW 16 MB flash size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */
190#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */
Scott Wood96b8a052007-04-16 14:54:15 -0500191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
193#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */
Scott Wood96b8a052007-04-16 14:54:15 -0500194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
196#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Scott Wood96b8a052007-04-16 14:54:15 -0500197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
Scott Wood96b8a052007-04-16 14:54:15 -0500199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && !defined(CONFIG_NAND_SPL)
201#define CONFIG_SYS_RAMBOOT
Scott Wood96b8a052007-04-16 14:54:15 -0500202#endif
203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_INIT_RAM_LOCK 1
205#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
206#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/
Scott Wood96b8a052007-04-16 14:54:15 -0500207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
209#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
210#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Scott Wood96b8a052007-04-16 14:54:15 -0500211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kim Phillips4a9932a2009-07-07 18:04:21 -0500213#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Scott Wood96b8a052007-04-16 14:54:15 -0500215
216/*
217 * Local Bus LCRR and LBCR regs
218 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4
220#define CONFIG_SYS_LBC_LBCR ( 0x00040000 /* TODO */ \
Scott Wood96b8a052007-04-16 14:54:15 -0500221 | (0xFF << LBCR_BMT_SHIFT) \
222 | 0xF ) /* 0x0004ff0f */
223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
Scott Wood96b8a052007-04-16 14:54:15 -0500225
Marcel Ziswiler7817cb22007-12-30 03:30:46 +0100226/* drivers/mtd/nand/nand.c */
Scott Woode4c09502008-06-30 14:13:28 -0500227#ifdef CONFIG_NAND_SPL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_NAND_BASE 0xFFF00000
Scott Woode4c09502008-06-30 14:13:28 -0500229#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_NAND_BASE 0xE2800000
Scott Woode4c09502008-06-30 14:13:28 -0500231#endif
232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_MAX_NAND_DEVICE 1
Scott Wood96b8a052007-04-16 14:54:15 -0500234#define CONFIG_MTD_NAND_VERIFY_WRITE
Scott Woodacdab5c2008-06-26 14:06:52 -0500235#define CONFIG_CMD_NAND 1
236#define CONFIG_NAND_FSL_ELBC 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
Kim Phillipsd9ac3d52009-06-15 11:51:47 -0500238#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
Scott Wood96b8a052007-04-16 14:54:15 -0500239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
241#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
242#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
243#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
244#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
Scott Woode4c09502008-06-30 14:13:28 -0500245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \
Wolfgang Denka7676ea2007-05-16 01:16:53 +0200247 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
248 | BR_PS_8 /* Port Size = 8 bit */ \
249 | BR_MS_FCM /* MSEL = FCM */ \
250 | BR_V ) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \
Scott Wood96b8a052007-04-16 14:54:15 -0500252 | OR_FCM_CSCT \
253 | OR_FCM_CST \
254 | OR_FCM_CHT \
255 | OR_FCM_SCY_1 \
256 | OR_FCM_TRLX \
257 | OR_FCM_EHTR )
258 /* 0xFFFF8396 */
Scott Woode4c09502008-06-30 14:13:28 -0500259
260#ifdef CONFIG_NAND_U_BOOT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
262#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
263#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
264#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
Scott Woode4c09502008-06-30 14:13:28 -0500265#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
267#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
268#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
269#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
Scott Woode4c09502008-06-30 14:13:28 -0500270#endif
271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
273#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
Scott Wood96b8a052007-04-16 14:54:15 -0500274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
276#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
Scott Woode4c09502008-06-30 14:13:28 -0500277
Scott Wood96b8a052007-04-16 14:54:15 -0500278/* local bus read write buffer mapping */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
280#define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
281#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000
282#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
Scott Wood96b8a052007-04-16 14:54:15 -0500283
Timur Tabi89c77842008-02-08 13:15:55 -0600284/* Vitesse 7385 */
285
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_VSC7385_BASE 0xF0000000
Timur Tabi89c77842008-02-08 13:15:55 -0600287
288#ifdef CONFIG_VSC7385_ENET
289
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
291#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
292#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */
293#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */
Timur Tabi89c77842008-02-08 13:15:55 -0600294
295#endif
296
Scott Wood96b8a052007-04-16 14:54:15 -0500297/* pass open firmware flat tree */
Kim Phillips35cc4e42007-08-15 22:30:39 -0500298#define CONFIG_OF_LIBFDT 1
Scott Wood96b8a052007-04-16 14:54:15 -0500299#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600300#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Scott Wood96b8a052007-04-16 14:54:15 -0500301
302/*
303 * Serial Port
304 */
305#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_NS16550
307#define CONFIG_SYS_NS16550_SERIAL
308#define CONFIG_SYS_NS16550_REG_SIZE 1
Scott Wood96b8a052007-04-16 14:54:15 -0500309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_BAUDRATE_TABLE \
Scott Wood96b8a052007-04-16 14:54:15 -0500311 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
314#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Scott Wood96b8a052007-04-16 14:54:15 -0500315
316/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_HUSH_PARSER
318#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Scott Wood96b8a052007-04-16 14:54:15 -0500319
320/* I2C */
321#define CONFIG_HARD_I2C /* I2C with hardware support*/
322#define CONFIG_FSL_I2C
323#define CONFIG_I2C_MULTI_BUS
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
325#define CONFIG_SYS_I2C_SLAVE 0x7F
326#define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
327#define CONFIG_SYS_I2C_OFFSET 0x3000
328#define CONFIG_SYS_I2C2_OFFSET 0x3100
Scott Wood96b8a052007-04-16 14:54:15 -0500329
Scott Wood96b8a052007-04-16 14:54:15 -0500330/*
331 * General PCI
332 * Addresses are mapped 1-1.
333 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
335#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
336#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
337#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
338#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
339#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
340#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
341#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
342#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
Scott Wood96b8a052007-04-16 14:54:15 -0500343
344#define CONFIG_PCI_PNP /* do pci plug-and-play */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
Scott Wood96b8a052007-04-16 14:54:15 -0500346
347/*
Timur Tabi89c77842008-02-08 13:15:55 -0600348 * TSEC
Scott Wood96b8a052007-04-16 14:54:15 -0500349 */
350#define CONFIG_TSEC_ENET /* TSEC ethernet support */
351
Timur Tabi89c77842008-02-08 13:15:55 -0600352#define CONFIG_NET_MULTI
353#define CONFIG_GMII /* MII PHY management */
354
355#ifdef CONFIG_TSEC1
356#define CONFIG_HAS_ETH0
357#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Timur Tabi89c77842008-02-08 13:15:55 -0600359#define TSEC1_PHY_ADDR 0x1c
360#define TSEC1_FLAGS TSEC_GIGABIT
361#define TSEC1_PHYIDX 0
Scott Wood96b8a052007-04-16 14:54:15 -0500362#endif
363
Timur Tabi89c77842008-02-08 13:15:55 -0600364#ifdef CONFIG_TSEC2
365#define CONFIG_HAS_ETH1
Kim Phillips255a35772007-05-16 16:52:19 -0500366#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600368#define TSEC2_PHY_ADDR 4
369#define TSEC2_FLAGS TSEC_GIGABIT
370#define TSEC2_PHYIDX 0
371#endif
372
Scott Wood96b8a052007-04-16 14:54:15 -0500373
374/* Options are: TSEC[0-1] */
375#define CONFIG_ETHPRIME "TSEC1"
376
377/*
378 * Configure on-board RTC
379 */
380#define CONFIG_RTC_DS1337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Scott Wood96b8a052007-04-16 14:54:15 -0500382
383/*
384 * Environment
385 */
Scott Woode4c09502008-06-30 14:13:28 -0500386#if defined(CONFIG_NAND_U_BOOT)
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200387 #define CONFIG_ENV_IS_IN_NAND 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200388 #define CONFIG_ENV_OFFSET (512 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200390 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
391 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
392 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
393 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#elif !defined(CONFIG_SYS_RAMBOOT)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200395 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200397 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
398 #define CONFIG_ENV_SIZE 0x2000
Scott Wood96b8a052007-04-16 14:54:15 -0500399
400/* Address and size of Redundant Environment Sector */
401#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200402 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200403 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200404 #define CONFIG_ENV_SIZE 0x2000
Scott Wood96b8a052007-04-16 14:54:15 -0500405#endif
406
407#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200408#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Scott Wood96b8a052007-04-16 14:54:15 -0500409
Jon Loeliger8ea54992007-07-04 22:30:06 -0500410/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500411 * BOOTP options
412 */
413#define CONFIG_BOOTP_BOOTFILESIZE
414#define CONFIG_BOOTP_BOOTPATH
415#define CONFIG_BOOTP_GATEWAY
416#define CONFIG_BOOTP_HOSTNAME
417
418
419/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500420 * Command line configuration.
421 */
422#include <config_cmd_default.h>
423
424#define CONFIG_CMD_PING
425#define CONFIG_CMD_DHCP
426#define CONFIG_CMD_I2C
427#define CONFIG_CMD_MII
428#define CONFIG_CMD_DATE
429#define CONFIG_CMD_PCI
430
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500432 #undef CONFIG_CMD_SAVEENV
Jon Loeliger8ea54992007-07-04 22:30:06 -0500433 #undef CONFIG_CMD_LOADS
434#endif
Scott Wood96b8a052007-04-16 14:54:15 -0500435
436#define CONFIG_CMDLINE_EDITING 1
437
Scott Wood96b8a052007-04-16 14:54:15 -0500438
439/*
440 * Miscellaneous configurable options
441 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#define CONFIG_SYS_LONGHELP /* undef to save memory */
443#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
444#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
445#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Scott Wood96b8a052007-04-16 14:54:15 -0500446
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
448#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
449#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
450#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Scott Wood96b8a052007-04-16 14:54:15 -0500451
452/*
453 * For booting Linux, the board info and command line data
454 * have to be in the first 8 MB of memory, since this is
455 * the maximum mapped by the Linux kernel during initialization.
456 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Scott Wood96b8a052007-04-16 14:54:15 -0500458
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Scott Wood96b8a052007-04-16 14:54:15 -0500460
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#ifdef CONFIG_SYS_66MHZ
Scott Wood96b8a052007-04-16 14:54:15 -0500462
463/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
464/* 0x62040000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_HRCW_LOW (\
Scott Wood96b8a052007-04-16 14:54:15 -0500466 0x20000000 /* reserved, must be set */ |\
467 HRCWL_DDRCM |\
468 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
469 HRCWL_DDR_TO_SCB_CLK_2X1 |\
470 HRCWL_CSB_TO_CLKIN_2X1 |\
471 HRCWL_CORE_TO_CSB_2X1)
472
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
Scott Woode4c09502008-06-30 14:13:28 -0500474
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#elif defined(CONFIG_SYS_33MHZ)
Scott Wood96b8a052007-04-16 14:54:15 -0500476
477/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
478/* 0x65040000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_HRCW_LOW (\
Scott Wood96b8a052007-04-16 14:54:15 -0500480 0x20000000 /* reserved, must be set */ |\
481 HRCWL_DDRCM |\
482 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
483 HRCWL_DDR_TO_SCB_CLK_2X1 |\
484 HRCWL_CSB_TO_CLKIN_5X1 |\
485 HRCWL_CORE_TO_CSB_2X1)
486
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 5)
Scott Woode4c09502008-06-30 14:13:28 -0500488
Scott Wood96b8a052007-04-16 14:54:15 -0500489#endif
490
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_HRCW_HIGH_BASE (\
Scott Wood96b8a052007-04-16 14:54:15 -0500492 HRCWH_PCI_HOST |\
493 HRCWH_PCI1_ARBITER_ENABLE |\
494 HRCWH_CORE_ENABLE |\
Scott Wood96b8a052007-04-16 14:54:15 -0500495 HRCWH_BOOTSEQ_DISABLE |\
496 HRCWH_SW_WATCHDOG_DISABLE |\
Scott Wood96b8a052007-04-16 14:54:15 -0500497 HRCWH_TSEC1M_IN_RGMII |\
498 HRCWH_TSEC2M_IN_RGMII |\
Scott Woode4c09502008-06-30 14:13:28 -0500499 HRCWH_BIG_ENDIAN)
500
501#ifdef CONFIG_NAND_SPL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200502#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
Wolfgang Denk4b070802008-08-14 14:41:06 +0200503 HRCWH_FROM_0XFFF00100 |\
504 HRCWH_ROM_LOC_NAND_SP_8BIT |\
505 HRCWH_RL_EXT_NAND)
Scott Woode4c09502008-06-30 14:13:28 -0500506#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200507#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
Wolfgang Denk4b070802008-08-14 14:41:06 +0200508 HRCWH_FROM_0X00000100 |\
509 HRCWH_ROM_LOC_LOCAL_16BIT |\
510 HRCWH_RL_EXT_LEGACY)
Scott Woode4c09502008-06-30 14:13:28 -0500511#endif
Scott Wood96b8a052007-04-16 14:54:15 -0500512
513/* System IO Config */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
515#define CONFIG_SYS_SICRL SICRL_USBDR /* Enable Internal USB Phy */
Scott Wood96b8a052007-04-16 14:54:15 -0500516
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200517#define CONFIG_SYS_HID0_INIT 0x000000000
518#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
Wolfgang Denka7676ea2007-05-16 01:16:53 +0200519 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
Scott Wood96b8a052007-04-16 14:54:15 -0500520
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521#define CONFIG_SYS_HID2 HID2_HBE
Scott Wood96b8a052007-04-16 14:54:15 -0500522
Becky Bruce31d82672008-05-08 19:02:12 -0500523#define CONFIG_HIGH_BATS 1 /* High BATs supported */
524
Scott Wood96b8a052007-04-16 14:54:15 -0500525/* DDR @ 0x00000000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200526#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
527#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Scott Wood96b8a052007-04-16 14:54:15 -0500528
529/* PCI @ 0x80000000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200530#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
531#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
532#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
533#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Scott Wood96b8a052007-04-16 14:54:15 -0500534
535/* PCI2 not supported on 8313 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200536#define CONFIG_SYS_IBAT3L (0)
537#define CONFIG_SYS_IBAT3U (0)
538#define CONFIG_SYS_IBAT4L (0)
539#define CONFIG_SYS_IBAT4U (0)
Scott Wood96b8a052007-04-16 14:54:15 -0500540
541/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200542#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
543#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)
Scott Wood96b8a052007-04-16 14:54:15 -0500544
545/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Scott Woodc1230982009-03-31 17:49:36 -0500546#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200547#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
Scott Wood96b8a052007-04-16 14:54:15 -0500548
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200549#define CONFIG_SYS_IBAT7L (0)
550#define CONFIG_SYS_IBAT7U (0)
Scott Wood96b8a052007-04-16 14:54:15 -0500551
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200552#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
553#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
554#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
555#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
556#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
557#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
558#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
559#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
560#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
561#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
562#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
563#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
564#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
565#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
566#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
567#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Scott Wood96b8a052007-04-16 14:54:15 -0500568
569/*
570 * Internal Definitions
571 *
572 * Boot Flags
573 */
574#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
575#define BOOTFLAG_WARM 0x02 /* Software reboot */
576
577/*
578 * Environment Configuration
579 */
580#define CONFIG_ENV_OVERWRITE
581
582#define CONFIG_ETHADDR 00:E0:0C:00:95:01
Scott Wood96b8a052007-04-16 14:54:15 -0500583#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
Scott Wood96b8a052007-04-16 14:54:15 -0500584
585#define CONFIG_IPADDR 10.0.0.2
586#define CONFIG_SERVERIP 10.0.0.1
587#define CONFIG_GATEWAYIP 10.0.0.1
588#define CONFIG_NETMASK 255.0.0.0
589#define CONFIG_NETDEV eth1
590
591#define CONFIG_HOSTNAME mpc8313erdb
592#define CONFIG_ROOTPATH /nfs/root/path
593#define CONFIG_BOOTFILE uImage
594#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
595#define CONFIG_FDTFILE mpc8313erdb.dtb
596
Kim Phillips79f516b2009-08-21 16:34:38 -0500597#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Kim Phillips7fd0bea2008-09-24 08:46:25 -0500598#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Scott Wood96b8a052007-04-16 14:54:15 -0500599#define CONFIG_BAUDRATE 115200
600
601#define XMK_STR(x) #x
602#define MK_STR(x) XMK_STR(x)
603
604#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200605 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
Scott Wood96b8a052007-04-16 14:54:15 -0500606 "ethprime=TSEC1\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200607 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
608 "tftpflash=tftpboot $loadaddr $uboot; " \
609 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
610 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
611 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
612 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
613 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500614 "fdtaddr=780000\0" \
Scott Wood96b8a052007-04-16 14:54:15 -0500615 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
616 "console=ttyS0\0" \
617 "setbootargs=setenv bootargs " \
618 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200619 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
Scott Wood96b8a052007-04-16 14:54:15 -0500620 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
621 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
622
623#define CONFIG_NFSBOOTCOMMAND \
624 "setenv rootdev /dev/nfs;" \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200625 "run setbootargs;" \
626 "run setipargs;" \
Scott Wood96b8a052007-04-16 14:54:15 -0500627 "tftp $loadaddr $bootfile;" \
628 "tftp $fdtaddr $fdtfile;" \
629 "bootm $loadaddr - $fdtaddr"
630
631#define CONFIG_RAMBOOTCOMMAND \
632 "setenv rootdev /dev/ram;" \
633 "run setbootargs;" \
634 "tftp $ramdiskaddr $ramdiskfile;" \
635 "tftp $loadaddr $bootfile;" \
636 "tftp $fdtaddr $fdtfile;" \
637 "bootm $loadaddr $ramdiskaddr $fdtaddr"
638
639#undef MK_STR
640#undef XMK_STR
641
642#endif /* __CONFIG_H */