Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| 5 | * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com> |
| 6 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | /************************************************************************ |
| 11 | * katmai.h - configuration for AMCC Katmai (440SPe) |
| 12 | ***********************************************************************/ |
| 13 | |
| 14 | #ifndef __CONFIG_H |
| 15 | #define __CONFIG_H |
Wolfgang Denk | 83b4cfa | 2007-06-20 18:14:24 +0200 | [diff] [blame] | 16 | |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 17 | /*----------------------------------------------------------------------- |
| 18 | * High Level Configuration Options |
| 19 | *----------------------------------------------------------------------*/ |
| 20 | #define CONFIG_KATMAI 1 /* Board is Katmai */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 21 | #define CONFIG_440 1 /* ... PPC440 family */ |
| 22 | #define CONFIG_440SPE 1 /* Specifc SPe support */ |
Stefan Roese | 2a72e9e | 2010-04-09 14:03:59 +0200 | [diff] [blame] | 23 | #define CONFIG_440SPE_REVA 1 /* Support old Rev A. */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 24 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 25 | #define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */ |
Stefan Roese | 490f204 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 26 | |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 27 | #define CONFIG_SYS_TEXT_BASE 0xFFFA0000 |
| 28 | |
Stefan Roese | 490f204 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 29 | /* |
Stefan Roese | 5d812b8 | 2008-07-09 17:33:57 +0200 | [diff] [blame] | 30 | * Enable this board for more than 2GB of SDRAM |
| 31 | */ |
Stefan Roese | 5d812b8 | 2008-07-09 17:33:57 +0200 | [diff] [blame] | 32 | #define CONFIG_VERY_BIG_RAM |
Stefan Roese | 5d812b8 | 2008-07-09 17:33:57 +0200 | [diff] [blame] | 33 | |
| 34 | /* |
Stefan Roese | 490f204 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 35 | * Include common defines/options for all AMCC eval boards |
| 36 | */ |
| 37 | #define CONFIG_HOSTNAME katmai |
| 38 | #include "amcc-common.h" |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 39 | |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 40 | #undef CONFIG_SHOW_BOOT_PROGRESS |
| 41 | |
| 42 | /*----------------------------------------------------------------------- |
| 43 | * Base addresses -- Note these are effective addresses where the |
| 44 | * actual resources get mapped (not physical addresses) |
| 45 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 46 | #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 47 | #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 48 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 49 | #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ |
| 50 | #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ |
| 51 | #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 52 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 53 | #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ |
| 54 | #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ |
| 55 | #define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 56 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 57 | #define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000 |
| 58 | #define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000 |
| 59 | #define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000 |
| 60 | #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000 |
| 61 | #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000 |
| 62 | #define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000 |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 63 | |
Stefan Roese | 9792377 | 2007-10-05 09:18:23 +0200 | [diff] [blame] | 64 | /* base address of inbound PCIe window */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 65 | #define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL |
Stefan Roese | 9792377 | 2007-10-05 09:18:23 +0200 | [diff] [blame] | 66 | |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 67 | /* System RAM mapped to PCI space */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 68 | #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE |
| 69 | #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 70 | #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) |
| 71 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 72 | #define CONFIG_SYS_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 73 | |
| 74 | /*----------------------------------------------------------------------- |
| 75 | * Initial RAM & stack pointer (placed in internal SRAM) |
| 76 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 77 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
| 78 | #define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE |
| 79 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 80 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 81 | |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 82 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
Michael Zaidman | 800eb09 | 2010-09-20 08:51:53 +0200 | [diff] [blame] | 83 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4) |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 84 | |
| 85 | /*----------------------------------------------------------------------- |
| 86 | * Serial Port |
| 87 | *----------------------------------------------------------------------*/ |
Stefan Roese | 550650d | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 88 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 89 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 90 | |
| 91 | /*----------------------------------------------------------------------- |
| 92 | * DDR SDRAM |
| 93 | *----------------------------------------------------------------------*/ |
| 94 | #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 95 | #define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/ |
Stefan Roese | 2721a68 | 2007-03-08 10:07:18 +0100 | [diff] [blame] | 96 | #define CONFIG_DDR_ECC 1 /* with ECC support */ |
Stefan Roese | 845c6c9 | 2008-01-05 09:12:41 +0100 | [diff] [blame] | 97 | #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 98 | #undef CONFIG_STRESS |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 99 | |
| 100 | /*----------------------------------------------------------------------- |
| 101 | * I2C |
| 102 | *----------------------------------------------------------------------*/ |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame] | 103 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 104 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 105 | #define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 106 | |
| 107 | #define IIC0_BOOTPROM_ADDR 0x50 |
| 108 | #define IIC0_ALT_BOOTPROM_ADDR 0x54 |
| 109 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 110 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0x50) |
| 111 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
| 112 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 |
| 113 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 114 | |
Stefan Roese | efe12bc | 2009-11-09 14:15:42 +0100 | [diff] [blame] | 115 | /* I2C bootstrap EEPROM */ |
| 116 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50 |
| 117 | #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0 |
| 118 | #define CONFIG_4xx_CONFIG_BLOCKSIZE 8 |
| 119 | |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 120 | /* I2C RTC */ |
| 121 | #define CONFIG_RTC_M41T11 1 |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 122 | #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ |
| 123 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
| 124 | #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 125 | |
| 126 | /* I2C DTT */ |
| 127 | #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 128 | #define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 129 | /* |
| 130 | * standard dtt sensor configuration - bottom bit will determine local or |
| 131 | * remote sensor of the ADM1021, the rest determines index into |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 132 | * CONFIG_SYS_DTT_ADM1021 array below. |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 133 | */ |
| 134 | #define CONFIG_DTT_SENSORS { 0, 1 } |
| 135 | |
| 136 | /* |
| 137 | * ADM1021 temp sensor configuration (see dtt/adm1021.c for details). |
| 138 | * there will be one entry in this array for each two (dummy) sensors in |
| 139 | * CONFIG_DTT_SENSORS. |
| 140 | * |
| 141 | * For Katmai board: |
| 142 | * - only one ADM1021 |
| 143 | * - i2c addr 0x18 |
| 144 | * - conversion rate 0x02 = 0.25 conversions/second |
| 145 | * - ALERT ouput disabled |
| 146 | * - local temp sensor enabled, min set to 0 deg, max set to 85 deg |
| 147 | * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg |
| 148 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 149 | #define CONFIG_SYS_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} } |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 150 | |
| 151 | /*----------------------------------------------------------------------- |
| 152 | * Environment |
| 153 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 5a1aceb | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 154 | #define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 155 | |
Stefan Roese | 490f204 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 156 | /* |
| 157 | * Default environment variables |
| 158 | */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 159 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
Stefan Roese | 490f204 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 160 | CONFIG_AMCC_DEF_ENV \ |
| 161 | CONFIG_AMCC_DEF_ENV_POWERPC \ |
Stefan Roese | 490f204 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 162 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ |
Stefan Roese | fc21cd5 | 2010-08-03 10:29:50 +0200 | [diff] [blame] | 163 | "kernel_addr=ff000000\0" \ |
| 164 | "fdt_addr=ff1e0000\0" \ |
| 165 | "ramdisk_addr=ff200000\0" \ |
Grzegorz Bernacki | 6efc1fc | 2007-09-07 18:35:37 +0200 | [diff] [blame] | 166 | "pciconfighost=1\0" \ |
Stefan Roese | d4cb2d1 | 2007-10-13 16:43:23 +0200 | [diff] [blame] | 167 | "pcie_mode=RP:RP:RP\0" \ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 168 | "" |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 169 | |
Jon Loeliger | bc234c1 | 2007-07-04 22:32:51 -0500 | [diff] [blame] | 170 | /* |
Stefan Roese | 490f204 | 2008-06-06 15:55:03 +0200 | [diff] [blame] | 171 | * Commands additional to the ones defined in amcc-common.h |
Jon Loeliger | 079a136 | 2007-07-10 10:12:10 -0500 | [diff] [blame] | 172 | */ |
Jon Loeliger | bc234c1 | 2007-07-04 22:32:51 -0500 | [diff] [blame] | 173 | #define CONFIG_CMD_DATE |
Stefan Roese | e372286 | 2010-07-22 19:06:14 +0200 | [diff] [blame] | 174 | #define CONFIG_CMD_ECCTEST |
Jon Loeliger | bc234c1 | 2007-07-04 22:32:51 -0500 | [diff] [blame] | 175 | #define CONFIG_CMD_PCI |
Jon Loeliger | bc234c1 | 2007-07-04 22:32:51 -0500 | [diff] [blame] | 176 | #define CONFIG_CMD_SDRAM |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 177 | |
| 178 | #define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 179 | #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */ |
| 180 | #define CONFIG_HAS_ETH0 |
| 181 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
| 182 | #define CONFIG_PHY_RESET_DELAY 1000 |
| 183 | #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ |
| 184 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 185 | |
| 186 | /*----------------------------------------------------------------------- |
| 187 | * FLASH related |
| 188 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 189 | #define CONFIG_SYS_FLASH_CFI |
Jean-Christophe PLAGNIOL-VILLARD | 00b1883 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 190 | #define CONFIG_FLASH_CFI_DRIVER |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 191 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| 192 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 193 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 194 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} |
| 195 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 196 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 197 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 198 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 199 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 200 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 201 | |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 202 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 203 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 204 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 205 | |
| 206 | /* Address and size of Redundant Environment Sector */ |
Jean-Christophe PLAGNIOL-VILLARD | 0e8d158 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 207 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
| 208 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 209 | |
| 210 | /*----------------------------------------------------------------------- |
| 211 | * PCI stuff |
| 212 | *----------------------------------------------------------------------- |
| 213 | */ |
| 214 | /* General PCI */ |
Gabor Juhos | 842033e | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 215 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 216 | #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ |
Grzegorz Bernacki | 6efc1fc | 2007-09-07 18:35:37 +0200 | [diff] [blame] | 217 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 218 | |
| 219 | /* Board-specific PCI */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 220 | #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */ |
| 221 | #undef CONFIG_SYS_PCI_MASTER_INIT |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 222 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 223 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ |
| 224 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */ |
| 225 | /* #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_DEVICEID */ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 226 | |
| 227 | /* |
| 228 | * NETWORK Support (PCI): |
| 229 | */ |
| 230 | /* Support for Intel 82557/82559/82559ER chips. */ |
| 231 | #define CONFIG_EEPRO100 |
| 232 | |
| 233 | /*----------------------------------------------------------------------- |
| 234 | * Xilinx System ACE support |
| 235 | *----------------------------------------------------------------------*/ |
| 236 | #define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 237 | #define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */ |
| 238 | #define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 239 | |
| 240 | /*----------------------------------------------------------------------- |
| 241 | * External Bus Controller (EBC) Setup |
| 242 | *----------------------------------------------------------------------*/ |
| 243 | |
| 244 | /* Memory Bank 0 (Flash) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 245 | #define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 246 | EBC_BXAP_TWT_ENCODE(7) | \ |
| 247 | EBC_BXAP_BCE_DISABLE | \ |
| 248 | EBC_BXAP_BCT_2TRANS | \ |
| 249 | EBC_BXAP_CSN_ENCODE(0) | \ |
| 250 | EBC_BXAP_OEN_ENCODE(0) | \ |
| 251 | EBC_BXAP_WBN_ENCODE(0) | \ |
| 252 | EBC_BXAP_WBF_ENCODE(0) | \ |
| 253 | EBC_BXAP_TH_ENCODE(0) | \ |
| 254 | EBC_BXAP_RE_DISABLED | \ |
| 255 | EBC_BXAP_SOR_DELAYED | \ |
| 256 | EBC_BXAP_BEM_WRITEONLY | \ |
| 257 | EBC_BXAP_PEN_DISABLED) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 258 | #define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 259 | EBC_BXCR_BS_16MB | \ |
| 260 | EBC_BXCR_BU_RW | \ |
| 261 | EBC_BXCR_BW_16BIT) |
| 262 | |
| 263 | /* Memory Bank 1 (Xilinx System ACE controller) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 264 | #define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \ |
Stefan Roese | d216862 | 2007-04-19 09:53:52 +0200 | [diff] [blame] | 265 | EBC_BXAP_TWT_ENCODE(4) | \ |
| 266 | EBC_BXAP_BCE_DISABLE | \ |
| 267 | EBC_BXAP_BCT_2TRANS | \ |
| 268 | EBC_BXAP_CSN_ENCODE(0) | \ |
| 269 | EBC_BXAP_OEN_ENCODE(0) | \ |
| 270 | EBC_BXAP_WBN_ENCODE(0) | \ |
| 271 | EBC_BXAP_WBF_ENCODE(0) | \ |
| 272 | EBC_BXAP_TH_ENCODE(0) | \ |
| 273 | EBC_BXAP_RE_DISABLED | \ |
| 274 | EBC_BXAP_SOR_NONDELAYED | \ |
| 275 | EBC_BXAP_BEM_WRITEONLY | \ |
| 276 | EBC_BXAP_PEN_DISABLED) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 277 | #define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE) | \ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 278 | EBC_BXCR_BS_1MB | \ |
| 279 | EBC_BXCR_BU_RW | \ |
| 280 | EBC_BXCR_BW_16BIT) |
| 281 | |
| 282 | /*------------------------------------------------------------------------- |
| 283 | * Initialize EBC CONFIG - |
| 284 | * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC |
| 285 | * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 |
| 286 | *-------------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 287 | #define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \ |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 288 | EBC_CFG_PTD_ENABLE | \ |
| 289 | EBC_CFG_RTC_16PERCLK | \ |
| 290 | EBC_CFG_ATC_PREVIOUS | \ |
| 291 | EBC_CFG_DTC_PREVIOUS | \ |
| 292 | EBC_CFG_CTC_PREVIOUS | \ |
| 293 | EBC_CFG_OEO_PREVIOUS | \ |
| 294 | EBC_CFG_EMC_DEFAULT | \ |
| 295 | EBC_CFG_PME_DISABLE | \ |
| 296 | EBC_CFG_PR_16) |
| 297 | |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 298 | /*----------------------------------------------------------------------- |
| 299 | * GPIO Setup |
| 300 | *----------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 301 | #define CONFIG_SYS_GPIO_PCIE_PRESENT0 17 |
| 302 | #define CONFIG_SYS_GPIO_PCIE_PRESENT1 21 |
| 303 | #define CONFIG_SYS_GPIO_PCIE_PRESENT2 23 |
| 304 | #define CONFIG_SYS_GPIO_RS232_FORCEOFF 30 |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 305 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 306 | #define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \ |
| 307 | GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \ |
| 308 | GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \ |
| 309 | GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)) |
| 310 | #define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) |
| 311 | #define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF) |
| 312 | #define CONFIG_SYS_GPIO_ODR 0 |
Stefan Roese | ba58e4c | 2007-03-01 21:11:36 +0100 | [diff] [blame] | 313 | |
Stefan Roese | 4745aca | 2007-02-20 10:57:08 +0100 | [diff] [blame] | 314 | #endif /* __CONFIG_H */ |